CN112382672A - PERC double-sided solar cell and manufacturing method thereof - Google Patents

PERC double-sided solar cell and manufacturing method thereof Download PDF

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CN112382672A
CN112382672A CN202011271350.3A CN202011271350A CN112382672A CN 112382672 A CN112382672 A CN 112382672A CN 202011271350 A CN202011271350 A CN 202011271350A CN 112382672 A CN112382672 A CN 112382672A
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silicon wafer
layer
silicon
diffusion
electrode
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康海涛
胡燕
吴中亚
赵建飞
郭万武
张燕飞
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China Building Materials Junxin Tongcheng Technology Co Ltd
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China Building Materials Junxin Tongcheng Technology Co Ltd
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Abstract

The invention relates to a PERC double-sided solar cell and a manufacturing method thereof; the method is characterized in that: the silicon wafer comprises a front electrode, a back electrode and a P-type silicon wafer substrate, wherein one surface of the P-type silicon wafer substrate is sequentially provided with an N-type doping layer, a front silicon dioxide layer and a front silicon nitride layer from inside to outside, and the other surface of the P-type silicon wafer substrate is sequentially provided with a back aluminum oxide layer, a back silicon nitride layer and a back silicon dioxide layer from inside to outside; the front electrode sequentially penetrates through the front silicon nitride layer and the front silicon dioxide layer; the front electrode is connected with the N-type doped layer; the back electrode sequentially penetrates through the back silicon dioxide layer, the back silicon nitride layer and the back aluminum oxide layer; the back electrode is connected with the P-type silicon wafer substrate. The problems that the generation of black spots and black spots cannot be fundamentally eliminated, the manufacturing cost of the silicon wafer is increased and the like caused by the conventional scheme are solved.

Description

PERC double-sided solar cell and manufacturing method thereof
Technical Field
The invention relates to a solar cell, in particular to a PERC double-sided solar cell and a manufacturing method thereof.
Background
Generally, the mainstream product in the photovoltaic industry at present is a P-type single crystal PERC (passivated emitter and reactor Cell, also called passivated emitter and back Cell) solar Cell, and after the PERC Cell is rapidly developed in recent years, the global PERC Cell capacity reaches one hundred GW, and the continuous increase trend of the photoelectric conversion efficiency of the PERC Cell is in bottleneck. The efficiency of the power-assisted PERC battery in the new technology needs to be continuously improved, and the high cost performance advantage of the PERC battery is kept. In addition, the current PERC solar cell is manufactured by adopting a plurality of complex process flows, pollution and damage are caused to the PERC cell piece in the manufacturing process, so that the yield of the PERC cell is influenced, the manufacturing cost of the PERC cell is increased, the solar cell is not beneficial to continuously reducing the cost, and the development trend of flat-price internet connection is realized. The PERC battery has the characteristics that the bad proportion of black spots and black spots is large, generally the black spots and the black spots are related to cleanliness and cleaning level, the traditional improvement method is to try to reduce the bad rate by means of improving the environment and the cleanliness of a tool clamp, repeatedly cleaning a silicon wafer and the like, but in the improvement process, the manufacturing cost is higher due to additional processes, and the improvement effect is greatly reduced due to the characteristics that some means are not easy to produce in quantity and the like.
In the existing scheme, the cleanliness level of the production environment is improved, and the times of adding a silicon wafer cleaning step in the production process are adopted. Such a solution has the following problems: (1) the generation of black spots and black spots can not be eliminated fundamentally, and the manufacturing cost of the silicon wafer is increased.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a PERC double-sided solar cell and a manufacturing method thereof, and aims to solve the problems that the generation of black spots and black spots cannot be fundamentally eliminated, the manufacturing cost of a silicon wafer is increased and the like in the prior art.
The technical scheme adopted by the invention is as follows:
a PERC bifacial solar cell;
the silicon wafer comprises a front electrode, a back electrode and a P-type silicon wafer substrate, wherein one surface of the P-type silicon wafer substrate is sequentially provided with an N-type doping layer, a front silicon dioxide layer and a front silicon nitride layer from inside to outside, and the other surface of the P-type silicon wafer substrate is sequentially provided with a back aluminum oxide layer, a back silicon nitride layer and a back silicon dioxide layer from inside to outside; the front electrode sequentially penetrates through the front silicon nitride layer and the front silicon dioxide layer; the front electrode is connected with the N-type doped layer; the back electrode sequentially penetrates through the back silicon dioxide layer, the back silicon nitride layer and the back aluminum oxide layer; the back electrode is connected with the P-type silicon wafer substrate.
A method for manufacturing a PERC double-sided solar cell;
when the PERC double-sided solar cell is manufactured, the manufacturing method of the PERC double-sided solar cell comprises the following steps:
step S1: surface texturing; texturing and cleaning the P-type silicon wafer by using a texturing and cleaning machine;
step S2: diffusing; the diffusion process comprises two times of diffusion;
high-temperature phosphorus diffusion: nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace, and oxygen is filled into the diffusion furnace;
selective laser diffusion: selectively diffusing and irradiating the front electrode area of the silicon wafer by a high-energy laser; selective diffusion back sheet resistance: 70-80 omega;
step S3: etching and polishing; the etching and polishing process sequentially comprises etching and polishing;
etching: respectively corroding the back surface of the silicon wafer and the edge of the silicon wafer by 49% of hydrofluoric acid liquid by mass percent;
polishing: polishing the back surface of the silicon wafer by using 47 mass percent of potassium hydroxide and polishing additives; back surface reflectance: 40-45%;
step S4: preparing a back laminated film; respectively preparing an alumina film layer and a silicon nitride film layer on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method;
step S5: preparing double-sided silicon dioxide and performing heat treatment; the double-sided silicon dioxide preparation and heat treatment process sequentially comprises double-sided silicon dioxide preparation and heat treatment;
preparing double-sided silicon dioxide; the silicon chip is placed in a high-temperature diffusion furnace; depositing silicon dioxide films on the front side of the silicon wafer and the back side of the silicon wafer respectively by a thermal oxidation method;
heat treatment; filling hydrogen-nitrogen mixed gas into the high-temperature diffusion furnace; flow rate of hydrogen-nitrogen mixed gas: 3000-: 500 ℃, heat treatment time: 30 min;
step S6: preparing a front silicon nitride layer; preparing a silicon nitride layer on the front side of the silicon wafer by adopting atomic layer deposition equipment;
step S7: laser grooving on the back; locally grooving the laminated passivation film on the back of the silicon wafer by using a high-energy laser;
step S8: preparing front and back electrodes; back printing a back electrode and an aluminum grid line on the back; printing an electrode and a silver grid line on the front side; and sintering to obtain the finished product.
The further technical scheme is as follows: in the step S1, the P-type silicon wafer is immersed in a solution with a concentration: 1.0-1.5 wt%, temperature: corroding the surface of the P-type silicon wafer into a plurality of conical surface appearances in a sodium hydroxide solution at the temperature of 70-90 ℃; the reaction time of the P-type silicon wafer is as follows: 200 and 400s, the reflectivity of the P-type silicon wafer is as follows: 11 to 12 percent.
The further technical scheme is as follows: in the high-temperature phosphorus diffusion of the step S2, nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace in the high-temperature diffusion step, and oxygen is filled into the diffusion furnace; nitrogen flow rate: 500-800sccm, oxygen flow: 600-1000sccm, reaction time: 80-100min, temperature: 700 ℃ and 800 ℃, diffusion sheet resistance: 110-.
The further technical scheme is as follows: in the step S4, preparing an aluminum oxide film layer on the back surface of the silicon wafer by using an atomic layer deposition device and using a mixed medium of trimethylaluminum and nitrous oxide; the thickness of the aluminum oxide film layer is 10nm, and the refractive index of the aluminum oxide film layer is as follows: 1.65; respectively preparing silicon nitride film layers on the back surfaces of the silicon wafers by adopting a mixed medium of silane and ammonia gas through atomic layer deposition equipment; the thickness of the silicon nitride film layer is 80nm, and the refractive index of the silicon nitride film layer is as follows: 2.10.
the further technical scheme is as follows: in the step S5, the silicon wafer is placed in a high-temperature diffusion furnace; depositing a silicon dioxide film on the front surface of the silicon wafer by adopting a thermal oxidation method; oxygen flow rate: 1000-: 100-300pa, thermal oxidation temperature: 700 ℃, time: 25min, the thickness of silicon dioxide is 3 nm.
The further technical scheme is as follows: in step S6, the deposition temperature: 450-: 1000-: 3500-5000sccm, pressure: 1500-: 500-700 s; thickness: 80nm, refractive index: 2.09.
the further technical scheme is as follows: in step S7, the back laser pattern parameters are: number of lines: 120-; the diameter of the light spot: 10-35 μm, spacing of laser lines: 500-700 μm.
The further technical scheme is as follows: in the step S8, printing an aluminum gate line and a silver back electrode screen printing plate structure on the back surface of the silicon wafer by using a screen printing device; number of silver back poles: 6-10, the number of aluminum grids: 120-; printing a silver grid line and a back aluminum grid line structure on the front side of the silicon wafer through screen printing equipment; the number of front silver main grid lines is as follows: 6-10 silver secondary grid lines: 120-.
The invention has the following beneficial effects: the invention designs a PERC double-sided solar cell, which adopts one surface of a P-type silicon wafer substrate to be sequentially provided with an N-type doping layer, a front silicon dioxide layer and a front silicon nitride layer from inside to outside, and the other surface of the P-type silicon wafer substrate to be sequentially provided with a back aluminum oxide layer, a back silicon nitride layer and a back silicon dioxide layer from inside to outside. The front electrode sequentially penetrates through the front silicon nitride layer and the front silicon dioxide layer. The front electrode is connected with the N-type doped layer. The back electrode sequentially penetrates through the back silicon dioxide layer, the back silicon nitride layer and the back aluminum oxide layer. The back electrode is connected with the P-type silicon wafer substrate. The PERC bifacial solar cell brings the following effects: (1) the uneven surface is formed on the P-type silicon wafer, so that the light receiving area of the P-type silicon wafer is greatly increased, and reflection is reduced, and the conversion efficiency of the solar cell is improved; (2) the phosphorus oxychloride can be uniformly distributed in the diffusion furnace, and the phosphorus oxychloride is fully oxidized at high temperature by charging oxygen into the diffusion furnace, so that the phosphorus oxychloride can be fully decomposed, and meanwhile, the phosphorus pentoxide can fully react with the silicon wafer; (3) phosphorus is inevitably diffused on all surfaces of the P-type silicon wafer in the high-temperature diffusion step, photo-generated electrons collected by the front surface of the PN junction flow to the back surface of the PN junction along the region with phosphorus diffused on the edge to cause short circuit, and the phosphorus on the edge of the P-type silicon wafer is completely removed through etching, so that the reduction of parallel resistance caused by the short circuit of the PN junction is avoided; (4) the phosphorosilicate glass is formed on the surface of the P-type silicon wafer in the high-temperature diffusion step, the existence of the phosphorosilicate glass can increase the reflectivity, and the phosphorosilicate glass on the front surface is removed through etching, so that preparation can be made for preparing silicon nitride, and the generation of color difference pieces is effectively reduced; (5) the preparation of the back laminated film is carried out, except for passivating the back to reduce the back surface recombination rate and the saturated dangling bond, carrying out secondary reflection on incident long-wave-band sunlight and increasing light absorption, the very important point is that the back is protected after the back functional layer film is deposited, so that micro particles can be effectively prevented from being directly contacted with the back of a silicon wafer, the problem that the exposed back is exposed outside for a long time in the subsequent process is avoided, the probability that the back is polluted by the micro particles is reduced, and defective products of black spots and black spots in a finished battery are reduced; (6) performing double-sided thermal oxidation process treatment on the front surface and the back surface of the silicon wafer, wherein a hydrogen passivation step is added in the thermal oxidation process, meanwhile, performing hydrogen-nitrogen mixed gas annealing treatment on the front surface and the back surface, saturating the surface dangling bonds, and simultaneously performing heat treatment annealing on the prepared functional layer film, so that the structural arrangement of the functional layer film material is improved, thereby improving the quality of the functional layer film material and further improving the passivation effect of the functional layer film material on the surface of the silicon wafer; (7) the hydrogen-nitrogen mixed gas annealing treatment is added while the thermal oxidation treatment is carried out on the front surface and the back surface, the silicon dioxide film can effectively reduce the front recombination rate, reduce the interface state density and prolong the minority carrier lifetime, the hydrogen-nitrogen mixed gas annealing treatment can play a role of hydrogen passivation, hydrogen atoms can saturate surface dangling bonds and enter a silicon wafer body to passivate a recombination center, the in-vivo defects and recombination centers are reduced, the atoms in a film material can be rearranged by annealing treatment of a back functional layer film material in the hydrogen-nitrogen mixed gas atmosphere, the quality of the film material is improved, so that the functional layer film material can play better effects of field passivation and chemical passivation, the recombination center and the dangling bonds of the silicon wafer are reduced, and the minority carrier lifetime is prolonged, so that the electrical property of the battery is improved; (8) the front surface of the solar cell adopts a silicon dioxide and silicon nitride film layer structure to play roles of antireflection and PID resistance, and non-hydrogen source reaction gas is added in the preparation process to reduce the use amount of hydrogen-containing source gas, so that redundant hydrogen atoms in the cell are reduced, and the effect of improving the cell LeTID phenomenon can be achieved; (9) the high-energy laser irradiates the surface of the silicon wafer with a hole or a groove through a laser beam with higher energy density, a film layer on the front surface of the silicon wafer is punched to expose out of a silicon wafer substrate, a back electric field is in contact with the silicon substrate through the hole or the groove on the film, and the silicon substrate can form good ohmic contact with an aluminum back field after the back electric field is printed and sintered; (10) in the electrode preparation step, the back electrode uses the burn-through type electrode slurry, so that the back dielectric layer slotting contact procedure can be omitted, the process manufacturing process is simple, in addition, the back electrode is designed into an electrode grid shape by the traditional full back electric field, so that the double sides of the solar cell can generate electricity, the output power of the whole solar cell is additionally improved, the slurry on the silicon wafer can be dried through sintering the silicon wafer, the organic components of the slurry are burnt out, and the slurry and the silicon wafer form good ohmic contact.
Drawings
FIG. 1 is a flow chart of the present invention.
Detailed Description
The following describes a specific embodiment of the present embodiment with reference to the drawings.
FIG. 1 is a flow chart of the present invention. Referring to fig. 1, the present invention discloses a PERC bifacial solar cell. The PERC double-sided solar cell comprises a front electrode, a back electrode and a P-type silicon wafer substrate, wherein an N-type doping layer, a front silicon dioxide layer and a front silicon nitride layer are sequentially arranged on one surface of the P-type silicon wafer substrate from inside to outside, and a back aluminum oxide layer, a back silicon nitride layer and a back silicon dioxide layer are sequentially arranged on the other surface of the P-type silicon wafer substrate from inside to outside; the front electrode sequentially penetrates through the front silicon nitride layer and the front silicon dioxide layer; the front electrode is connected with the N-type doped layer; the back electrode sequentially penetrates through the back silicon dioxide layer, the back silicon nitride layer and the back aluminum oxide layer; the back electrode is connected with the P-type silicon wafer substrate.
One surface of the P-type silicon wafer substrate is the upper surface of the P-type silicon wafer substrate. An N-type doped layer, a front silicon dioxide layer and a front silicon nitride layer are arranged on the upper surface of the P-type silicon wafer substrate from bottom to top. The upper surface of the P-type silicon wafer substrate is attached to the lower surface of the N-type doped layer. The upper surface of the N-type doped layer is attached to the lower surface of the front silicon dioxide layer. The upper surface of the front silicon dioxide layer is attached to the lower surface of the front silicon nitride layer. The front electrode penetrates through the front silicon nitride layer and the front silicon dioxide layer in the vertical direction. The lower end of the front electrode is connected with the upper end of the N-type doped layer. The lower surface of the front electrode is attached to the upper surface of the N-type doped layer.
The other surface of the P-type silicon wafer substrate is the lower surface of the P-type silicon wafer substrate. The lower surface of the P-type silicon wafer substrate is provided with a back aluminum oxide layer, a back silicon nitride layer and a back silicon dioxide layer from top to bottom. The lower surface of the P-type silicon wafer substrate is attached to the upper surface of the back alumina layer. The lower surface of the back aluminum oxide layer is attached to the upper surface of the back silicon nitride layer. The lower surface of the back silicon nitride layer is attached to the upper surface of the back silicon dioxide layer. The back electrode passes through the back silicon dioxide layer, the back silicon nitride layer and the back aluminum oxide layer in the up-down direction. The upper end of the back electrode is connected with the lower end of the P-type silicon wafer substrate. The upper surface of the back electrode is attached to the lower surface of the P-type silicon wafer substrate.
When the PERC double-sided solar cell is manufactured, the manufacturing method of the PERC double-sided solar cell comprises the following steps:
step S1: and (4) surface texture. And (3) texturing the surface of the P-type silicon wafer by using a texturing cleaning machine.
In step S1, the P-type silicon wafer immersion concentration: 1.0-1.5 wt%, temperature: in a sodium hydroxide solution at the temperature of 70-90 ℃, the surface of the P-type silicon wafer is corroded into a plurality of conical surface appearances. Reaction time of the P-type silicon wafer: 200-400s, the reflectivity of the P-type silicon wafer: 11 to 12 percent.
The surface appearance of the cone is a pyramid suede. The surface of the P-type silicon wafer can be formed with a conical surface topography by a texturing cleaning machine. The uneven surface is formed on the P-type silicon wafer, so that the light receiving area of the P-type silicon wafer is greatly increased, the reflection is reduced, and the conversion efficiency of the solar cell is improved.
Step S2: and (4) diffusion. The diffusion process includes two diffusions.
High-temperature phosphorus diffusion: the nitrogen drives the phosphorus oxychloride to be filled into the diffusion furnace, and the oxygen is filled into the diffusion furnace.
Selective laser diffusion: and selectively diffusing and irradiating the front electrode area of the silicon wafer by using a high-energy laser. Selective diffusion back sheet resistance: 70-80 omega.
In the high-temperature phosphorus diffusion of the step S2, nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace in the high-temperature diffusion step, and oxygen is filled into the diffusion furnace. Nitrogen flow rate: 500-800sccm, oxygen flow: 600-1000sccm, reaction time: 80-100min, temperature: 700 ℃ and 800 ℃, diffusion sheet resistance: 110-.
The phosphorus oxychloride is decomposed into phosphorus pentachloride and phosphorus pentoxide at high temperature, and the phosphorus pentoxide is deposited on the surface of the silicon wafer. Phosphorus pentoxide reacts with the silicon wafer to generate silicon dioxide and phosphorus atoms, and phosphorus-silicon glass is formed on the surface of the silicon wafer, and the phosphorus atoms are diffused into the silicon wafer.
The nitrogen is inert gas, and the nitrogen drives the phosphorus oxychloride to be filled into the diffusion furnace, so that the phosphorus oxychloride can be uniformly distributed in the diffusion furnace. The phosphorus oxychloride is fully oxidized at high temperature by charging oxygen into the diffusion furnace.
The temperature is increased to between 700 and 800 ℃, so that the phosphorus oxychloride can be fully decomposed, and the phosphorus pentoxide can be fully reacted with the silicon wafer.
And a non-collector region and a collector region are formed on the surface of the P-type silicon wafer. Heavy doping can be formed in the collection electrode region by laser selective diffusion.
Step S3: and etching and polishing. The etching and polishing process sequentially comprises etching and polishing.
Etching: and respectively corroding the back surface of the silicon wafer and the edge of the silicon wafer by 49 mass percent of hydrofluoric acid liquid.
Polishing: and polishing the back surface of the silicon wafer by 47 mass percent of potassium hydroxide and polishing additives. Back surface reflectance: 40-45 percent.
All surfaces (including edges) of the P-type silicon wafer will inevitably be diffused with phosphorus during the high temperature diffusion step. Photo-generated electrons collected by the front side of the PN junction can flow to the back side of the PN junction along the region with the phosphorus diffused along the edge to cause a short circuit. After etching, phosphorus on the edge of the P-type silicon wafer can be removed completely, and reduction of parallel resistance caused by PN junction short circuit is avoided.
And forming phosphorosilicate glass on the surface of the P-type silicon wafer in the high-temperature diffusion step. The reflectivity can be increased due to the existence of the phosphorosilicate glass, the phosphorosilicate glass on the front surface is removed through etching, preparation can be made for preparing silicon nitride, and the generation of a color difference piece is effectively reduced.
The groove type cleaning machine polishes the back of the P-type silicon wafer, improves the flatness of the back of the P-type silicon wafer and enables the back of the P-type silicon wafer to be flat.
The polishing additive was NP-110 type polishing additive manufactured by Shaoxing Tuppon electronics technologies, Inc. The polishing additive comprises potassium carbonate, vitamins, protease, cleaning agent, surface cleaning agent and water.
Step S4: and preparing a back laminated film. And respectively preparing an alumina film layer and a silicon nitride film layer on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method.
In step S4, an aluminum oxide film is formed on the back surface of the silicon wafer by using a mixed medium of trimethylaluminum and nitrous oxide through an atomic layer deposition apparatus. The thickness of the aluminum oxide film layer is 10nm, and the refractive index of the aluminum oxide film layer is as follows: 1.65. and respectively preparing silicon nitride film layers on the back surfaces of the silicon wafers by adopting a mixed medium of silane and ammonia gas through atomic layer deposition equipment. The thickness of the silicon nitride film layer is 80nm, and the refractive index of the silicon nitride film layer is as follows: 2.10.
after the etching and polishing in step S3, the surface of the silicon wafer is very clean and flat, and is very sensitive to external dust, particles, dust and other microparticles, and once the microparticles fall on the back of the silicon wafer, the microparticles will cause contamination and form black spots and black spots in the end of the finished battery. After the etching and polishing in the step S3, the back laminated film preparation in the step S4 is performed, except that the back is passivated to reduce the back surface recombination rate and the saturation dangling bonds, and incident long-wave-band sunlight is secondarily reflected to increase light absorption, what is important is that the back is protected after the back functional layer film is deposited first, so that the microparticles can be effectively prevented from directly contacting the back of the silicon wafer, the exposed back is prevented from being exposed to the outside for a long time in the subsequent process, the probability of the back being polluted by the microparticles is reduced, and defective products of black spots and black spots in the finished battery are reduced.
And performing a back passivation process, sequentially depositing an aluminum oxide film and a silicon nitride film on the back, passivating the back and protecting the back at the same time, so as to prevent the back of the subsequent process from being directly exposed in the air and being polluted by dust particles to form black spots and black spots.
Step S5: preparing double-sided silicon dioxide and carrying out heat treatment. The double-sided silicon dioxide preparation and heat treatment process sequentially comprises double-sided silicon dioxide preparation and heat treatment.
And (3) preparing double-sided silicon dioxide. The silicon chip is placed in a high-temperature diffusion furnace. And respectively depositing silicon dioxide films on the front side and the back side of the silicon wafer by a thermal oxidation method.
And (6) heat treatment. And filling hydrogen-nitrogen mixed gas into the high-temperature diffusion furnace. Flow rate of hydrogen-nitrogen mixed gas: 3000-: 500 ℃, heat treatment time: and (3) 30 min.
In step S5, the silicon wafer is placed in a high temperature diffusion furnace. And depositing a silicon dioxide film on the front surface of the silicon wafer by a thermal oxidation method. Oxygen flow rate: 1000-: 100-300pa, thermal oxidation temperature: 700 ℃, time: 25min, the thickness of silicon dioxide is 3 nm.
And performing double-sided thermal oxidation process treatment on the front surface and the back surface of the silicon wafer, wherein a hydrogen passivation step is added in the thermal oxidation process, and meanwhile, performing hydrogen-nitrogen mixed gas annealing treatment on the front surface and the back surface, and performing heat treatment annealing on the prepared functional layer film by using a saturated surface dangling bond, so that the structural arrangement of the functional layer film material is improved, the quality of the functional layer film material is improved, and the passivation effect of the functional layer film material on the surface of the silicon wafer is further improved.
The hydrogen-nitrogen mixed gas is added for annealing treatment while the thermal oxidation treatment is carried out on the front surface and the back surface, so that the silicon dioxide film can effectively reduce the front surface recombination rate, reduce the interface state density and prolong the minority carrier lifetime. The hydrogen-nitrogen mixed gas annealing treatment can play a role in hydrogen passivation, so that hydrogen atoms can saturate surface dangling bonds, and can enter the silicon wafer body to passivate a recombination center, thereby reducing defects and recombination centers in the silicon wafer body. In addition, atoms in the film material can be rearranged by annealing the back functional layer film material in the hydrogen-nitrogen mixed gas atmosphere, the quality of the film material is improved, the functional layer film material can play better effects of field passivation and chemical passivation, the silicon wafer composite center and dangling bonds are reduced, the minority carrier lifetime is prolonged, and the electrical property of the battery is improved.
Step S6: and preparing a front silicon nitride layer. And preparing a silicon nitride layer on the front side of the silicon wafer by adopting atomic layer deposition equipment.
In step S6, deposition temperature: 450-: 1000-: 3500-5000sccm, pressure: 1500-: 500- & lt700 & gt. Thickness: 80nm, refractive index: 2.09.
the front surface of the solar cell adopts a silicon dioxide and silicon nitride film layer structure, and the solar cell plays roles of antireflection and PID resistance. Due to the fact that non-hydrogen source reaction gas is added in the preparation process, the using amount of hydrogen-containing source gas is reduced, redundant hydrogen atoms in the battery piece are reduced, and the effect of improving the LeTID phenomenon of the battery piece can be achieved. The refractive index of the front surface of the solar cell adopting the silicon dioxide and silicon nitride film layer structure can be regulated, more incident light can be absorbed, photo-generated carriers are increased, and the short-circuit current of the cell is improved.
The silicon nitride layer is used as an antireflection film, has good optical performance and chemical performance, can play a role in passivation on the surface of a silicon wafer, and improves the short-circuit current of the solar cell.
By setting the deposition temperature at 450-550 ℃, the minority carrier lifetime in the polysilicon is less affected by the lower deposition temperature. And the energy consumption is lower during production, the deposition speed is higher, and the thickness of the silicon nitride layer is uniform.
Step S7: and laser grooving on the back. And (3) locally grooving the laminated passivation film on the back of the silicon wafer by using a high-energy laser.
In step S7, the back laser pattern parameters are: number of lines: 120-. The diameter of the light spot: 10-35 μm, spacing of laser lines: 500-700 μm.
The high-energy laser irradiates the surface of the silicon wafer with holes or grooves through a laser beam with higher energy density, the film layer on the front surface of the silicon wafer is punched to expose the silicon wafer substrate, and the back electric field is in contact with the silicon substrate through the holes or grooves on the film. After the back electric field printing sintering is completed, the silicon substrate can form good ohmic contact with the aluminum back field.
Step S8: and preparing front and back electrodes. And printing a back electrode and an aluminum grid line on the back surface. And printing an electrode and a silver grid line on the front surface. And sintering to obtain the finished product.
In step S8, an aluminum gate line and a silver back electrode screen printing plate structure are printed on the back surface of the silicon wafer by a screen printing apparatus. Number of silver back poles: 6-10, the number of aluminum grids: 120-. And printing a silver grid line and a back aluminum grid line structure on the front surface of the silicon wafer by using screen printing equipment. The number of front silver main grid lines is as follows: 6-10 silver secondary grid lines: 120-.
In the electrode preparation step, the back electrode uses the burn-through electrode slurry, so that the back dielectric layer slotting contact procedure can be omitted, and the process manufacturing process is simple. In addition, the back electrode is designed into an electrode grid shape by the traditional full back electric field, so that the double sides of the solar cell can generate electricity, and the output power of the whole solar cell is additionally improved.
By sintering the silicon wafer, the slurry on the silicon wafer can be dried, and the organic components of the slurry are burnt out, so that the slurry and the silicon wafer form good ohmic contact.
The techniques of the present invention are illustrated below in several examples.
The first embodiment:
step S1: and (4) surface texture. And (3) texturing the surface of the P-type silicon wafer by using a texturing cleaning machine.
In step S1, the P-type silicon wafer immersion concentration: 1.1 wt%, temperature: in a sodium hydroxide solution at 70 ℃, the surface of the P-type silicon wafer is corroded into a plurality of conical surface appearances. Reaction time of the P-type silicon wafer: 220s, P-type silicon wafer reflectivity: 11 percent.
Step S2: and (4) diffusion. The diffusion process includes two diffusions.
High-temperature phosphorus diffusion: the nitrogen drives the phosphorus oxychloride to be filled into the diffusion furnace, and the oxygen is filled into the diffusion furnace.
Selective laser diffusion: and selectively diffusing and irradiating the front electrode area of the silicon wafer by using a high-energy laser. Selective diffusion back sheet resistance: 70 omega.
In the high-temperature phosphorus diffusion of the step S2, nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace in the high-temperature diffusion step, and oxygen is filled into the diffusion furnace. Nitrogen flow rate: 500sccm, oxygen flow: 700sccm, reaction time: 85min, temperature: 700 ℃, diffusion sheet resistance: 110 omega.
Step S3: and etching and polishing. The etching and polishing process sequentially comprises etching and polishing.
Etching: and respectively corroding the back surface of the silicon wafer and the edge of the silicon wafer by 49 mass percent of hydrofluoric acid liquid.
Polishing: and polishing the back surface of the silicon wafer by 47 mass percent of potassium hydroxide and polishing additives. Back surface reflectance: 40 percent.
Step S4: and preparing a back laminated film. And respectively preparing an alumina film layer and a silicon nitride film layer on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method.
In step S4, an aluminum oxide film is formed on the back surface of the silicon wafer by using a mixed medium of trimethylaluminum and nitrous oxide through an atomic layer deposition apparatus. The thickness of the aluminum oxide film layer is 10nm, and the refractive index of the aluminum oxide film layer is as follows: 1.65. and respectively preparing silicon nitride film layers on the back surfaces of the silicon wafers by adopting a mixed medium of silane and ammonia gas through atomic layer deposition equipment. The thickness of the silicon nitride film layer is 80nm, and the refractive index of the silicon nitride film layer is as follows: 2.10.
step S5: preparing double-sided silicon dioxide and carrying out heat treatment. The double-sided silicon dioxide preparation and heat treatment process sequentially comprises double-sided silicon dioxide preparation and heat treatment.
And (3) preparing double-sided silicon dioxide. The silicon chip is placed in a high-temperature diffusion furnace. And respectively depositing silicon dioxide films on the front side and the back side of the silicon wafer by a thermal oxidation method.
And (6) heat treatment. And filling hydrogen-nitrogen mixed gas into the high-temperature diffusion furnace. Flow rate of hydrogen-nitrogen mixed gas: 3000sccm, temperature in high temperature diffusion furnace: 500 ℃, heat treatment time: and (3) 30 min.
In step S5, the silicon wafer is placed in a high temperature diffusion furnace. And depositing a silicon dioxide film on the front surface of the silicon wafer by a thermal oxidation method. Oxygen flow rate: 1200sccm, pressure: 120pa, thermal oxidation temperature: 700 ℃, time: 25min, the thickness of silicon dioxide is 3 nm.
Step S6: and preparing a front silicon nitride layer. And preparing a silicon nitride layer on the front side of the silicon wafer by adopting atomic layer deposition equipment.
In step S6, deposition temperature: 450 ℃, silane flow rate: 1000sccm, ammonia gas flow: 3500sccm, pressure: 1500pa, deposition time: for 500 s. Thickness: 80nm, refractive index: 2.09.
step S7: and laser grooving on the back. And (3) locally grooving the laminated passivation film on the back of the silicon wafer by using a high-energy laser.
In step S7, the back laser pattern parameters are: number of lines: 130 roots. The diameter of the light spot: 15 μm, spacing of laser lines: 540 μm.
Step S8: and preparing front and back electrodes. And printing a back electrode and an aluminum grid line on the back surface. And printing an electrode and a silver grid line on the front surface. And sintering to obtain the finished product.
In step S8, an aluminum gate line and a silver back electrode screen printing plate structure are printed on the back surface of the silicon wafer by a screen printing apparatus. Number of silver back poles: 6, the number of aluminum grids: 120 roots of the Chinese yam. And printing a silver grid line and a back aluminum grid line structure on the front surface of the silicon wafer by using screen printing equipment. The number of front silver main grid lines is as follows: 6 silver secondary grid lines: 120 roots of the Chinese yam.
Second embodiment:
step S1: and (4) surface texture. And (3) texturing the surface of the P-type silicon wafer by using a texturing cleaning machine.
In step S1, the P-type silicon wafer immersion concentration: 1.4 wt%, temperature: in a sodium hydroxide solution at 85 ℃, the surface of the P-type silicon wafer is corroded into a plurality of conical surface appearances. Reaction time of the P-type silicon wafer: 380s, reflectivity of the P-type silicon wafer: 12 percent.
Step S2: and (4) diffusion. The diffusion process includes two diffusions.
High-temperature phosphorus diffusion: the nitrogen drives the phosphorus oxychloride to be filled into the diffusion furnace, and the oxygen is filled into the diffusion furnace.
Selective laser diffusion: and selectively diffusing and irradiating the front electrode area of the silicon wafer by using a high-energy laser. Selective diffusion back sheet resistance: 80 omega.
In the high-temperature phosphorus diffusion of the step S2, nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace in the high-temperature diffusion step, and oxygen is filled into the diffusion furnace. Nitrogen flow rate: 750sccm, oxygen flow: 950sccm, reaction time: 95min, temperature: 800 ℃, diffusion sheet resistance: 130 omega.
Step S3: and etching and polishing. The etching and polishing process sequentially comprises etching and polishing.
Etching: and respectively corroding the back surface of the silicon wafer and the edge of the silicon wafer by 49 mass percent of hydrofluoric acid liquid.
Polishing: and polishing the back surface of the silicon wafer by 47 mass percent of potassium hydroxide and polishing additives. Back surface reflectance: 45 percent.
Step S4: and preparing a back laminated film. And respectively preparing an alumina film layer and a silicon nitride film layer on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method.
In step S4, an aluminum oxide film is formed on the back surface of the silicon wafer by using a mixed medium of trimethylaluminum and nitrous oxide through an atomic layer deposition apparatus. The thickness of the aluminum oxide film layer is 10nm, and the refractive index of the aluminum oxide film layer is as follows: 1.65. and respectively preparing silicon nitride film layers on the back surfaces of the silicon wafers by adopting a mixed medium of silane and ammonia gas through atomic layer deposition equipment. The thickness of the silicon nitride film layer is 80nm, and the refractive index of the silicon nitride film layer is as follows: 2.10.
step S5: preparing double-sided silicon dioxide and carrying out heat treatment. The double-sided silicon dioxide preparation and heat treatment process sequentially comprises double-sided silicon dioxide preparation and heat treatment.
And (3) preparing double-sided silicon dioxide. The silicon chip is placed in a high-temperature diffusion furnace. And respectively depositing silicon dioxide films on the front side and the back side of the silicon wafer by a thermal oxidation method.
And (6) heat treatment. And filling hydrogen-nitrogen mixed gas into the high-temperature diffusion furnace. Flow rate of hydrogen-nitrogen mixed gas: 5000sccm, temperature in high temperature diffusion furnace: 500 ℃, heat treatment time: and (3) 30 min.
In step S5, the silicon wafer is placed in a high temperature diffusion furnace. And depositing a silicon dioxide film on the front surface of the silicon wafer by a thermal oxidation method. Oxygen flow rate: 2800sccm, pressure: 250pa, thermal oxidation temperature: 700 ℃, time: 25min, the thickness of silicon dioxide is 3 nm.
Step S6: and preparing a front silicon nitride layer. And preparing a silicon nitride layer on the front side of the silicon wafer by adopting atomic layer deposition equipment.
In step S6, deposition temperature: 550 ℃, silane flow rate: 2000sccm, ammonia gas flow: 5000sccm, pressure: 2000pa, deposition time: 700 s. Thickness: 80nm, refractive index: 2.09.
step S7: and laser grooving on the back. And (3) locally grooving the laminated passivation film on the back of the silicon wafer by using a high-energy laser.
In step S7, the back laser pattern parameters are: number of lines: 160 roots. The diameter of the light spot: 30 μm, spacing of laser lines: 650 μm.
Step S8: and preparing front and back electrodes. And printing a back electrode and an aluminum grid line on the back surface. And printing an electrode and a silver grid line on the front surface. And sintering to obtain the finished product.
In step S8, an aluminum gate line and a silver back electrode screen printing plate structure are printed on the back surface of the silicon wafer by a screen printing apparatus. Number of silver back poles: 10, the number of aluminum grids: 160 roots. And printing a silver grid line and a back aluminum grid line structure on the front surface of the silicon wafer by using screen printing equipment. The number of front silver main grid lines is as follows: 10 silver secondary grid lines: 150 roots.
In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed" and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The foregoing description is illustrative of the present invention and is not to be construed as limiting thereof, the scope of the invention being defined by the appended claims, which may be modified in any manner without departing from the basic structure thereof.

Claims (9)

1. A PERC bifacial solar cell, characterized by: the silicon wafer comprises a front electrode, a back electrode and a P-type silicon wafer substrate, wherein one surface of the P-type silicon wafer substrate is sequentially provided with an N-type doping layer, a front silicon dioxide layer and a front silicon nitride layer from inside to outside, and the other surface of the P-type silicon wafer substrate is sequentially provided with a back aluminum oxide layer, a back silicon nitride layer and a back silicon dioxide layer from inside to outside; the front electrode sequentially penetrates through the front silicon nitride layer and the front silicon dioxide layer; the front electrode is connected with the N-type doped layer; the back electrode sequentially penetrates through the back silicon dioxide layer, the back silicon nitride layer and the back aluminum oxide layer; the back electrode is connected with the P-type silicon wafer substrate.
2. A method for manufacturing a PERC double-sided solar cell is characterized by comprising the following steps: when the PERC double-sided solar cell is manufactured, the manufacturing method of the PERC double-sided solar cell comprises the following steps:
step S1: surface texturing; texturing and cleaning the P-type silicon wafer by using a texturing and cleaning machine;
step S2: diffusing; the diffusion process comprises two times of diffusion;
high-temperature phosphorus diffusion: nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace, and oxygen is filled into the diffusion furnace;
selective laser diffusion: selectively diffusing and irradiating the front electrode area of the silicon wafer by a high-energy laser; selective diffusion back sheet resistance: 70-80 omega;
step S3: etching and polishing; the etching and polishing process sequentially comprises etching and polishing;
etching: respectively corroding the back surface of the silicon wafer and the edge of the silicon wafer by 49% of hydrofluoric acid liquid by mass percent;
polishing: polishing the back surface of the silicon wafer by using 47 mass percent of potassium hydroxide and polishing additives; back surface reflectance: 40-45%;
step S4: preparing a back laminated film; respectively preparing an alumina film layer and a silicon nitride film layer on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method;
step S5: preparing double-sided silicon dioxide and performing heat treatment; the double-sided silicon dioxide preparation and heat treatment process sequentially comprises double-sided silicon dioxide preparation and heat treatment;
preparing double-sided silicon dioxide; the silicon chip is placed in a high-temperature diffusion furnace; depositing silicon dioxide films on the front side of the silicon wafer and the back side of the silicon wafer respectively by a thermal oxidation method;
heat treatment; filling hydrogen-nitrogen mixed gas into the high-temperature diffusion furnace; flow rate of hydrogen-nitrogen mixed gas: 3000-: 500 ℃, heat treatment time: 30 min;
step S6: preparing a front silicon nitride layer; preparing a silicon nitride layer on the front side of the silicon wafer by adopting atomic layer deposition equipment;
step S7: laser grooving on the back; locally grooving the laminated passivation film on the back of the silicon wafer by using a high-energy laser;
step S8: preparing front and back electrodes; back printing a back electrode and an aluminum grid line on the back; printing an electrode and a silver grid line on the front side; and sintering to obtain the finished product.
3. The method of claim 2, wherein: in the step S1, the P-type silicon wafer is immersed in a solution with a concentration: 1.0-1.5 wt%, temperature: corroding the surface of the P-type silicon wafer into a plurality of conical surface appearances in a sodium hydroxide solution at the temperature of 70-90 ℃; the reaction time of the P-type silicon wafer is as follows: 200 and 400s, the reflectivity of the P-type silicon wafer is as follows: 11 to 12 percent.
4. The method of claim 3, wherein:
in the high-temperature phosphorus diffusion of the step S2, nitrogen drives phosphorus oxychloride to be filled into the diffusion furnace in the high-temperature diffusion step, and oxygen is filled into the diffusion furnace; nitrogen flow rate: 500-800sccm, oxygen flow: 600-1000sccm, reaction time: 80-100min, temperature: 700 ℃ and 800 ℃, diffusion sheet resistance: 110-.
5. The method of claim 4, wherein: in the step S4, preparing an aluminum oxide film layer on the back surface of the silicon wafer by using an atomic layer deposition device and using a mixed medium of trimethylaluminum and nitrous oxide; the thickness of the aluminum oxide film layer is 10nm, and the refractive index of the aluminum oxide film layer is as follows: 1.65; respectively preparing silicon nitride film layers on the back surfaces of the silicon wafers by adopting a mixed medium of silane and ammonia gas through atomic layer deposition equipment; the thickness of the silicon nitride film layer is 80nm, and the refractive index of the silicon nitride film layer is as follows: 2.10.
6. the method of claim 5, wherein: in the step S5, the silicon wafer is placed in a high-temperature diffusion furnace; depositing a silicon dioxide film on the front surface of the silicon wafer by adopting a thermal oxidation method; oxygen flow rate: 1000-: 100-300pa, thermal oxidation temperature: 700 ℃, time: 25min, the thickness of silicon dioxide is 3 nm.
7. The method of claim 6, wherein: in step S6, the deposition temperature: 450-: 1000-: 3500-5000sccm, pressure: 1500-: 500-700 s; thickness: 80nm, refractive index: 2.09.
8. the method of claim 7, wherein:
in step S7, the back laser pattern parameters are: number of lines: 120-; the diameter of the light spot: 10-35 μm, spacing of laser lines: 500-700 μm.
9. The method of claim 8, wherein: in the step S8, printing an aluminum gate line and a silver back electrode screen printing plate structure on the back surface of the silicon wafer by using a screen printing device; number of silver back poles: 6-10, the number of aluminum grids: 120-; printing a silver grid line and a back aluminum grid line structure on the front side of the silicon wafer through screen printing equipment; the number of front silver main grid lines is as follows: 6-10 silver secondary grid lines: 120-.
CN202011271350.3A 2020-11-13 2020-11-13 PERC double-sided solar cell and manufacturing method thereof Pending CN112382672A (en)

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