CN118156270A - 一种薄膜覆晶接合封装电路连接结构及其制造方法 - Google Patents
一种薄膜覆晶接合封装电路连接结构及其制造方法 Download PDFInfo
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Abstract
本发明公开了一种薄膜覆晶接合封装电路连接结构及其制造方法,包括薄膜覆晶接合封装载带,所述薄膜覆晶接合封装载带包括基材和多个金属线路,多个所述金属线路设置于所述基材上且沿基材面向外延伸并相邻排列;芯片,位于薄膜覆晶接合封装载带的下方;多个金凸块,设置于所述芯片朝向所述基材的一侧上并与基材上对应的金属线路电性连接;转接线路,位于所述多个金凸块和所述芯片之间并与所述芯片电性连接,用于将金属线路与金凸块和芯片相连接从而降低金属线路密度、用于将两个金属线路连接或者用于增加线路整体的阻值且缩短金属线路的长度;本发明能够降低线路密度,进而降低载带制作成本与提升良率。
Description
技术领域
本发明涉及芯片封装技术领域,具体涉及一种薄膜覆晶接合封装电路连接结构及其制造方法。
背景技术
近年来薄膜晶体管液晶显示器(Thin film transistor liquid crystaldisplay, TFT-LCD)液晶屏幕产业迅速发展,其原理是是藉由晶体管输出电压控制液晶排列方向,进而控制透光度产生灰阶之色彩效果。薄膜晶体管液晶显示器驱动芯片使用薄膜覆晶接合(Chip on film, COF)方式封装,一端透过类似双面胶之导电胶黏贴于液晶面板之玻璃基板上,另一端则与控制电路链接。
当屏幕分辨率越来越高,为了节省成本,驱动芯片使用颗数自然是愈少愈好,因此必须提高封装脚数, 这就导致负责驱动液晶分子的驱动芯片其输入/输出(I/O)数量越来越多, 负责连接芯片与周边电路的薄膜覆晶接合封装的金属线路数量与密度亦同步增加。为于固定面积下容纳更多的金属线路,必须研发更精密的工艺,缩短金属线路的宽度与间距, 以容纳更多的金属线路通过,但此方式一方面因蚀刻线路之技术提高了研发成本,而尺寸愈来愈小,导致负责连接信号的金属线路其宽度与间隙亦越来越小,造成金属线路阻值升高与金属线路间绝缘值降低,进而使产品本身特性变差与可靠度降低。
发明内容
技术目的:针对现有技术的不足,本发明公开了一种薄膜覆晶接合封装电路连接结构及其制造方法,能够降低金属线路密度,降低制作成本。
技术方案:为实现上述技术目的,本发明采用了如下技术方案:
一种薄膜覆晶接合封装电路连接结构,包括
薄膜覆晶接合封装载带,包括基材和多个金属线路,多个所述金属线路设置于所述基材上且沿基材表面向外延伸并相邻排列;
芯片,位于薄膜覆晶接合封装载带的下方;
多个金凸块,设置于所述芯片朝向所述基材的一侧上并与基材上对应的金属线路电性连接;
转接线路,位于所述多个金凸块和所述芯片之间并与所述芯片电性连接,用于将金属线路与金凸块和芯片相连接从而降低金属线路密度、用于将两个金属线路连接或者用于增加线路整体的阻值且缩短金属线路的长度。
优选地,所述金属线路和所述转接线路的具体结构为:
一缩短的金属线路,且两侧与其相邻的金属线路宽度增加;
所述转接线路设置于缩短的金属线路下方芯片上,且通过金凸块与所述缩短的金属线路电性连接。
优选地,所述金属线路和所述转接线路的具体结构为:
横向排布具有一定间隔且位于同一水平线上的两个金属线路和位于两者之间竖向排布的金属线路;
所述转接线路设置于所述两个金属线路间隔下方的芯片上,且两端分别通过两个金属线路对应的金凸块与两个金属线路电性相连。
优选地,述金属线路和所述转接线路的具体结构为:
一断开分成两部分的金属线路;
所述转接线路设置于两部分金属线路间隔下方的芯片上,且两端分别通过两部分金属线路对应的金凸块使得断开的金属线路电性相连。
本发明还提供一种薄膜覆晶接合封装电路连接结构的制造方法,应用于上述的一种薄膜覆晶接合封装电路连接结构,包括:
提供芯片和薄膜覆晶接合封装载带,所述芯片的一侧表面上设置有多个金凸块,并在芯片与多个金凸块之间设置转接线路,所述薄膜覆晶接合封装载带包括基材和多个金属线路,多个所述金属线路设置于所述基材上且沿基材表面向外延伸并相邻排列;
进行接合程序,将所述芯片设置多个金凸块的一侧与基材上的金属线路相对设置,将金凸块与所述金属线路对准,并通过热压合以使所述芯片通过所述转接线路和多个金凸块与各个金属线路之间相接合,从而与所述基材电性连接;
封装胶体,填充封装胶体于所述芯片与所述薄膜覆晶接合封装载带之间,且所述封装胶体覆盖所述各所述多个金凸块和所述多个金属线路,最后再烘烤硬化。
有益效果:本发明的所提供的一种薄膜覆晶接合封装电路连接结构及其制造方法具有如下有益效果:
本发明通过在芯片上设置转接线路,当薄膜覆晶结合封装载带的金属线路密度过高时,通过将部分金属线路利用金凸块和芯片上的转接线路所代替,进而能够缩短金属线路的长度,从而能够增大相邻金属线路的间距以及金属线路的宽度,降低金属线路的密度,进而降低薄膜覆晶结合封装载带的制作成本,提升良率。
现有的薄膜覆晶结合封装载带的金属线路之间走线为2D平面,不同的金属导线之间无法交叉,否则将会造成短路的状况,而本发明通过设置转接线路,金属导线之间通过3D连线方式能够通过转接线路实现交叉连接的目的且彼此之间不会互相干扰。
现有技术中当膜覆晶结合封装载带的金属线路因特殊需求要达到特定的电阻值时,需要增加金属线路的长度从而导致载带面积增大,本发明通过设置转接线路将部分金属线路代替,而且转接线路的单位阻值较大,从而实现用较短的长度达到相同的阻值,能够节省大量薄膜覆晶结合封装载带的面积。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍。
图1为本发明薄膜覆晶接合封装电路连接结构与外接装置的模块图;
图2A为现有技术薄膜覆晶接合封装电路连接结构的俯视图;
图2B为现有技术薄膜覆晶接合封装电路连接结构的剖面图
图3为现有技术薄膜覆晶接合封装电路连接结构的立体图;
图4A为本发明实施例一中薄膜覆晶接合封装电路连接结构的俯视图;
图4B为本发明实施例一中薄膜覆晶接合封装电路连接结构的剖面图;
图5为本发明实施例一中薄膜覆晶接合封装电路连接结构的立体图;
图6A为本发明实施例一中具体实施结构更改结构前的立体图;
图6B为本发明实施例一中具体实施结构更改结构后的立体图;
图7A为本发明实施例二中薄膜覆晶接合封装电路连接结构的俯视图;
图7B为本发明实施例二中薄膜覆晶接合封装电路连接结构的剖面图;
图8为本发明实施例二中薄膜覆晶接合封装电路连接结构的立体图;
图9A为本发明实施例三中现有技术薄膜覆晶接合封装电路连接结构的俯视图;
图9B为本发明实施例三中薄膜覆晶接合封装电路连接结构的的俯视图;
图10为为本发明实施例三中现有技术薄膜覆晶接合封装电路连接结构的立体图;
图11为本发明实施例三中薄膜覆晶接合封装电路连接结构的立体图;
图12为本发明薄膜覆晶接合封装电路连接结构的封装结构图。
图中:100、薄膜覆晶接合封装载带;110、基材;120、金属线路;200、金凸块;300、芯片。
具体实施方式
下面通过一较佳实施例的方式并结合附图来更清楚完整地说明本发明,但并不因此将本发明限制在所述的实施例范围之中。
一种薄膜覆晶接合封装电路连接结构,包括
薄膜覆晶接合封装载带100,包括基材110和多个金属线路120,多个所述金属线路120设置于所述基材110上且沿基材110表面向外延伸并相邻排列;
芯片300,位于薄膜覆晶接合封装载带100的下方;
多个金凸块200,设置于所述芯片300朝向所述基材110的一侧上并与基材110上对应的金属线路120电性连接;
转接线路310,位于所述多个金凸块200和所述芯片300之间并与所述芯片300电性连接,用于将金属线路120与金凸块200和芯片300相连接从而降低金属线路120密度、用于将两个金属线路120连接或者用于增加线路整体的阻值且缩短金属线路120的长度。
如图1所示为本发明薄膜覆晶接合封装电路连接结构与外接装置的模块图,包含薄膜覆晶接合封装载带100与芯片300,其中薄膜覆晶接合封装载带100的功能为连接驱动电路即输入端、芯片和液晶面板即输出端,其实现方式为于基材110上生成的金属线路120,所述金属线路120一端与驱动电路或液晶面板相连, 另一端透过金凸块200与芯片300上的转接电路310相连接。
驱动芯片封装时将薄膜覆晶接合封装载带100上的金属线路120的端点与金凸块相连接, 金凸块200另一端则与芯片200上的转接线路310相连接, 转接线路310末端则连接另一金凸块200, 金凸块200另一端则连结薄膜覆晶接合封装载带100的金属线路120,以此方式构成一个信号连接回路。
薄膜覆晶接合封装载带100上的金属线路120除了将芯片300上之信号与外部相连接外,因应设计上的需求,利用制作金凸块200的方式可达成芯片300区域不同方式的连接。如图1中的金属线路120将芯片300输出端的金凸块a、c与输入端的金凸块200相连接,或通过金属线路120将金凸块b直接连接至驱动电路,或是金属线路d、e和f将芯片内部的金凸块200相连结。
如图2A至图3所示,为现有技术中现薄膜覆晶接合封装电路连接结构,包括薄膜覆晶接合封装载带100、金凸块200和芯片300,所述薄膜覆晶接合封装载带100包括基材110和设置在基材110上的金属线路120,基材110通过金属线路120和金凸块200与芯片300相连接,从而将芯片的信号与外界相连,现有技术这种薄膜覆晶接合封装电路连接结构为了容纳更多的金属线路导致金属线路的宽度以及金属线路之间的间距越来越小。
实施例
如图4A至图6B所示,为本发明提供的一种薄膜覆晶接合封装电路连接结构,包括薄膜覆晶接合封装载带100、金凸块200、芯片300以及设置在芯片300上的转接线路310,所述薄膜覆晶接合封装载带包括基材110和设置在基材110上的金属线路120,所述金属线路120和所述转接线路310的具体结构为:
一缩短的金属线路b,且两侧与其相邻的金属线路a和c的宽度增加;
所述转接线路310设置于缩短的金属线路b下方的芯片300上,且通过金凸块200与所述缩短的金属线路b电性连接。
在有多个金属线路120相邻排列的时候,根据预期设计的金属线路120 的数量和间距和制程工艺可达到的数量与间距进行对比,若金属线路120的宽度或与临近的金属线路之间的间距小于线路制作工艺水平时,例如设计的线路间距为20微米,但是制程能力只能达到22微米时,即可采用本发明提出的结构,缩短某些金属线路120的长度用转接线路310取代,同时增加剩余金属线路120的宽度或整体的空间,以此满足制程工艺的限制。
如图4A至图5所示,有三条金属线路a、b和c,若因为金属线路的制程能力限制,无法在特定区域容纳3条金属线路时,此时可以在芯片300特定位置上制作金凸块200,将金属线路b与所述金凸块200连接后截断,截断后金属线路b的长度得以缩短,缩短后多余的空间便可以供金属线路a和金属线路c使用,两者可以根据制程工艺和需求对线路宽度以及线路之间的空间进行自适应调整,例如宽度:空间=1:1、宽度:空间=2:1或宽度:空间=1:2等等,最终达到制程能力需求。
传统薄膜覆晶接合封装载带的金属线路将芯片的信号与外界相连接, 当驱动芯片密度越来越大, 导致金属线路宽度与线路间隙越来越小时, 利用本发明的电路连接结构, 将部分金属线路b的信号利用金凸块与芯片上的转接线路予以替代,如此可降低薄膜覆晶接合封装载带金属线路密集度, 增加金属线路a,c宽度与线路间隙, 进一步降低薄膜覆晶结合封装载带技术门坎与成本。
如图6A所示,例如某区域中有10条金属线路120分别编号为1-10,10条金属线路的宽度均为12微米,金属线路之间的间距为12微米,如图6B所示,将编号为偶数的金属线路的长度缩短,缩短后多出的空间可以分配给临近的金属线路,平均每根金属线路的宽度可增加至24微米,且金属线路之间的距离增加至24微米。
实施例
如图7A至图8所示,为本发明提供的一种薄膜覆晶接合封装电路连接结构,包括薄膜覆晶接合封装载带100、金凸块200、芯片300以及设置在芯片300上的转接线路310,所述薄膜覆晶接合封装载带包括基材110和设置在基材110上的金属线路120,所述金属线路120和所述转接线路310的具体结构为:
横向排布具有一定间隔且位于同一水平线上的两个金属线路d和f以及位于两者之间竖向排布的金属线路e;
所述转接线路310设置于所述两个金属线路d和f间隔下方的芯片300上,且两端分别通过两个金属线路d和f对应的金凸块200与两个金属线路d和f电性相连。
当金属线路d需与金属线路f相连时, 由于金属线路e的存在,导致二者无法相连,通过本发明的此新型设计, 通过金凸块200与转接线路310, 可将金属线路d与金属线路f顺利相连结,并且不会与金属线路e发生短路和干扰。
实施例
如图9A和图10所示,为现有技术一种薄膜覆晶接合封装电路连接结构,当金属线路120因特殊需求例如需要达到特定的电阻值时,现有技术中通常采用增加金属线路120的长度来实现,增加金属线路120的长度则需要占用大量薄膜覆晶接合封装载带的面积,当金属线路较密集时很难达成。
如图9B和图11所示,为本发明提供的一种薄膜覆晶接合封装电路连接结构,包括薄膜覆晶接合封装载带100、金凸块200、芯片300以及设置在芯片300上的转接线路310,所述薄膜覆晶接合封装载带包括基材110和设置在基材110上的金属线路120,所述金属线路120和所述转接线路310的具体结构为:
一断开分成两部分的金属线路120;
所述转接线路310设置于两部分金属线路120间隔下方的芯片300上,且两端分别通过两部分金属线路120对应的金凸块200使得断开的金属线路120电性相连。
通过本发明此新型设计, 将金属线路120以转接线路310予以替代,由于转接线路310的单位阻值较大, 只需要较短长度即可达成相同阻值,故此方式一方面可省下大量薄膜覆晶接合封装载带面积, 另一方面也可使用适当单位阻值的转接线路达到使用最小面积的目的。
在一个具体实施例中,一条金属线路长10毫米,宽10微米,厚8微米,那么该金属线路的电阻约为1.7*10-8 * 1.0*10-2 /(8.0*10-6 * 1.0*10-5 ) = 2.13欧姆,当用本发明中的转接线路310代替时,仅需要设置成长度2微米,宽度16微米即可,因为转接线路310的材料为多晶硅,单位电阻值为13.76欧姆,则长度为2微米宽度为16微米的转接线路310的总阻值为13.76*2/16=2.13欧姆,所以采用本发明的转接线路310可以有效缩短金属线路所用长度,节省空间。
如图12所示,本发明还提供一种薄膜覆晶接合封装电路连接结构的制造方法,应用于上述的一种薄膜覆晶接合封装电路连接结构,包括:
提供芯片300和薄膜覆晶接合封装载带100,所述芯片300的一侧表面上设置有多个金凸块200,并在芯片300与多个金凸块200之间设置转接线路310,所述薄膜覆晶接合封装载带100包括基材110和多个金属线路120,多个所述金属线路120设置于所述基材110上且沿基材110向外延伸并相邻排列;
进行接合程序,将所述芯片300设置多个金凸块200的一侧与基材110上的金属线路120相对设置,将金凸块200与所述金属线路120对准,并通过热压合以使所述芯片300通过所述转接线路310和多个金凸块200与各个金属线路120之间相接合,从而与所述基材110电性连接;
封装胶体,填充封装胶体于所述芯片300与所述薄膜覆晶接合封装载带100之间,且所述封装胶体覆盖所述各所述多个金凸块200和所述多个金属线路120,最后再烘烤硬化。
通过电气绝缘胶材低吸湿特性,封装胶体之后本发明的装置能够阻绝外来的湿气与污染物,并包覆引脚以避免结构被破坏,进而提升本发明装置的可靠度与机械强度。
以上所述仅是本发明的优选实施方式,应当指出:对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (5)
1.一种薄膜覆晶接合封装电路连接结构,其特征在于,包括
薄膜覆晶接合封装载带,包括基材和多个金属线路,多个所述金属线路设置于所述基材上且沿基材表面向外延伸并相邻排列;
芯片,位于薄膜覆晶接合封装载带的下方;
多个金凸块,设置于所述芯片朝向所述基材的一侧上并与基材上对应的金属线路电性连接;
转接线路,位于所述多个金凸块和所述芯片之间并与所述芯片电性连接,用于将金属线路与金凸块和芯片电性连接。
2.根据权利要求1所述的一种薄膜覆晶接合封装电路连接结构,其特征在于,所述金属线路和所述转接线路的具体结构为:
一缩短的金属线路,且两侧与其相邻的金属线路宽度增加;
所述转接线路设置于缩短的金属线路下方芯片上,且通过金凸块与所述缩短的金属线路电性连接。
3.根据权利要求1所述的一种薄膜覆晶接合封装电路连接结构,其特征在于,所述金属线路和所述转接线路的具体结构为:
横向排布具有一定间隔且位于同一水平线上的两个金属线路和位于两者之间竖向排布的金属线路;
所述转接线路设置于所述两个金属线路间隔下方的芯片上,且两端分别通过两个金属线路对应的金凸块与两个金属线路电性相连。
4.根据权利要求1所述的一种薄膜覆晶接合封装电路连接结构,其特征在于,述金属线路和所述转接线路的具体结构为:
一断开分成两部分的金属线路;
所述转接线路设置于两部分金属线路间隔下方的芯片上,且两端分别通过两部分金属线路对应的金凸块使得断开的金属线路电性相连。
5.一种薄膜覆晶接合封装电路连接结构的制造方法,应用于权利要求1-4任一所述的一种薄膜覆晶接合封装电路连接结构,其特征在于,包括:
提供芯片和薄膜覆晶接合封装载带,所述芯片的一侧表面上设置有多个金凸块,并在芯片与多个金凸块之间设置转接线路,所述薄膜覆晶接合封装载带包括基材和多个金属线路,多个所述金属线路设置于所述基材上且沿基材表面向外延伸并相邻排列;
进行接合处理,将所述芯片设置多个金凸块的一侧与基材上的金属线路相对设置,将金凸块与所述金属线路对准,并通过热压合以使所述芯片通过所述转接线路和多个金凸块与各个金属线路之间相接合,从而与所述基材电性连接;
封装胶体,填充封装胶体于所述芯片与所述薄膜覆晶接合封装载带之间,且所述封装胶体覆盖所述各所述多个金凸块和所述多个金属线路,最后再烘烤硬化。
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