CN118113646A

CN118113646A - Slave access method, device, equipment and storage medium

Info

Publication number: CN118113646A
Application number: CN202410242012.9A
Authority: CN
Inventors: 赵前程; 赵鑫鑫; 高晨; 姜凯
Original assignee: Shandong Inspur Science Research Institute Co Ltd
Current assignee: Shandong Inspur Science Research Institute Co Ltd
Priority date: 2024-03-04
Filing date: 2024-03-04
Publication date: 2024-05-31

Abstract

The application discloses a slave access method, a device, equipment and a storage medium, which relate to the technical field of data communication and comprise the following steps: acquiring a data access request for register data sent by an upper computer, and controlling the slave to enter a start bit state from an IDLE state based on the data access request; judging whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line, and entering an address bit after the slave machine successfully; storing address information of the register data, and jumping to a synchronous information domain state after finishing access operation of the register data according to the address information; and in the synchronous information domain state, carrying out assignment processing on the multiplexing signal line based on the data access request and controlling the slave to recover to the IDLE state. In this way, access to the slaves through a variety of serial interfaces by the complex system can be accomplished in accordance with the LPC interface specification.

Description

Slave access method, device, equipment and storage medium

Technical Field

The present invention relates to the field of data communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for accessing a slave.

Background

The X86 architecture (The X86 architecture) processor is highly programmable, has high processing power, good backward compatibility, and its instruction set is more complex than The RISC (Reduced Instruction Set Computer) architecture. The X86 architecture is one of the most widely used instruction set architectures in the computer arts. EPLD (Erasable Programmable Logic Device, i.e., large-scale programmable logic device) is an erasable programmable logic device, and when applied to a large-scale integrated circuit, EPLD has advantages of small size, high reliability, low price, etc.

On a 5G (5 th Generation Mobile Communication Technology, i.e., fifth generation mobile communication technology) baseband board, an X86 processor is commonly used as a main processor, an EPLD is used as a low-speed serial interface for expansion, power-on timing control, and the like, and the X86 processor also realizes read-write access to the EPLD. The LPC (Low pin count) interface is a special interface for the X86 processor to connect to external low-speed devices. In the design of a 5G baseband board, an LPC interface is used for connecting an EPLD, and a register of the EPLD is read through the LPC interface; and the configuration data of the FPGA (Field Programmable GATE ARRAY, i.e., the field programmable gate array) is transmitted using the LPC interface. The LPC interface is also an important interface in the X86 debugging process. In this context, how the X86 processor accesses the external low-speed slave through the LPC interface needs to be addressed.

Disclosure of Invention

In view of the foregoing, an object of the present invention is to provide a slave access method, apparatus, device, and storage medium, which enable an X86 processor to access an external low-speed slave through an LPC interface. The specific scheme is as follows:

In a first aspect, the application discloses a slave access method based on LPC interface communication, which is applied to an X86 processor, wherein the slave is an FPGA or an EPLD logic device, and the method comprises the following steps:

Acquiring a data access request for register data sent by an upper computer, and controlling the slave to enter a start bit state from an IDLE state based on the data access request;

Judging whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line, and entering an address bit after the slave machine successfully;

storing address information of the register data, and jumping to a synchronous information domain state after finishing access operation of the register data according to the address information;

And in the synchronous information domain state, carrying out assignment processing on the multiplexing signal line based on the data access request and controlling the slave to recover to the IDLE state.

Optionally, the X86 processor communicates with the FPGA or EPLD logic device via an LPC bus.

Optionally, the controlling the slave to enter a start bit state from an IDLE state based on the data access request includes:

and carrying out reset release operation through a reset signal based on the data access request, and controlling the slave to enter a start bit state from an IDLE state through a control line.

Optionally, if the data access request is a data write request, the step of skipping to the synchronous information domain state after completing the access operation of the register data according to the address information includes:

the control register is in a low level, and controls the slave to jump to a host data state;

In the host data state, the multiplexing signal line is used for completing the writing operation of the register data according to the address information and then jumping to a first bus switching state;

judging whether the multiplexing signal line is at a high potential or not in the bus switching state;

If not, the method jumps to the synchronous information domain state.

Optionally, if the data access request is a data write request, the performing assignment processing on the multiplexing signal line based on the data access request and controlling the slave to restore to the IDLE state includes:

And jumping to a TAP1_P state, performing assignment processing on the multiplexing signal line in the TAP1_P state, and controlling the slave to recover to the IDLE IDLE state.

Optionally, if the data access request is a data read request, the step of skipping to the synchronous information domain state after completing the access operation of the register data according to the address information includes:

The control register is in a high level, and controls the slave to jump to a second bus switching state to judge whether the multiplexing signal line is in a high potential or not under the condition that the bus switching state is judged;

If not, the method jumps to the synchronous information domain state.

Optionally, if the data access request is a data read request, the performing assignment processing on the multiplexing signal line based on the data access request and controlling the slave to restore to the IDLE state includes:

Jumping to a DATA_P state, reading register DATA sent by the slave machine through a bus in the DATA_P state, and jumping to a TAP1_P state;

And in the TAP1_P state, carrying out assignment processing on the multiplexing signal line and controlling the slave to recover to the IDLE IDLE state.

In a second aspect, the present application discloses a slave access device based on LPC interface communication, applied to an X86 processor, where the slave is an FPGA or EPLD logic device, the device includes:

The request sending module is used for obtaining a data access request for register data sent by the upper computer and controlling the slave computer to enter a start bit state from an IDLE state based on the data access request;

The signal judging module is used for judging whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line and entering an address bit after the slave machine successfully;

The data access module is used for storing the address information of the register data and jumping to a synchronous information domain state after completing the access operation of the register data according to the address information;

and the signal jump module is used for carrying out assignment processing on the multiplexing signal line based on the data access request and controlling the slave to recover to the IDLE IDLE state in the synchronous information domain state.

In a third aspect, the present application discloses an electronic device, comprising:

a memory for storing a computer program;

and the processor is used for executing the computer program to realize the slave access method based on the LPC interface communication.

In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program which, when executed by a processor, implements the foregoing slave access method based on LPC interface communication.

In the application, firstly, a data access request for register data sent by an upper computer is obtained, and the slave computer is controlled to enter a start bit state from an IDLE state based on the data access request; judging whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line, and entering an address bit after the slave machine successfully; storing address information of the register data, and jumping to a synchronous information domain state after finishing access operation of the register data according to the address information; and in the synchronous information domain state, carrying out assignment processing on the multiplexing signal line based on the data access request and controlling the slave to recover to the IDLE state. Therefore, the access operation to the slave machine can be completed by the X86 processor through the LPC interface, the application scene is wider, the method is suitable for the use logic of the slave machines such as the EPLD or the FPGA and the like, the transplanting is convenient, and the requirements of different data transmission can be met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a slave access method based on LPC interface communication;

FIG. 2 is a diagram illustrating a connection between an X86 processor and a slave according to one embodiment of the present disclosure;

FIG. 3 is a flowchart of a specific slave access method based on LPC interface communication according to the present application;

FIG. 4 is a schematic diagram of a slave access device based on LPC interface communication according to the present application;

Fig. 5 is a block diagram of an electronic device according to the present disclosure.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

On a complex system, a commonly used serial interface is similar to I2C (Inter-INTEGRATED CIRCUIT, namely an integrated circuit bus) and SPI (SERIAL PERIPHERAL INTERFACE, namely a serial peripheral interface), and because of more devices and address conflicts of the serial interface, a main controller basically needs to expand and design the serial port through an FPGA or an EPLD. In addition, the power-on time sequence of the system is also controlled by a logic device FPGA or an EPLD. Because of the characteristics of small volume, low price and high reliability of the EPLD, the EPLD is mostly adopted in the power-on control and serial communication expansion design of the system.

The LPC bus has a small number of signals, including LAD [3:0], LFRAME, LRESET, LCLK. LAD [3:0] is a nibble, which is a multiplexed signal line of command, address and data. LFRAME is a control line indicating a new access cycle or ending an erroneous access cycle. LRESET is the reset signal and LCLK is the clock signal of the interface.

Using the LPC interface specification, the domains are as follows: START, cyctype+ DIR, SIZE, TAR, ADDR, CHANGNEL, DATA, SYNC. The START bit START takes one clock cycle, and when the LFRAME signal triggers, all peripheral devices monitor the LAD [3:0] bus to confirm whether the START state is entered. The START state is the last clock edge that samples and reads the LAD [3:0] bus after the LFRAME signal low active state triggers. CYCTYPE +DIR is the type and direction of transmission, taking one clock cycle, and the domain is driven by the host. The SIZE of the SIZE transmission also takes one clock cycle. TAR is bus switching, which takes up two clock cycles, driven by the host when bus control is to be switched to the peripheral device; when control is to be switched to the host, it is driven by the peripheral device. ADDR is an address field, taking 4 clock cycles for I/O access, I/O is a 16-bit address. CHANGNEL is the channel number for transferring DMA, which is used only in DMA transfer. DATA is the DATA field, and since LAD [3:0] is a nibble, transmitting one byte takes two clock cycles. SYNC is a synchronous domain that is used to add latency information and may take several clock cycles.

Referring to fig. 1, the embodiment of the application discloses a slave access method based on LPC interface communication, which is applied to an X86 processor, wherein the slave is an FPGA or EPLD logic device, and the method comprises the following steps:

step S11: and acquiring a data access request for register data sent by an upper computer, and controlling the slave to enter a start bit state from an IDLE state based on the data access request.

In this embodiment, as shown in fig. 2, the X86 processor communicates with the FPGA or EPLD logic device via an LPC bus. That is, the LPC interface host is an X86 processor and the slave is an FPGA or EPLD logic device. Host X86 is processed according to the specified LPC protocol. First, the LPC slave process is divided into IDLE IDLE, START START, ADDR (i.e., address) Address, DATA_H host DATA, TAR_H bus switch, SYNC (i.e., synchronization) synchronization field, DATA_P DATA field, TAR1_P bus switch, TAR2_P bus switch. The controlling the slave to enter a start bit state from an IDLE state based on the data access request includes: and carrying out reset release operation through a reset signal based on the data access request, and controlling the slave to enter a start bit state from an IDLE state through a control line. That is, when IDLE is IDLE, the reset is entered into this state, the signal lines LAD [3:0] are set to the high impedance state, and the associated registers are cleared. After the reset is released and the slave detects that the signal LFRAME is pulled low, the state machine enters the START state from IDLE.

Step S12: and judging whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line, and entering an address bit after the slave machine successfully.

In this embodiment, based on the digital signal and the level signal of the multiplexing signal line, it is determined whether the slave successfully enters the start bit state, and after the success, enters the address bit. That is, if the signal line LAD has 4 0000, the state of the start bit is correct, and it should be noted that, in the next data of the signal line LAD, the highest bit and the highest bit are both high, the level of the first bit is assigned to the DIR register, then the state machine jumps to ADDR, otherwise, the state machine jumps to IDLE.

Step S13: storing the address information of the register data, and jumping to a synchronous information domain state after finishing the access operation of the register data according to the address information.

In this embodiment, after the ADDR state, corresponding address information is stored, and the size of the direction register DIR is detected. If DIR is low, indicating a read operation, the state machine jumps to TAR_H bus switch; if the DIR is high, indicating a write operation, the state machine jumps to the DATA_H bus switch. In a specific embodiment, if the data access request is a data write request, the step of skipping to the synchronous information domain state after completing the access operation of the register data according to the address information includes: the control register is in a low level, and controls the slave to jump to a host data state; in the host data state, the multiplexing signal line is used for completing the writing operation of the register data according to the address information and then jumping to a first bus switching state; judging whether the multiplexing signal line is at a high potential or not in the bus switching state; if not, the method jumps to the synchronous information domain state. That is, during the TAR_H bus switch, it is indicated that the host is currently driving, and the control of the bus is given to the slave, and LAD [3:0] is set high during two clock cycles of the bus switch. During DATA_H, the current writing operation is described, after two clock cycles, the host can write one byte through the signal lines LAD [3:0], and the state machine jumps to the TAR_H state after writing; the state machine switches states at tar_h, i.e. the second bus. If it is detected that the signal lines LAD [3:0] are not high, the jump is made to IDLE. If LAD [3:0] is set high, the delay period value wait_cnt is set, and after 2 clock cycles, the state of SYNC is skipped, namely the state of the synchronous information domain. In another embodiment, if the data access request is a data read request, the step of skipping to the synchronous information domain state after completing the access operation of the register data according to the address information includes: the control register is in a high level, and controls the slave to jump to a second bus switching state to judge whether the multiplexing signal line is in a high potential or not under the condition that the bus switching state is judged; if not, the method jumps to the synchronous information domain state. I.e. the state machine switches states at tar_h, i.e. the second bus. If it is detected that the signal lines LAD [3:0] are not high, the jump is made to IDLE. If LAD [3:0] is set high, the delay period value wait_cnt is set, and after 2 clock cycles, the state of SYNC is skipped.

Step S14: and in the synchronous information domain state, carrying out assignment processing on the multiplexing signal line based on the data access request and controlling the slave to recover to the IDLE state.

In this embodiment, the SYNC state is a synchronous information domain state, and determines to perform delay of several clock cycles according to the delay period value wait_cnt. SYNC state, when detecting that LAD [3:0] is all low, indicates that synchronization is currently completed, and can jump according to DIR value. In a specific embodiment, if the data access request is a data write request, the performing assignment processing on the multiplexing signal line based on the data access request and controlling the slave to restore to the IDLE state includes: and jumping to a TAP1_P state, performing assignment processing on the multiplexing signal line in the TAP1_P state, and controlling the slave to recover to the IDLE IDLE state. That is, when DIR is high, jump to TAP1_P state; in TAP1_P state, LAD [3:0] is assigned 1111 in the first cycle, LAD [3:0] is assigned high impedance state in the second clock cycle, and then jump to IDLE IDLE state. In another embodiment, if the data access request is a data read request, the performing assignment processing on the multiplexing signal line based on the data access request and controlling the slave to restore to the IDLE state includes: jumping to a DATA_P state, reading register DATA sent by the slave machine through a bus in the DATA_P state, and jumping to a TAP1_P state; and in the TAP1_P state, carrying out assignment processing on the multiplexing signal line and controlling the slave to recover to the IDLE IDLE state. That is, when DIR is low, jump to the DATA_P state. In the data_p state, the bus control right is that the slave sends the DATA to be read by the host to the bus, the DATA is sent after two clock cycles, and the state machine enters the TAP1_p state. In TAP1_P state, LAD [3:0] is assigned 1111 in the first cycle, LAD [3:0] is assigned high impedance state in the second clock cycle, and then jump to IDLE IDLE state.

In this embodiment, a data access request for register data sent by an upper computer is first obtained, and the slave is controlled to enter a start bit state from an IDLE state based on the data access request; judging whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line, and entering an address bit after the slave machine successfully; storing address information of the register data, and jumping to a synchronous information domain state after finishing access operation of the register data according to the address information; and in the synchronous information domain state, carrying out assignment processing on the multiplexing signal line based on the data access request and controlling the slave to recover to the IDLE state. Therefore, the access operation to the slave machine can be completed by the X86 processor through the LPC interface, the application scene is wider, the method is suitable for the use logic of the slave machines such as the EPLD or the FPGA and the like, the transplanting is convenient, and the requirements of different data transmission can be met.

Because the EPLD or the FPGA on the non-integrated PS side does not have an integrated serial port controller, the serial port logic is designed independently to occupy resources, and the serial port logic is not required to be designed independently when a processor exists in the system. In a system such as a 5G base station, an X86 processor is used as a core, and can be connected with low-speed equipment such as an external serial port. The upper computer is required to access register data in the EPLD or the FPGA, the X86 processor can be accessed first, the X86 processor and the EPLD or the FPGA are communicated through an LPC interface, and finally, the data access to the EPLD or the FPGA is completed. Accordingly, this embodiment will specifically describe a logic implementation of the slave.

Referring to fig. 3, the embodiment of the application discloses a specific slave access method based on LPC interface communication, which is applied to an X86 processor, wherein the slave is an FPGA or EPLD logic device, and the method comprises the following steps:

The LPC slave process is divided into IDLE IDLE, START START, ADDR address, DATA_H host DATA, TAR_H bus switch, SYNC SYNC field, DATA_P DATA field, TAR1_P bus switch, TAR2_P bus switch. When IDLE is IDLE, reset is entered into this state, the signal lines LAD [3:0] are set to the high impedance state, and the associated registers are cleared. After the reset is released and the slave detects that the signal LFRAME is pulled low, the state machine enters the START state from IDLE. When the method is used for starting, if the signal line LAD is provided with 4 appointed 0000, the starting bit state is correct, in the next data of the signal line LAD, the highest bit and the highest bit are both high level, the level of the first bit is assigned to the DIR register, then the state machine jumps to ADDR, otherwise, the state machine jumps to IDLE. After ADDR state, the corresponding address information is stored, and the size of the direction register DIR is detected, if DIR is low level, the instruction is read operation, and the state machine jumps to TAR_H bus switching; if the DIR is high, indicating a write operation, the state machine jumps to the DATA_H bus switch. During the TAR_H bus switch, it is indicated that the host is currently driving, the control of the bus is given to the slave, and LAD [3:0] is set high during two clock cycles of the bus switch. In DATA_H, which indicates that a write operation is currently performed, the host writes one byte via signal lines LAD [3:0] after two clock cycles, and the state machine jumps to the TAR_H state after writing. When the state machine is in TAR_H, if the signal lines LAD [3:0] are detected not to be in a high level, jumping to an IDLE; if LAD [3:0] is set high, the delay period value wait_cnt is set, and after 2 clock cycles, the state of SYNC is skipped. The SYNC state is a synchronous information field, and determines to delay for several clock cycles according to the delay period value wait_cnt. And a SYNC state, when the LAD [3:0] is detected to be in a low level, indicating that synchronization is completed currently, jumping can be performed according to the value of the DIR, when the DIR is in a high state, jumping to a TAP1_P state, and when the DIR is in a low state, jumping to a DATA_P state. In the data_p state, the bus control right is that the slave sends the DATA to be read by the host to the bus, the DATA is sent after two clock cycles, and the state machine enters the TAP1_p state. In TAP1_P state, LAD [3:0] is assigned 1111 in the first cycle, LAD [3:0] is assigned high impedance state in the second clock cycle, and then jump to IDLE IDLE state.

Therefore, the method based on the LPC interface slave of the X86 processor in the embodiment is suitable for logic design of slaves such as an EPLD or an FPGA, is convenient to transplant, and can meet different data access requirements.

The embodiment of the application also correspondingly discloses a slave access device based on LPC interface communication, which is applied to an X86 processor, wherein the slave is an FPGA or an EPLD logic device and comprises:

A request sending module 11, configured to obtain a data access request for register data sent by an upper computer, and control the slave to enter a start bit state from an IDLE state based on the data access request;

A signal judging module 12, configured to judge whether the slave machine successfully enters a start bit state based on the digital signal and the level signal of the multiplexing signal line, and enter an address bit after the success;

The data access module 13 is configured to store address information of the register data, and jump to a synchronous information domain state after completing an access operation of the register data according to the address information;

And the signal skipping module 14 is configured to perform assignment processing on the multiplexed signal line based on the data access request and control the slave to recover to the IDLE state in the synchronous information domain state.

Therefore, in this embodiment, the access operation to the slave machine can be completed by using the LPC interface through the X86 processor, which has a wider application scenario, is suitable for the logic of the slave machines such as EPLD or FPGA, and is convenient for migration, and can meet the requirements of different data transmission.

In some specific embodiments, the request sending module 11 may be specifically configured to perform a reset release operation by using a reset signal based on the data access request, and control the slave to enter the start bit state from the IDLE state through a control line.

If the data access request is a data write request, in some specific embodiments, the data access module 13 may specifically include:

the host data state jumping unit is used for controlling the register to be in a low level and controlling the slave to jump to a host data state;

The first bus switching unit is used for jumping to a first bus switching state after finishing the writing operation of the register data according to the address information through the multiplexing signal line in the host data state;

a first multiplexed signal line judging unit configured to judge whether the multiplexed signal line is at a high potential in the bus switching state;

and the first information domain jumping unit is used for jumping to the synchronous information domain state if not.

If the data access request is a data write request, in some specific embodiments, the signal skipping module 14 may specifically include:

And the signal direct jump unit is used for jumping to a TAP1_P state, carrying out assignment processing on the multiplexing signal line under the TAP1_P state and controlling the slave to recover to the IDLE IDLE state.

If the data access request is a data read request, in some specific embodiments, the data access module 13 may specifically include:

a second bus switching unit for controlling the register to be at high level and controlling the slave to jump to a second bus switching state

A second multiplexed signal line judging unit configured to judge whether the multiplexed signal line is at a high potential in the bus switching state;

and the second information domain jumping unit is used for jumping to the synchronous information domain state if not.

If the data access request is a data read request, in some specific embodiments, the signal skipping module 14 may specifically include:

A data_p state switching unit for jumping to a data_p state, reading register DATA transmitted from the slave machine through a bus in the data_p state, and then jumping to a TAP1_p state;

And the slave recovery unit is used for carrying out assignment processing on the multiplexing signal line and controlling the slave to recover to the IDLE state under the TAP1_P state.

Further, the embodiment of the present application further discloses an electronic device, and fig. 5 is a block diagram of an electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.

Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is configured to store a computer program that is loaded and executed by the processor 21 to implement relevant steps in the LPC interface communication-based slave access method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.

In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.

The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, and the like, and the storage may be temporary storage or permanent storage.

The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further comprise a computer program capable of performing other specific tasks in addition to the computer program capable of performing the slave access method based on LPC interface communication performed by the electronic device 20 as disclosed in any of the previous embodiments.

Further, the application also discloses a computer readable storage medium for storing a computer program; the computer program, when executed by the processor, implements the above disclosed slave access method based on the LPC interface communication. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing has outlined rather broadly the more detailed description of the application in order that the detailed description of the application that follows may be better understood, and in order that the present principles and embodiments may be better understood; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. An access method of a slave machine based on LPC interface communication is characterized by being applied to an X86 processor, wherein the slave machine is an FPGA or an EPLD logic device, and the method comprises the following steps:

2. The method of claim 1, wherein the X86 processor communicates with the FPGA or EPLD logic device via an LPC bus.

3. The slave access method according to claim 1, wherein controlling the slave to enter a start bit state from an IDLE state based on the data access request comprises:

4. The method according to claim 1, wherein if the data access request is a data write request, the step of skipping to the synchronous information domain state after completing the access operation of the register data according to the address information comprises:

If not, the method jumps to the synchronous information domain state.

5. The method according to claim 4, wherein if the data access request is a data write request, the performing assignment processing on the multiplexed signal line based on the data access request and controlling the slave to return to the IDLE state includes:

6. The method for accessing a slave machine based on LPC interface communication according to claim 1, wherein if the data access request is a data read request, the step of skipping to a synchronous information domain state after completing the access operation of the register data according to the address information includes:

the control register is in high level and controls the slave to jump to the second bus switching state

Judging whether the multiplexing signal line is in a high potential or not under the bus switching state;

If not, the method jumps to the synchronous information domain state.

7. The method according to claim 6, wherein if the data access request is a data read request, the performing assignment processing on the multiplexed signal line based on the data access request and controlling the slave to return to the IDLE state includes:

8. A slave access device based on LPC interface communication, applied to an X86 processor, the slave being an FPGA or EPLD logic device, the device comprising:

9. An electronic device, comprising:

a memory for storing a computer program;

A processor for executing the computer program to implement the slave access method based on LPC interface communication according to any of claims 1 to 7.

10. A computer readable storage medium for storing a computer program which, when executed by a processor, implements the method of slave access based on LPC interface communication according to any of claims 1 to 7.