CN116501268B - Data reading method applied to DDR PHY - Google Patents

Data reading method applied to DDR PHY Download PDF

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Publication number
CN116501268B
CN116501268B CN202310771617.2A CN202310771617A CN116501268B CN 116501268 B CN116501268 B CN 116501268B CN 202310771617 A CN202310771617 A CN 202310771617A CN 116501268 B CN116501268 B CN 116501268B
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data
preamble
postamble
read
signal
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CN116501268A (en
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吴志平
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Niuxin Semiconductor Shenzhen Co ltd
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Niuxin Semiconductor Shenzhen Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the application provides a data reading method applied to DDR PHY, which comprises the following steps: generating read pointer information according to the received read control signal, the preamble signal and the postamble signal; reading target data from the FIFO module based on the read pointer information, the target data being read from a data memory and written into the FIFO module based on the DQS signal; wherein the read pointer information includes: when the reading control signal is at a low level, the reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble; when the read control signal is at a high level, the read pointer points to a storage address corresponding to the target data. According to the technical scheme, the data corresponding to the preamble and the postamble stored in the FIFO module can be skipped, and the target data can be directly read, so that the DDR Controller is prevented from acquiring invalid data, and the transmission time is shortened.

Description

Data reading method applied to DDR PHY
Technical Field
The application relates to the technical field of data transmission, in particular to a data reading method applied to DDR PHY.
Background
With the continuous development of science and technology, the DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory ) is used as a memory, which is one of the conventional choices.
In the related art, the DDR SDRAM includes a DDR Controller (Double Data Rate Controller ), a DDR PHY (Double Data Rate Physical interface, double data rate physical interface) and a DRAM (Dynamical Random Access Memory, dynamic random access memory), wherein the DDR PHY is used to establish a communication bridge between the DDR Controller and the DRAM, and ensures data transmission between the DDR Controller and the DRAM.
While the DDR PHY generally uses a FIFO (First In First Out, first-in first-out) module to read Data in the DRAM based on a DQS (Data Strobe) signal, the FIFO module reads and stores Data from the DRAM based on the DQS signal, and simultaneously writes invalid Data corresponding to each of a preamble and a postamble included in the DQS signal into the DRAM, which results in that when the DDR Controller reads Data in the FIFO module through the DDR PHY, the DDR Controller also reads the invalid Data, so that the DDR Controller needs to further reject the invalid Data in the read Data, and the overall transmission time is prolonged.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present application provide a data reading method applied to a DDR PHY, and a data processing circuit.
According to an aspect of the embodiments of the present application, there is provided a data reading method applied to a DDR PHY, including: generating read pointer information according to the received read control signal, the preamble signal and the postamble signal; reading target data from the FIFO module based on the read pointer information, the target data being read from a data memory and written into the FIFO module based on the DQS signal; wherein the read pointer information includes: when the reading control signal is at a low level, the reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble; when the read control signal is at a high level, the read pointer points to a storage address corresponding to the target data.
In some embodiments of the present application, based on the foregoing solution, the data reading method further includes: determining a number of signal ports that initiate a read control signal; and if the number of the signal ports is multiple, reading the target data through the reading ports corresponding to the signal ports in sequence.
In some embodiments of the present application, based on the foregoing solution, the data reading method further includes: when a read control signal initiated by any signal port is at a low level, the read pointer skips the storage addresses respectively corresponding to the preamble and the postamble; when the read control signal initiated by any signal port is at a high level, the read pointer points to a storage address corresponding to the target data.
In some embodiments of the present application, based on the foregoing solution, the data reading method further includes: determining a storage address corresponding to the target data according to the read pointer information; and determining the storage addresses respectively corresponding to the preamble and the postamble based on the storage addresses corresponding to the target data.
In some embodiments of the present application, based on the foregoing solution, the data reading method further includes: acquiring the storage data width of the FIFO module; determining sequence number information of the target data according to a read control signal in the read pointer information; respectively determining the data widths corresponding to the preamble and the postamble according to the preamble and the postamble in the read pointer information; and calculating the storage address of the target data based on the storage data width of the FIFO module, the sequence number information of the target data, and the data width of each of the preamble and the postamble.
In some embodiments of the present application, based on the foregoing solution, the data reading method further includes: and calculating the storage addresses of the preamble and the postamble corresponding to the target data based on the storage address of the target data, the data widths of the preamble and the postamble respectively.
In some embodiments of the present application, based on the foregoing scheme, the preamble and the postamble are generated according to a preset transmission protocol, or the preamble and the postamble are generated according to a user-defined transmission rule.
According to an aspect of an embodiment of the present application, there is provided a DDR PHY including: the FIFO module is used for carrying out first-in first-out storage on the received data according to the sequence of data reception; the read pointer module is used for generating read pointer information according to the received read control signal, the preamble signal and the postamble signal and reading target data from the FIFO module based on the read pointer information; wherein the read pointer information includes: when the reading control signal is at a low level, the reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble; when the read control signal is at a high level, the read pointer points to a storage address corresponding to the target data.
In some embodiments of the present application, based on the foregoing, the read pointer module includes a plurality of signal ports for receiving read control signals, and a plurality of read ports for reading data in the FIFO module.
According to an aspect of the embodiments of the present application, there is provided a data processing circuit including the DDR PHY in the above embodiments, so that the data processing circuit implements the data storage method as described in the above embodiments.
In the technical scheme of the embodiment of the application, the DDR PHY can generate read pointer information according to the received read control signal, the preamble and the postamble, and when the read control signal is obtained to be at a low level, namely, when the data in the FIFO module is about to be read, the read pointer skips the storage address corresponding to the preamble, so that target data is directly read from the FIFO module, and invalid data corresponding to the preamble is avoided from being read; when the level corresponding to the read control signal is switched from high level to low level, the target data is characterized to be read, and the read pointer skips over the storage address corresponding to the rear synchronous code, so that invalid data corresponding to the rear synchronous code is avoided, and the transmission efficiency is improved.
In addition, when the read pointer jumps to the storage address corresponding to the post-synchronization code, that is, the read pointer jumps to the storage address of the next data of the FIFO module or the address of the non-stored data, the FIFO module is supported to switch the read-write mode subsequently, so that the purpose of ensuring that the FIFO module is not easy to generate read-write conflict is achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of an architecture of DDR PHY (double data rate physical interface) and DRAM (dynamic random access memory) included in a DDR SDRAM related to the related art.
Fig. 2 is a signal diagram of a DRAM according to the related art transmitting data based on the DQS signal.
Fig. 3 is a flowchart illustrating a data reading method applied to a DDR PHY according to an exemplary embodiment of the present application.
Fig. 4 is a flowchart illustrating a data reading method applied to a DDR PHY according to another exemplary embodiment of the present application.
Fig. 5 is a flowchart showing a data reading method applied to the DDR PHY on the basis of the embodiment shown in fig. 4.
Fig. 6 is a flowchart illustrating a data reading method applied to a DDR PHY according to still another exemplary embodiment of the present application.
FIG. 7 is a block diagram of a DDR PHY shown in an exemplary embodiment of the application.
Fig. 8 is a circuit connection diagram of a read pointer module shown in an exemplary embodiment of the present application.
Fig. 9 is a schematic diagram of a signal port and a read port in a DDR PHY as illustrated by an exemplary embodiment of the present application.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
It should be noted that: references herein to "a plurality" means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In the related art, in order to obtain a faster data transmission speed, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory ) is generally used as a memory, and the DDR SDRAM includes a DDR Controller (Double Data Rate Controller ), a DDR PHY (Double Data Rate Physical interface, double data rate physical interface) and a DRAM (Dynamical Random Access Memory, dynamic random access memory), wherein the DDR PHY is used to establish a communication bridge between the DDR Controller and the DRAM, so as to ensure data transmission between the DDR Controller and the DRAM. The data sent by the DDR Controller is converted into data conforming to the DDR protocol and then sent to the DRAM for storage; and reading the data in the DRAM, converting the data into data conforming to the DFI (DDR PHY Interface) protocol, and then sending the data to the DDR Controller for use, thereby realizing data intercommunication.
Fig. 1 is a schematic diagram of the architecture of a DDR PHY (double data rate physical interface) and a DRAM (dynamic random access memory) included in a DDR SDRAM in the related art, and referring to fig. 1, when the DDR PHY reads data stored in the DRAM, the DDR PHY generally first reads the data through an FIFO (First In First Out, first-in first-out) module included therein. In the process of reading Data in the DRAM, the DRAM generally sends DQ (Data) based on DQS (Data Strobe) signals, so that the FIFO module accurately distinguishes each transmission period in one clock period, thereby facilitating synchronous reading, that is, reading of Preamble (Preamble) flag Data based on DQS signals is about to start, reading of post-amble (Preamble) flag Data is about to end, so that the transmission period is calibrated by the Preamble to establish phase alignment, smooth switching between read and write operations of the DRAM is ensured by the post-amble, and collision of read and write operations of the DRAM is avoided while accurate Data reception is ensured, and particularly, reference is made to a signal diagram shown in fig. 2.
However, when the FIFO module reads data from the DRAM based on the DQS signal and stores the data, the FIFO module writes the invalid data corresponding to each of the preamble and the postamble into the DRAM, so that when the DDR Controller reads the data in the FIFO module through the DDR PHY, the invalid data is also read, so that the DDR Controller needs to further reject the invalid data in the read data, and the overall transmission time is prolonged.
Therefore, in order to solve the above-mentioned problem, the technical solution of the embodiment of the present application proposes a flowchart of a data reading method applied to a DDR PHY, and specifically refer to fig. 3. The method at least comprises the steps S210 to S220, and the detailed description is as follows:
in step S210, read pointer information is generated from the received read control signal, preamble signal, and postamble signal.
In the embodiment of the application, when the DDR Controller needs to read the data in the FIFO module through the DDR PHY, the DDR PHY may generate the read pointer information according to the received read control signal, the preamble signal, and the postamble signal.
The read control signal received by the DDR PHY is generated by a DDR Controller. The generation modes of the preamble signal and the postamble signal can be flexibly set according to the requirement. In one example, the preamble and the postamble may be generated according to a preset transmission protocol, that is, a transmission protocol preset by a manufacturer according to a corresponding system design and a type of DRAM during the production of the DDR SDRAM, where the transmission protocol includes preamble information and postamble information of the DRAM transmit signal based on the DQS signal, so that the preamble and the postamble may be generated according to the preamble information and the postamble information included in the preset transmission protocol.
In another example, since the user may further adjust the DDR SDRAM operating frequency and adjust the preamble and postamble employed by the DRAM to generate their user-defined transmission rules in order to obtain a faster transmission rate during use of the DDR SDRAM, the preamble and postamble may be generated according to the user-defined transmission rules to adapt to the current transmission rules.
In step S220, the target data is read from the FIFO module based on the read pointer information.
Wherein the read pointer information includes: when the reading control signal is at a low level, the reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble;
when the read control signal is at a high level, the read pointer points to a memory address corresponding to the target data.
In the embodiment of the application, by identifying the input level of the read control signal in the read pointer information, the data corresponding to the preamble and the postamble stored in the FIFO module can be skipped, and the target data can be directly read, so that the DDR Controller is prevented from acquiring invalid data.
Because the DRAM sends the target data to the FIFO module based on the DQS signal, the corresponding preamble information and the corresponding postamble information when the target data is transmitted can be obtained according to the configured DQS signal, and the corresponding storage addresses of the preamble and the postamble can be naturally obtained according to the DQS signal, so that when the reading control signal is low, namely the data in the FIFO module is about to be read, the reading pointer skips the storage address corresponding to the preamble, and the target data can be directly read from the FIFO module.
In addition, the read control signal also includes size information of the target data, namely, the data size required to be acquired by the DDR Controller. Therefore, when the read pointer sequentially reads the target data in the FIFO module until the reading is completed, the level corresponding to the read control signal is switched from the high level to the low level, and the corresponding read pointer jumps the storage address corresponding to the rear synchronous code, so that invalid data is prevented from being read, the transmission time is shortened, and the transmission efficiency is improved.
Meanwhile, when the read pointer jumps to the storage address corresponding to the post-synchronization code, that is, the read pointer jumps to the storage address of the next data of the FIFO module or the address of the non-stored data, the FIFO module is supported to switch the read-write mode subsequently, so that the purpose of ensuring that the FIFO module is not easy to generate read-write conflict is achieved.
Referring to fig. 4, fig. 4 is a flowchart illustrating a data reading method applied to a DDR PHY according to another exemplary embodiment. As shown in fig. 4, the method may further include steps S310 to S320, which are described in detail below:
in step S310, the number of signal ports that initiate the read control signal is determined.
Because the DDR PHY controls the read target data according to the read control signal, in order to improve the transmission efficiency of the DDR PHY, a plurality of signal ports for initiating the read control signal can be arranged, and corresponding read ports are arranged for each signal port, so that when any signal port initiates the read control signal, the target data is read through the corresponding read port.
Wherein the manner of initiating the signal port of the read control signal is determined, in one example, the address information of the initiation may be determined by the read control signal, so that the corresponding signal port is determined according to the address information.
In step S320, if the number of signal ports is plural, the target data is sequentially read through the corresponding read ports of the plural signal ports.
It should be noted that the target data is composed of a plurality of data segments.
In the embodiment of the application, after the number of the signal ports initiating the read control signal is determined, if the number of the signal ports is determined to be multiple, the target data can be sequentially read through the read ports corresponding to the multiple signal ports, so that the transmission efficiency of the DDR PHY is improved, and meanwhile, the repeated data segments are prevented from being read by the multiple read ports, and the data is abnormal.
Referring to fig. 5, fig. 5 is a flowchart illustrating a data reading method applied to a DDR PHY according to another exemplary embodiment. As shown in fig. 5, the method may further include steps S410 to S420 on the basis of the method shown in fig. 4, which are described in detail as follows:
in step S410, when the read control signal initiated by any signal port is at a low level, the read pointer skips the memory addresses respectively corresponding to the preamble and the postamble.
In step S420, when the read control signal initiated by any signal port is at a high level, the read pointer points to the memory address corresponding to the target data.
In the embodiment of the application, by setting a plurality of signal ports for initiating the read control signal and the read ports corresponding to the signal ports, the transmission efficiency of the DDR PHY is improved, so that in order to skip the data corresponding to the preamble and the postamble stored in the FIFO module when any signal port is used, when the read control signal initiated by any signal port is at a low level, the read pointer skips the storage addresses corresponding to the preamble and the postamble respectively, and simultaneously when the read control signal initiated by any signal port is at a high level, the read pointer points to the storage address corresponding to the target data, and further, the read port corresponding to any signal port can directly read the target data, thereby avoiding that any read port causes the DDR to acquire invalid data.
Referring to fig. 6, fig. 6 is a flowchart illustrating a data reading method applied to a DDR PHY according to another exemplary embodiment. As shown in fig. 6, the method may further include steps S510 to S520, which are described in detail below:
in step S510, a storage address corresponding to the target data is determined according to the read pointer information.
The manner of determining the storage address corresponding to the target data according to the read pointer information may be flexibly set according to needs, and in one example, the storage address corresponding to the target data in the FIFO module may be added to the read control signal, so that the storage address corresponding to the target data may be directly determined by the read control signal in the read pointer information.
In another example, the storage data width of the FIFO module may be first acquired, and then the sequence number information of the target data may be determined according to the read control signal in the read pointer information; then respectively determining the data width corresponding to the preamble and the postamble according to the preamble and the postamble in the read pointer information; and finally, calculating the storage address of the target data based on the storage data width of the FIFO module, the sequence number information of the target data, and the data width of each of the preamble and the postamble.
In the process, the storage data width of the FIFO module represents the data quantity which can be written by the FIFO module for executing single writing operation; where the unit of written data is typically a bit. The width of the stored data can be flexibly adjusted according to the requirements of users. In addition, through the connection with the FIFO module, the preset storage data width of the FIFO module or the storage data width adjusted by the user requirement can be directly obtained.
It should be noted that, the transmission principle of the FIFO module is first in first out, and the DRAM sequentially transmits each data in the data packet to be transmitted to the FIFO module, so as to facilitate the subsequent reading of the data packet. The sequence number information of the target data characterizes the sequence number of the uploaded target data when the data packet containing the target data is uploaded.
Because the read control signal is generated by the DDR Controller, the corresponding target data is the data required by the DDR Controller, the sequence number information of the target data can be added in the read control signal in advance so as to be convenient for reading from the FIFO module, and the sequence number information of the target data can be directly determined according to the read control signal in the read pointer information.
And when the FIFO module reads and stores data from the DRAM based on the DQS signal, invalid data corresponding to each of the preamble and the postamble is written into and stored in the FIFO module, and the data width corresponding to each of the preamble and the postamble characterizes the width occupied by the data quantity corresponding to each of the preamble and the postamble in the FIFO module.
In the embodiment of the application, the preamble signal and the postamble signal are generated based on the preamble and the postamble in the DQS signal currently adopted by the DRAM, and the data quantity corresponding to each of the preamble and the postamble can be determined according to the preamble signal and the postamble signal so as to calculate and determine the data width corresponding to each of the preamble and the postamble based on the data quantity corresponding to each of the preamble and the postamble.
Considering that the FIFO module can store only the data amount corresponding to the stored data width in a single execution of the write operation, it is necessary to store again according to the preamble and the postamble each time the sum of the data amount of the write data and the data amount corresponding to each of the preamble and the postamble reaches the data amount corresponding to the stored data width. Therefore, in order to accurately acquire the storage address of the target data, the storage address of the target data can be calculated based on the storage data width of the FIFO module, the sequence number information of the target data, and the data widths corresponding to the preamble and the postamble.
For example, when the data width of the FIFO module is 20 bits, the sequence number information of the target data is 16 th bit, the data width corresponding to the preamble is 3 bits, and the data width corresponding to the postamble is 2 bits. The amount of data that can be written by a single write operation of the FIFO module is calculated to be 15 bits, i.e. the stored data width of the FIFO module minus the sum of the data widths of the preamble and postamble. Because the sequence number information of the target data is the 16 th bit, the corresponding data needs to be subjected to a write operation, so that the data corresponding to the preamble is written before the target data, and the storage address corresponding to the target data in the FIFO module is calculated to be the 24 th bit, namely the width of the previous storage data plus the data width corresponding to the preamble is added by one.
In step S520, the memory addresses respectively corresponding to the preamble and the postamble are determined based on the memory address corresponding to the target data.
In the embodiment of the present application, after the storage address of the target data is calculated, the storage addresses corresponding to the preamble and the postamble respectively may be determined based on the storage address corresponding to the target data.
The method for determining the storage addresses corresponding to the preamble and the postamble respectively based on the storage addresses corresponding to the target data can be flexibly set according to needs, in one example, the storage address of each preamble and postamble in the FIFO module and the storage interval corresponding to each preamble and postamble can be determined by a protocol, the storage interval is formed by each storage address between the preamble and the postamble in a write-once operation, and after the storage address of the target data is determined, the target storage interval corresponding to the storage address can be determined, so that the corresponding storage address of the preamble and postamble is determined based on the target storage interval.
In another example, considering that the preamble and the postamble can be flexibly adjusted according to the user requirement, correspondingly, the data widths occupied by the preamble and the postamble are also changed, so that the data widths corresponding to the preamble and the postamble can be obtained first, and then the storage addresses of the preamble and the postamble corresponding to the target data can be calculated based on the storage address of the target data and the data widths of the preamble and the postamble respectively.
The manner of acquiring the data widths corresponding to the preamble and the postamble in step S510 is described in detail herein, and is not described in detail herein.
And calculating the storage addresses of the preamble and the postamble corresponding to the target data based on the respective data widths of the storage address, the preamble and the postamble of the target data, wherein, referring to the above example, the storage data width of the FIFO module is 20 bits, the data width corresponding to the preamble is 3 bits, the data width corresponding to the postamble is 2 bits, and the storage address of the target data is 24 th bit. And calculating the corresponding storage addresses of the preamble in the FIFO module as 21 st bit to 23 rd bit, namely the address bits corresponding to the end of the previous storage data width, and the corresponding storage addresses of the postamble in the FIFO module as 38 th bit to 40 th bit, namely the current storage data width minus the data width corresponding to the preamble and the data width of the storage data in the storage data width.
The following describes embodiments of the DDR PHY of the present application that may be used to perform the data read method applied to the DDR PHY in the above-described embodiments of the present application. For details not disclosed in the embodiments of the DDR PHY of the present application, please refer to the embodiments of the data reading method applied to the DDR PHY described above.
Fig. 7 shows a block diagram of a DDR PHY (double data rate physical interface) 600 according to one embodiment of the present application. Referring to fig. 7, a DDR PHY600 according to one embodiment of the present application includes: the FIFO (first in first out) module 610 is configured to store received data in a first out manner according to a sequence of data reception.
A read pointer module 620, configured to generate read pointer information according to the received read control signal, preamble signal and postamble signal, and read target data from the FIFO module based on the read pointer information;
wherein the read pointer information includes:
when the reading control signal is at a low level, the reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble;
when the read control signal is at a high level, the read pointer points to a memory address corresponding to the target data.
A specific arrangement of the read pointer module 620 is shown in fig. 8, where dfi_rddata_en_p0 is a signal port for receiving a read control signal, pre_cfg is a signal port for receiving a preamble signal, and pst_cfg is a signal port for receiving a postamble signal.
In some embodiments of the present application, based on the foregoing scheme, the read pointer module 620 includes a plurality of signal ports for receiving the read control signals, and a plurality of read ports for reading the data in the FIFO module 610, so as to facilitate implementation of the data reading method applied to the DDR PHY shown in fig. 3. In addition, the specific arrangement of the signal ports can be shown in fig. 9, where dfi_rddata_en_p0/1/2/3 is a plurality of signal ports for receiving read control signals, and dfi_rddata_w0/1/2/3 is a plurality of read ports for reading data in the FIFO (first in first out) module 610.
It should be noted that, the DDR PHY600 provided in the above embodiment and the data reading method applied to the DDR PHY provided in the above embodiment belong to the same concept, and the specific manner in which each module and unit perform the operation has been described in detail in the method embodiment, which is not repeated here.
The embodiment of the application also provides a data processing circuit, which comprises the DDR PHY in the embodiment, so that the data reading method applied to the DDR PHY is realized conveniently.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (9)

1. A data reading method applied to DDR PHY, the method comprising:
generating read pointer information according to the received read control signal, the preamble signal and the postamble signal; the preamble signal and the postamble signal are generated according to a preset transmission protocol or according to a user-defined transmission rule;
reading target data from the FIFO module based on the read pointer information, the target data being read from a data memory and written into the FIFO module based on the DQS signal;
wherein the read pointer information includes:
determining a storage address corresponding to the target data according to the read pointer information;
determining storage addresses corresponding to a preamble and a postamble respectively based on the storage addresses corresponding to the target data;
when the reading control signal is at a low level, a reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble; when the read pointer skips the storage address corresponding to the post-synchronization code, the read pointer is jumped to the storage address of the next data of the FIFO module or the address of the non-stored data;
when the read control signal is at a high level, the read pointer points to a storage address corresponding to the target data.
2. The data reading method of claim 1, wherein the method further comprises:
determining a number of signal ports that initiate a read control signal;
and if the number of the signal ports is multiple, reading the target data through the reading ports corresponding to the signal ports in sequence.
3. The data reading method according to claim 2, characterized in that the method further comprises:
when a read control signal initiated by any signal port is at a low level, the read pointer skips the storage addresses respectively corresponding to the preamble and the postamble;
when the read control signal initiated by any signal port is at a high level, the read pointer points to a storage address corresponding to the target data.
4. The data reading method according to claim 1, wherein the determining the storage address corresponding to the target data according to the read pointer information includes:
acquiring the storage data width of the FIFO module;
determining sequence number information of the target data according to a read control signal in the read pointer information;
respectively determining the data widths corresponding to the preamble and the postamble according to the preamble and the postamble in the read pointer information;
and calculating the storage address of the target data based on the storage data width of the FIFO module, the sequence number information of the target data, and the data width of each of the preamble and the postamble.
5. The data reading method according to claim 4, wherein the determining the memory addresses to which the preamble and the postamble correspond, respectively, based on the memory address to which the target data corresponds, comprises:
and calculating the storage addresses of the preamble and the postamble corresponding to the target data based on the storage address of the target data, the data widths of the preamble and the postamble respectively.
6. The data reading method according to claim 1, wherein the preamble and the postamble are generated according to a preset transmission protocol or the preamble and the postamble are generated according to a user-defined transmission rule.
7. A DDR PHY comprising:
the FIFO module is used for carrying out first-in first-out storage on the received data according to the sequence of data reception;
the read pointer module is used for generating read pointer information according to the received read control signal, the preamble signal and the postamble signal and reading target data from the FIFO module based on the read pointer information; the preamble signal and the postamble signal are generated according to a preset transmission protocol or according to a user-defined transmission rule;
wherein the read pointer information includes:
determining a storage address corresponding to the target data according to the read pointer information;
determining storage addresses corresponding to a preamble and a postamble respectively based on the storage addresses corresponding to the target data;
when the reading control signal is at a low level, the reading pointer skips the storage addresses respectively corresponding to the preamble and the postamble; when the read pointer skips the storage address corresponding to the post-synchronization code, the read pointer is jumped to the storage address of the next data of the FIFO module or the address of the non-stored data;
when the read control signal is at a high level, the read pointer points to a storage address corresponding to the target data.
8. The DDR PHY of claim 7, wherein the read pointer module comprises a plurality of signal ports to receive read control signals, and a plurality of read ports to read data in the FIFO module.
9. A data processing circuit comprising a DDR PHY as claimed in claim 7 or 8.
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