CN118016593B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN118016593B CN118016593B CN202410422598.7A CN202410422598A CN118016593B CN 118016593 B CN118016593 B CN 118016593B CN 202410422598 A CN202410422598 A CN 202410422598A CN 118016593 B CN118016593 B CN 118016593B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 230000000694 effects Effects 0.000 description 17
- 238000011049 filling Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012084 conversion product Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention belongs to the technical field of semiconductors, and discloses a semiconductor structure and a preparation method thereof; the method comprises the following steps: providing a substrate; forming an epitaxial layer and a pad oxide layer on the substrate; forming a first trench and a second trench on a substrate; depositing an insulating medium in the first trench and the second trench; the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove; etching the insulating medium at the bottoms of the first groove and the second groove, and etching through the insulating medium at the bottom of the second groove to expose the substrate; the insulating medium at the bottom of the first groove is not etched through; and depositing polysilicon in the first groove and the second groove to form a first deep groove isolation structure and a second deep groove isolation structure with different structures. The first deep trench isolation structure and the second deep trench isolation structure with different structures can be prepared under the same process, so that the process is simplified, and the time and the cost are saved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
The nature of the power management integrated circuit (Power Management Integratedcircuit, PMIC for short) is a power converter, which converts an unstable or inapplicable power source into a stable power source usable by an electronic product, and which is immune to input voltage and load variations.
With the increase of the integration level of ICs, the market has increasingly demanded products of BCD (Bipolar CMOS DMOS, monolithic integrated process technology). The corresponding effective area increases with higher withstand voltages. To improve this problem, DTI (DEEP TRENCH isolation, deep channel isolation) structures are employed, and higher withstand voltages can be obtained with smaller lateral dimensions.
The DTI isolation process is a process of isolating a circuit by etching deep trenches in the surface of a chip; the DTI isolation process etches a groove with depth reaching several micrometers on the silicon wafer, and then some insulating materials are filled in the groove, so that an isolation structure is formed; the isolation mechanism can effectively prevent current and charge transmission between different circuits, and electrical isolation is formed.
The currently mainstream DTI structures fall into two categories:
Referring to fig. 1, a first deep trench isolation structure: siO 2 is filled in the etched first groove 20 to play an isolating role, so that the withstand voltage of the device is improved;
Referring to fig. 2, a second deep trench isolation structure: the second groove 30 is etched to a depth of 40um filled with P-type poly and can be in homotype contact with the substrate 10 (P-sub), so that the second groove plays a role of a conducting wire and leads out leakage current and noise on the substrate 10; can be widely applied to vehicle-mounted and power conversion products.
However, since the etching depths of the first deep trench isolation structure and the second deep trench isolation structure are different, the conventional process cannot simultaneously implement the two types of deep trench isolation structures on one device.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a preparation method thereof, which solve the technical problem that the existing first deep trench isolation structure and the second deep trench isolation structure cannot be used for one device at the same time.
Compared with the prior art, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a method for preparing a semiconductor structure, including:
Providing a substrate;
forming an epitaxial layer and a pad oxide layer on the substrate;
Forming a first trench and a second trench on a substrate; the first groove and the second groove sequentially penetrate through the epitaxial layer and the liner oxide layer and extend into the substrate; the depth of the second groove is greater than that of the first groove; the first groove and the second groove are closed grooves which are connected end to end; the second groove is arranged on the periphery of the first groove and surrounds the first groove;
Depositing insulating medium in the first groove and the second groove, forming a first insulating medium layer on the side wall of the first groove, and forming a second insulating medium layer on the side wall of the second groove; the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove;
etching the insulating medium at the bottoms of the first groove and the second groove, and etching through the insulating medium at the bottom of the second groove to expose the substrate; the insulating medium at the bottom of the first groove is not etched through;
and depositing polysilicon in the first groove and the second groove to form a first deep groove isolation structure and a second deep groove isolation structure with different structures.
The invention is further improved in that: the step of forming the first groove and the second groove on the substrate specifically comprises the following steps:
forming a photoresist layer on the pad oxide layer;
Forming a first groove pattern and a second groove pattern on the photoresist layer by using a mask plate through exposure and development processes; the critical dimension of the first groove pattern is smaller than the critical dimension of the second groove pattern;
And etching the liner oxide layer, the epitaxial layer and the substrate in the openings of the first groove pattern and the second groove pattern by taking the photoresist layer as a mask, and removing the photoresist layer after etching is finished to form the first groove and the second groove.
The invention is further improved in that: the step of depositing polysilicon in the first trench and the second trench to form a first deep trench isolation structure and a second deep trench isolation structure with different structures specifically comprises the following steps:
depositing polysilicon to fill the first groove and the second groove, and forming a polysilicon layer on the top of the device;
Flattening the polysilicon layer on the top of the device until the liner oxide layer is exposed; first and second deep trench isolation structures of different structures are formed on a substrate.
The invention is further improved in that: the cross section of the first groove and the second groove parallel to the substrate is annular or polygonal.
The invention is further improved in that: the cross section of the first groove and the cross section of the second groove are both in a shape of a Chinese character kou, and the second groove is arranged on the periphery of the first groove and surrounds the first groove; the opening width of the second groove is larger than that of the first groove.
The invention is further improved in that: the side wall angle of the first groove is 88-89.5 degrees; the side wall angle of the second groove is 88-89.5 degrees.
The invention is further improved in that: the first trench and the second trench are spaced apart by 2-2.5 microns.
The invention is further improved in that: the critical dimension (Critical Dimension, abbreviated as CD) of the first trench is 1.5um, and the critical dimension of the second trench further outside is 2.5um.
The invention is further improved in that: in the step of depositing the insulating medium in the first trench and the second trench, the deposited insulating medium is SiO 2.
The invention is further improved in that: the first deep trench isolation structure is an isolation type deep trench isolation structure; the second deep trench isolation structure is a wire type deep trench isolation structure.
In a second aspect, the present invention provides a semiconductor structure comprising:
a substrate;
an epitaxial layer formed on the substrate;
A pad oxide layer formed on the epitaxial layer;
a first trench formed on the substrate; the first groove penetrates through the whole epitaxial layer, the whole liner oxide layer and part of the substrate;
the first insulating medium layer is formed on the side wall and the bottom of the first groove;
the first polysilicon layer is filled in the first insulating medium layer;
A second trench formed on the substrate; the second groove penetrates through the whole epitaxial layer, the whole liner oxide layer and part of the substrate; the depth of the second groove is greater than that of the first groove;
The second insulating medium layer is formed on the side wall of the second groove;
and the second polysilicon layer is filled in the second insulating medium layer and contacts the substrate exposed at the bottom of the second groove.
The invention is further improved in that: the opening width of the second groove is larger than that of the first groove; the second groove is arranged on the periphery of the first groove and surrounds the first groove.
Compared with the prior art, the application has the unexpected technical effects that:
The invention provides a semiconductor structure and a preparation method thereof, wherein a first deep trench isolation structure and a second deep trench isolation structure with different structures are formed on the same semiconductor structure; the first deep trench isolation structure and the second deep trench isolation structure have different trench depths; when grooves with different depths are formed, the first grooves and the second grooves with different depths can be prepared under one process by controlling the critical dimension of the first grooves to be smaller than that of the second grooves, so that the process is simplified, and the time and the cost are saved. In the invention, because the opening width of the first groove is smaller than the opening width of the second groove, when the insulating medium is deposited in the groove, the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove, when the bottom of the groove is etched, the insulating medium deposited at the bottom of the second groove is etched to expose the substrate by controlling the etching time, and the insulating medium deposited at the bottom of the first groove is thicker and is not etched through in the same etching time; after further filling the polysilicon, a first deep trench isolation structure and a second deep trench isolation structure with different structures are formed on the same semiconductor structure.
The unexpected technical effects of the application are as follows: controlling the opening width of the first groove to be smaller than that of the second groove, so that the depth of the second groove is larger than that of the first groove under the same etching process; in the application, the side wall angle of the first groove is controlled to be equal to the side wall angle of the second groove, so that when the insulating medium is deposited at the same time, the insulating medium deposited at the bottom of the first groove with the narrower bottom is thicker, and in the subsequent unified etching process, the insulating medium deposited at the bottom of the second groove is etched to expose the substrate, and the insulating medium deposited at the bottom of the first groove is thicker and is not etched through in the same etching time.
The unexpected technical effects of the application are as follows: the cross section of the first groove and the cross section of the second groove are both in a shape of a Chinese character kou, the second groove is arranged on the periphery of the first groove, and surrounds the first groove to form a Chinese character 'Hui' -shaped structure; bringing the first deep trench isolation structure closer to the high voltage device of the power management integrated circuit; when the high-voltage device operates, the first deep trench isolation structure is firstly isolated, carrier accumulation between the first deep trench isolation structure and the second deep trench isolation structure is reduced, and the second deep trench isolation structure which is further outside can better lead out leakage current leakage and noise on the substrate; the two are organically matched to play a better role in isolation.
The unexpected technical effects of the application are as follows: the interval between the first groove and the second groove is 2-2.5 micrometers; leakage current of the central high-voltage device can be rapidly discharged.
The unexpected technical effects of the application are as follows: polysilicon is also deposited in the center of the first deep trench isolation structure, which can provide good stress dissipation.
The unexpected technical effects of the application are as follows: the two DTI structures are arranged to be a reverse-square structure to alternately wrap the HV device, and the inner ring is insulated, so that the difficulty of passing carriers through the drift region is increased, and the breakdown voltage is improved. The outer ring is conductive, so that the carrier with the upper part accelerated transversely can be prevented from escaping, and the electric leakage accumulated to the substrate by longitudinal acceleration can be led out; therefore, the breakdown voltage and the reliability are improved on the premise of not changing the effective structure of the HV device.
The unexpected technical effects of the application are as follows: by utilizing the different opening widths of the first groove and the second groove, a first insulating medium layer can be formed on the side wall of the first groove by utilizing a one-time deposition process, a second insulating medium layer is formed on the side wall of the second groove, and meanwhile, the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove; when the subsequent bottom etching is performed, the insulating medium at the bottom of the second groove can be etched through to expose the substrate, and the insulating medium at the bottom of the first groove is not etched through under the same etching time; therefore, different DTI structures can be formed on the same chip, so that the two structures act cooperatively to play a better role in isolation.
The unexpected technical effects of the application are as follows: the depth of the CD 1.5um DTI tree is shallower to be an isolated DTI, the depth of the CD 2.5um DTI tree reaches 40um to be a conducting wire led out by deep leakage, and the wiring type penetrating structure can meet the requirements of high voltage resistance and low interference required by the ultra-high voltage PIMC device on the premise of not changing the effective structure of the high voltage device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Figure 1 is a schematic diagram of a first deep trench isolation structure;
FIG. 2 is a schematic diagram of a second deep trench isolation structure;
FIG. 3 is a top view of a semiconductor structure according to one embodiment of the present invention;
FIG. 4 is a partial cross-sectional view of a substrate, epitaxial layer and liner oxide in accordance with one embodiment of the present invention;
FIG. 5 is a partial cross-sectional view of a first CD trench pattern and a second CD trench pattern formed in a photoresist layer over a pad oxide layer according to one embodiment of the present invention;
FIG. 6 is a partial cross-sectional view of a first trench and a second trench formed in a substrate in accordance with one embodiment of the present invention;
FIG. 7 is a partial cross-sectional view of an embodiment of the present invention for depositing an insulating medium in a first trench and a second trench;
FIG. 8 is a partial cross-sectional view of the bottom of the etched first trench and the etched second trench in an embodiment of the invention;
FIG. 9 is a partial cross-sectional view of deposited polysilicon in accordance with one embodiment of the present invention;
Figure 10 is a partial cross sectional view of a semiconductor structure in accordance with one embodiment of the present invention.
Reference numerals illustrate:
10. Is a substrate; 11. an epitaxial layer; 12. a pad oxide layer; 13. a photoresist layer; 14. a polysilicon layer;
20. A first trench; 200. a first critical dimension trench pattern; 201. a first insulating dielectric layer; 202. a first polysilicon filling layer;
30. A second trench; 300. a second critical dimension trench pattern; 301. a second insulating dielectric layer; 302. and a second polysilicon filling layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
The nature of the power management integrated circuit (Power Management Integratedcircuit, PMIC for short) is a power converter, which converts an unstable or inapplicable power source into a stable power source usable by an electronic product, and which is immune to input voltage and load variations. The semiconductor structure and the manufacturing method thereof provided by the invention can be applied to a power management integrated circuit, and the first deep trench isolation structure and the second deep trench isolation structure are prepared in the same device at the same time, so that the cooperative isolation effect of the first deep trench isolation structure and the second deep trench isolation structure is exerted, and the performance of the semiconductor structure is further improved.
An embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can manufacture two deep trench isolation structures with different functions in the same DTI photomask manufacturing process. First, the critical dimension (Critical Dimension, abbreviated as CD; critical Dimension, which can also be translated into critical dimension, feature dimension, or line width) of the first trench near the high voltage device location is set to 1.5um, and the critical dimension of the second trench immediately further outward is set to 2.5um. Due to the difference in critical dimensions, there is a difference in the behavior of DTI trench etch (the larger the CD the deeper the trench); filling 5000A SiO 2 dep on the side wall of the groove, wherein the bottom position of the first groove with the critical dimension CD 1.5um is sealed by SiO 2, and SiO 2 in the second groove with the critical dimension CD 2.5um is only on the inner wall and the bottom position; etching the SiO 2 at the bottom of the groove, wherein the SiO 2 layer at the bottom of the first groove is thicker and is still isolated from the substrate after etching, the SiO 2 layer at the bottom of the second groove is thinner, and the substrate is exposed after etching; and filling the polysilicon P-type poly, and simultaneously preparing a first deep trench isolation structure and a second deep trench isolation structure with different structures on the same semiconductor device.
Referring to fig. 3-10, fig. 3 is a top view of a semiconductor structure according to an embodiment of the invention; FIGS. 4-10 are cross-sectional views of a portion A of the semiconductor structure of FIG. 3 during a partial fabrication process in accordance with one embodiment of the present invention; an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including the following steps:
Step 1: referring to fig. 4, a substrate 10 is provided, an epitaxial layer 11 is grown on the substrate 10, and then a pad oxide layer 12 is deposited on the epitaxial layer 11;
In the present invention, the substrate 10 may be any material suitable for forming a semiconductor device, such as a semiconductor material formed of silicon carbide (SiC), aluminum nitride (AlN), indium nitride (InN), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compounds.
By way of example, the substrate 10 may be a P-type silicon substrate.
Illustratively, the thickness of the substrate 10 is greater than 40 μm; for example 500-1000. Mu.m, specifically 500. Mu.m, 600. Mu.m, 700. Mu.m, 800. Mu.m, 900. Mu.m, 1000. Mu.m, etc.
In the present invention, the epitaxial growth method (Epitaxial Growth) may be used to form the outer epitaxial layer 11 on the surface of the substrate 10.
By way of example, epitaxial layer 11 may employ a P-type epitaxial layer (P-epi).
Illustratively, the epitaxial layer 11 covers the substrate 10. The thickness of the epitaxial layer 11 is, for example, 6 to 15. Mu.m, specifically, 6 μm, 8 μm, 10 μm, 12 μm, 15 μm, etc.
In the present invention, the pad oxide layer 12 (pad oxide) may be formed by a deposition method, for example, a chemical vapor deposition method, an atomic layer deposition method, and the like, which will not be described herein.
The thickness of the liner oxide 12 is, for example, 2000A-3000A; specifically, 2000A, 2500A, 3000A, etc., for example.
Step 2: referring to fig. 5, after forming the pad oxide layer 12, a photoresist layer 13 is formed on the pad oxide layer 12, for example, by spin coating, and a first critical dimension trench pattern 200 and a second critical dimension trench pattern 300 are formed on the photoresist layer 13 by exposure and development processes using a mask plate (mask); the first critical dimension trench pattern 200 is used to define the location of the first deep trench isolation structure and the second critical dimension trench pattern 300 is used to define the location of the second deep trench isolation structure.
Illustratively, the first critical-dimension trench pattern 200 is annular or polygonal; the specific shape of the mouth is, for example, a groove width of 1.5-2.0 μm; specifically, for example, 1.5. Mu.m, 1.8. Mu.m, 2. Mu.m, etc.
Illustratively, the second critical-dimension trench pattern 300 is annular or polygonal; the specific shape of the mouth is a Chinese character 'kou', and the width of the groove is 2.5-3.5 mu m; specifically, for example, the thickness is 2.5. Mu.m, 3. Mu.m, 3.5. Mu.m, etc.
Illustratively, the second critical-dimension trench pattern 300 has a greater trench width than the first critical-dimension trench pattern 200; the second critical-dimension trench pattern 300 is disposed on the outer periphery of the first critical-dimension trench pattern 200, surrounding the first critical-dimension trench pattern 200.
Step 3: referring to fig. 6, the photoresist layer 13 is used as a mask, and an etching process is used to etch the pad oxide layer 12, the epitaxial layer 11 and the substrate 10 in the openings of the first critical dimension trench pattern 200 and the second critical dimension trench pattern 300, and after etching, the photoresist layer 13 is removed to form the first trench 20 and the second trench 30.
By way of example, the first trench 20 and the second trench 30 may be formed using dry etching, and the etching gas may include, for example, one or a mixture of chlorine (Cl 2), trifluoromethane (CHF 3), difluoromethane (CH 2F2), nitrogen trifluoride (NF 3), sulfur hexafluoride (SF 6), hydrogen bromide (HBr), or the like, or a combination thereof with oxygen (O 2).
Illustratively, the first and second grooves 20, 30 are closed grooves that are joined end to end; the second trench 30 is disposed at the periphery of the first trench 20, and surrounds the first trench 20.
Illustratively, the first trench 20 and the second trench 30 are both mouth-shaped deep trenches; the first groove 20 and the second groove 30 form a zigzag shape.
Illustratively, the first trenches 20 and the second trenches 30 are spaced 2-2.5 microns apart; specifically, for example, 2 microns, 2.2 microns, and 2.5 microns.
Illustratively, the sidewall angle (Profile) of the first trench 20 and the second trench 30 is, for example, 88 ° -89.5 °; specifically, the angles are 88 °, 88.5 °, 89 °, and 89.5 °.
The second trenches 30 each have an average depth of, for example, 35 to 45 μm; specifically, for example, 35 μm, 40 μm, 45 μm, and the like are mentioned. Specifically, for example, the second trenches 30 have a depth of 40 μm, and the first trenches 20 have a depth of 36 to 38 μm.
Illustratively, the groove width of the first critical-dimension groove pattern 200 is smaller than the groove width of the second critical-dimension groove pattern 300 such that the depth of the etched second groove 30 is greater than the depth of the first groove 20.
Step 4: referring to fig. 7, an insulating dielectric layer is grown on the device; forming a first insulating dielectric layer 201 on the side wall of the first trench 20, and forming a second insulating dielectric layer 301 on the side wall of the second trench 30; the synchronization pad oxide layer 12 thickens.
Illustratively, the insulating dielectric layer may be a silicon dioxide layer; the silicon dioxide layer may be formed using Chemical Vapor Deposition (CVD) of Tetraethoxysilane (TEOS); the deposition thickness of the silicon dioxide layer is 4000-6000A; specifically, 4000A, 5000A, and 6000A are examples.
Illustratively, the synchronization pad oxide layer 12 is thickened to 6000-8000A.
Illustratively, the first trench 20 has a smaller groove width than the second trench 30, and the first trench 20 and the second trench 30 have equal sidewall angles; since the groove width of the first groove 20 is smaller than the groove width of the second groove 30, the bottom of the first groove 20 is narrower than the bottom of the second groove 30, and the insulating medium deposited at the bottom of the first groove 30 is more thick, so that the insulating medium accumulation thickness at the bottom of the first groove 20 is greater than the insulating medium accumulation thickness at the bottom of the second groove 30.
Step 5: referring to fig. 8, an etching process is then used to etch the insulating medium at the bottom of the first trench 20 and the bottom of the second trench 30, the etching time is controlled, the insulating medium at the bottom of the second trench 30 is etched through, and the substrate 10 is exposed at the bottom of the second trench 30; the insulating medium stack thickness at the bottom of the first trench 20 is greater than the insulating medium stack thickness at the bottom of the second trench 30, and a large amount of insulating medium remains at the bottom of the first trench 20 and is not etched through.
Illustratively, after etching through the insulating medium at the bottom of the second trench 30, a further etching may be performed.
Step 6: referring to fig. 9, polysilicon (P-type Poly) is deposited on the device surface by chemical vapor deposition, the first trench 20 and the second trench 30 are filled, a first polysilicon filling layer 202 is formed in the first trench 20, a second polysilicon filling layer 302 is formed in the second trench 30, and a polysilicon layer 14 is formed on top of the device.
Illustratively, the polysilicon fills the bottom of the second trench 30 and contacts the substrate 10 exposed at the bottom of the second trench 30.
Step 7: referring to fig. 10, a Chemical Mechanical Polishing (CMP) process is used to polish the polysilicon layer 14 on top of the device, so that the dielectric layers on top of the first trench 20 and the second trench 30 are level with the pad oxide layer 12. Thus, the isolated DTI for improving the voltage resistance and the lead-type DTI for leading out leakage current and noise on the substrate can be simultaneously manufactured on one semiconductor device.
Illustratively, the first trench 20, which has a narrower critical dimension (Critical Dimension, CD for short), has a shallower depth, forming an isolated DTI; the second trench 30, which has a wider critical dimension (Critical Dimension, CD for short), has an average depth of 40 μm, forming a conductive line DTI that leads out leakage current and noise on the substrate. Can simultaneously meet the requirements of high voltage resistance and low interference required by the ultra-high voltage PIMC device.
Referring to fig. 3 and 10, in one embodiment of the present invention, a semiconductor structure is provided, which includes:
a substrate 10;
an epitaxial layer 11, the epitaxial layer 11 being formed on the substrate 10;
A pad oxide layer 12, the pad oxide layer 12 being formed on the epitaxial layer 11;
A first trench 20, the first trench 20 being formed on the substrate 10; the first trench 20 penetrates the whole epitaxial layer 11, the whole liner oxide layer 12 and part of the substrate 10;
A first insulating dielectric layer 201, wherein the first insulating dielectric layer 201 is formed on the side wall and the bottom of the first trench 20;
A first polysilicon layer 202, wherein the first polysilicon layer 202 is filled in the first insulating dielectric layer 201;
A second trench 30, the second trench 30 being formed on the substrate 10; the second trench 30 penetrates the whole epitaxial layer 11, the whole liner oxide layer 12 and part of the substrate 10; the depth of the second trenches 30 is greater than the depth of the first trenches 20;
A second insulating dielectric layer 301, where the second insulating dielectric layer 301 is formed on a sidewall of the second trench 30;
And a second polysilicon layer 302, wherein the second polysilicon layer 302 is filled in the second insulating dielectric layer 301 and contacts the substrate 10 exposed at the bottom of the second trench 30.
Illustratively, the opening width of the second trench 30 is greater than the opening width of the first trench 20; the second groove 30 is disposed at the periphery of the first groove 20, and surrounds the first groove 20.
Illustratively, the first trenches 20 and the second trenches 30 are annular or polygonal in cross-section parallel to the substrate 10.
Illustratively, the cross section of the first groove 20 and the cross section of the second groove 30 are both in a shape of a Chinese character 'kou', and the second groove 30 is arranged at the periphery of the first groove 20 and surrounds the first groove 20; the opening width of the second trench 30 is larger than the opening width of the first trench 20.
Illustratively, the sidewall angle of the first trench 20 is 88 ° -89.5 °; the side wall angle of the second groove 30 is 88-89.5 degrees; the sidewall angle of the first trench 20 and the sidewall angle of the second trench 30 are specifically, for example, 89 °, which enables a better fit of the insulating medium to the trench sidewalls during deposition.
Illustratively, the first trenches 20 and the second trenches 30 are spaced 2-2.5 microns apart.
Illustratively, the critical dimension of the first trench is 1.5um and the critical dimension of the second, further outer trench is 2.5um.
The second trenches 30 are, for example, 40 μm deep and the first trenches 20 are 36-38 μm deep.
The unexpected technical effects of the application are: the application provides a semiconductor structure and a preparation method thereof, wherein a first deep trench isolation structure and a second deep trench isolation structure with different structures are formed on the same semiconductor structure; the first deep trench isolation structure and the second deep trench isolation structure have different trench depths; when grooves with different depths are formed, the first grooves and the second grooves with different depths can be prepared under one process by controlling the critical dimension of the first grooves to be smaller than that of the second grooves, so that the process is simplified, and the time and the cost are saved. In the application, because the opening width of the first groove is smaller than the opening width of the second groove, when the insulating medium is deposited in the groove, the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove, when the bottom of the groove is etched, the insulating medium deposited at the bottom of the second groove is etched to expose the substrate by controlling the etching time, and the insulating medium deposited at the bottom of the first groove is thicker and is not etched through in the same etching time; after further filling the polysilicon, a first deep trench isolation structure and a second deep trench isolation structure with different structures are formed on the same semiconductor structure.
The unexpected technical effects of the application are as follows: controlling the opening width of the first groove to be smaller than that of the second groove, so that the depth of the second groove is larger than that of the first groove under the same etching process; in the application, the side wall angle of the first groove is controlled to be equal to the side wall angle of the second groove, so that when the insulating medium is deposited at the same time, the insulating medium deposited at the bottom of the first groove with the narrower bottom is thicker, and in the subsequent unified etching process, the insulating medium deposited at the bottom of the second groove is etched to expose the substrate, and the insulating medium deposited at the bottom of the first groove is thicker and is not etched through in the same etching time.
The unexpected technical effects of the application are as follows: the cross section of the first groove and the cross section of the second groove are both in a shape of a Chinese character kou, the second groove is arranged on the periphery of the first groove, and surrounds the first groove to form a Chinese character 'Hui' -shaped structure; bringing the first deep trench isolation structure closer to the high voltage device of the power management integrated circuit; when the high-voltage device operates, the first deep trench isolation structure is firstly isolated, carrier accumulation between the first deep trench isolation structure and the second deep trench isolation structure is reduced, and the second deep trench isolation structure which is further outside can better lead out leakage current leakage and noise on the substrate; the two are organically matched to play a better role in isolation.
The unexpected technical effects of the application are as follows: the interval between the first groove and the second groove is 2-2.5 micrometers; leakage current of the central high-voltage device can be rapidly discharged.
The unexpected technical effects of the application are as follows: polysilicon is also deposited in the center of the first deep trench isolation structure, which can provide good stress dissipation.
The unexpected technical effects of the application are as follows: the two DTI structures are arranged to be a reverse-square structure to alternately wrap the HV device, and the inner ring is insulated, so that the difficulty of passing carriers through the drift region is increased, and the breakdown voltage is improved. The outer ring is conductive, so that the carrier with the upper part accelerated transversely can be prevented from escaping, and the electric leakage accumulated to the substrate by longitudinal acceleration can be led out; therefore, the breakdown voltage and the reliability are improved on the premise of not changing the effective structure of the HV device.
The unexpected technical effects of the application are as follows: by utilizing the different opening widths of the first groove and the second groove, a first insulating medium layer can be formed on the side wall of the first groove by utilizing a one-time deposition process, a second insulating medium layer is formed on the side wall of the second groove, and meanwhile, the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove; when the subsequent bottom etching is performed, the insulating medium at the bottom of the second groove can be etched through to expose the substrate, and the insulating medium at the bottom of the first groove is not etched through under the same etching time; therefore, different DTI structures can be formed on the same chip, so that the two structures act cooperatively to play a better role in isolation.
The unexpected technical effects of the application are as follows: the depth of the CD 1.5um DTI tree is shallower to be an isolated DTI, the depth of the CD 2.5um DTI tree reaches 40um to be a conducting wire led out by deep leakage, and the wiring type penetrating structure can meet the requirements of high voltage resistance and low interference required by the ultra-high voltage PIMC device on the premise of not changing the effective structure of the high voltage device.
It will be appreciated by those skilled in the art that the present invention can be carried out in other embodiments without departing from the spirit or essential characteristics thereof. Accordingly, the above disclosed embodiments are illustrative in all respects, and not exclusive. All changes that come within the scope of the invention or equivalents thereto are intended to be embraced therein.
Claims (7)
1. A method of fabricating a semiconductor structure, comprising:
Providing a substrate; the substrate is a P-type substrate;
forming an epitaxial layer and a pad oxide layer on the substrate;
Forming a first trench and a second trench on a substrate; the first groove and the second groove sequentially penetrate through the epitaxial layer and the liner oxide layer and extend into the substrate; the depth of the second groove is greater than that of the first groove; the first groove and the second groove are closed grooves which are connected end to end; the second groove is arranged on the periphery of the first groove and surrounds the first groove;
After forming a first groove and a second groove, directly depositing an insulating medium in the first groove and the second groove, forming a first insulating medium layer on the side wall of the first groove, and forming a second insulating medium layer on the side wall of the second groove; the thickness of the insulating medium deposited at the bottom of the first groove is larger than that of the insulating medium deposited at the bottom of the second groove;
synchronously etching the insulating medium at the bottoms of the first groove and the second groove until the insulating medium at the bottom of the second groove is etched through to expose the substrate; the insulating medium at the bottom of the first groove is not etched through;
polysilicon is deposited in the first groove and the second groove, and a first deep groove isolation structure and a second deep groove isolation structure with different structures are formed;
the step of forming the first groove and the second groove on the substrate specifically comprises the following steps:
forming a photoresist layer on the pad oxide layer;
Forming a first groove pattern and a second groove pattern on the photoresist layer by using a mask plate through exposure and development processes; the critical dimension of the first groove pattern is smaller than the critical dimension of the second groove pattern;
Etching the liner oxide layer, the epitaxial layer and the substrate in the openings of the first groove pattern and the second groove pattern by taking the photoresist layer as a mask, and removing the photoresist layer after etching is finished to form a first groove and a second groove;
the side wall angle of the first groove is 88-89.5 degrees; the side wall angle of the second groove is 88-89.5 degrees.
2. The method of claim 1, wherein the step of depositing polysilicon in the first trench and the second trench to form a first deep trench isolation structure and a second deep trench isolation structure having different structures, specifically comprises:
depositing polysilicon to fill the first trench and the second trench;
Planarizing the top of the device until the pad oxide layer is exposed; first and second deep trench isolation structures of different structures are formed on a substrate.
3. The method of claim 1, wherein the first trench and the second trench have a circular or polygonal cross-section parallel to the substrate.
4. The method for manufacturing a semiconductor structure according to claim 1, wherein a cross section of the first trench and a cross section of the second trench are both in a shape of a Chinese character kou, and the second trench is arranged at the periphery of the first trench and surrounds the first trench; the opening width of the second groove is larger than that of the first groove.
5. The method of claim 1, wherein in the step of depositing an insulating medium in the first trench and the second trench, the deposited insulating medium is SiO 2.
6. The method of claim 1, wherein the first deep trench isolation structure is an isolation type deep trench isolation structure; the second deep trench isolation structure is a wire type deep trench isolation structure.
7. A semiconductor structure, characterized in that it is obtained by a method for producing a semiconductor structure according to any one of claims 1 to 6, comprising:
A substrate; the substrate is a P-type substrate;
an epitaxial layer formed on the substrate;
A pad oxide layer formed on the epitaxial layer;
a first trench formed on the substrate; the first groove penetrates through the whole epitaxial layer, the whole liner oxide layer and part of the substrate;
the first insulating medium layer is formed on the side wall and the bottom of the first groove;
the first polysilicon layer is filled in the first insulating medium layer;
A second trench formed on the substrate; the second groove penetrates through the whole epitaxial layer, the whole liner oxide layer and part of the substrate; the depth of the second groove is greater than that of the first groove; the first groove and the second groove are closed grooves which are connected end to end; the second groove is arranged on the periphery of the first groove and surrounds the first groove;
The second insulating medium layer is formed on the side wall of the second groove;
the second polysilicon layer is filled in the second insulating medium layer and contacts the substrate exposed at the bottom of the second groove;
the opening width of the second groove is larger than that of the first groove;
the side wall angle of the first groove is 88-89.5 degrees; the side wall angle of the second groove is 88-89.5 degrees.
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