CN116632069B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN116632069B CN116632069B CN202310896539.9A CN202310896539A CN116632069B CN 116632069 B CN116632069 B CN 116632069B CN 202310896539 A CN202310896539 A CN 202310896539A CN 116632069 B CN116632069 B CN 116632069B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The application discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device includes at least: a substrate, wherein a well region and a drift region are arranged in the substrate in parallel; a shallow trench isolation structure disposed between adjacent semiconductor devices; the isolation column is arranged in the drift region, the depth of the isolation column is smaller than that of the shallow trench isolation structure, and the isolation column and the shallow trench isolation structure are obtained synchronously; the grid structure is positioned on part of the isolation column, the drift region at one side of the isolation column and part of the well region; the leakage doping region is arranged in the drift region; and a source doped region disposed in the well region. The semiconductor device and the manufacturing method thereof improve the performance of the semiconductor device and simplify the manufacturing process of the semiconductor device.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
With the development of semiconductor devices, a lateral double-diffused metal oxide semiconductor field effect transistor (Lateral double diffusion MOS, LDMOS) has advantages of gate voltage control, large current density, small turn-on voltage drop, and the like, and is widely applied to functional elements of integrated Power Management circuits (PMIC). The LDMOS device with the shallow trench isolation structure has the advantage of high breakdown voltage, but the current passes through the bottom of the deeper shallow trench isolation structure, so that high specific on-resistance can be generated. Therefore, by reducing the depth of the shallow trench isolation structure in the LDMOS device, a device with high breakdown voltage and small specific on-resistance is obtained, but in the production process, the depth of the shallow trench isolation structure cannot be used for combining the isolation effect and the device characteristic, or the manufacturing process is complex, so that the manufacturing cost is increased.
Disclosure of Invention
The application aims to provide a semiconductor device and a manufacturing method thereof, and the semiconductor device and the manufacturing method thereof can simplify the manufacturing flow of the semiconductor device and improve the performance of the semiconductor device.
In order to solve the technical problems, the application is realized by the following technical scheme:
the present application provides a semiconductor device including:
a substrate, wherein a well region and a drift region are arranged in the substrate in parallel;
a shallow trench isolation structure disposed between adjacent semiconductor devices;
the isolation column is arranged in the drift region, the depth of the isolation column is smaller than that of the shallow trench isolation structure, and the isolation column and the shallow trench isolation structure are obtained synchronously;
the grid structure is positioned on part of the isolation column, the drift region at one side of the isolation column and part of the well region;
the leakage doping region is arranged in the drift region; and
and the source doping region is arranged in the well region.
In an embodiment of the present application, a gate oxide layer is disposed between the gate structure and the substrate, the gate oxide layer is disposed adjacent to the isolation pillars, and a surface of the gate oxide layer is flush with a surface of the isolation pillars.
In an embodiment of the present application, the depth of the shallow trench isolation structure is 1.2 times to 2 times the depth of the isolation column.
In an embodiment of the present application, a depth of the well region is less than or equal to a depth of the drift region.
Another object of the present application is to provide a method for manufacturing a semiconductor device, including:
providing a substrate;
forming shallow trench isolation structures in the substrate, wherein the shallow trench isolation structures are arranged between adjacent semiconductor devices;
forming an isolation column in the substrate, wherein the depth of the isolation column is smaller than that of the shallow trench isolation structure, and the isolation column and the shallow trench isolation structure are formed synchronously;
forming a well region and a drift region which are arranged in parallel in the substrate, wherein the drift region wraps the isolation column;
forming a gate structure on the substrate, wherein the gate structure is positioned on part of the isolation column, the drift region at one side of the isolation column and part of the well region;
forming a drain doping region in the drift region; and
and forming a source doping region in the well region.
In an embodiment of the present application, the method for forming the isolation pillar and the shallow trench isolation structure includes:
forming a pad oxide layer and a pad nitride layer on the substrate, the pad nitride layer being formed on the pad oxide layer;
forming a photoresist layer on the pad nitride layer;
exposing and developing the photoresist layer by using a mask plate to form a first opening and a second opening, wherein the second opening is positioned between adjacent first openings, the first opening exposes the pad nitride layer, and the second opening is positioned in the photoresist layer;
placing the substrate into a cavity, and etching the pad nitride layer, the pad oxide layer and part of the substrate at the bottom of the first opening to form a first groove;
changing etching gas, and ashing the photoresist layer until the second opening exposes the pad nitride layer;
using the photoresist layer as a mask, replacing etching gas, and etching part of the substrate in the first groove, the pad nitride layer, the pad oxide layer and part of the substrate at the bottom of the second opening to form a shallow groove and an isolation shallow groove; and
and depositing insulating medium in the shallow trench and the isolation shallow trench to form the shallow trench isolation structure and the isolation column.
In an embodiment of the application, the mask plate includes a substrate, a barrier layer and a light shielding layer, wherein the light transmittance of the substrate is greater than that of the barrier layer, and the light transmittance of the barrier layer is greater than that of the light shielding layer.
In an embodiment of the present application, the mask on the second opening includes the substrate and the barrier layer.
In an embodiment of the present application, the depth difference between the shallow trench isolation structure and the isolation pillar is obtained by the following formula:
H=d+T 1 ×S 1 +T 2 ×S 2 ；
wherein H is the depth difference between the shallow trench isolation structure and the isolation column, d is the depth of the first trench in the substrate, T 1 S is the thickness of the pad nitride layer 1 T for the etching selection ratio of the substrate and the pad nitride layer 2 S is the thickness of the pad oxide layer 2 And etching the substrate and the pad oxide layer according to the selection ratio.
In an embodiment of the present application, the manufacturing method further includes:
depositing an insulating medium in the shallow trenches and the isolation shallow trenches, wherein the insulating medium covers the pad nitride layer;
planarizing the insulating medium and the pad nitride layer;
removing the pad nitride layer; and
and removing part of the pad oxide layer and the insulating medium, wherein the surface of the pad oxide layer is flush with the surface of the insulating medium so as to form a gate oxide layer and the isolation column.
In summary, the present application provides a semiconductor device and a method for manufacturing the same, which are capable of forming shallow trenches of different depths through a photoresist layer, and etching the shallow trenches in the same chamber, so that the performance requirements of the semiconductor device can be satisfied, the controllability is high, the process can be simplified, and the production cost of enterprises can be reduced. The depth difference between the shallow trench isolation structure and the isolation column and the thickness of the gate oxide layer are controlled through a one-time photoresist process, so that the manufacturing process is simplified. The depth of the isolation column is smaller than that of the shallow trench isolation structure, so that the on-state current of the semiconductor device is improved, the specific on-state resistance of the semiconductor device is reduced, the electric field distribution at the edge of the grid structure is improved, the withstand voltage of the device is improved, and meanwhile, the hot carrier effect can be reduced, so that the performance of the LDMOS device is improved.
Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a pad oxide layer and a pad nitride layer according to an embodiment.
FIG. 2 is a schematic diagram of a reticle and photoresist layer in one embodiment.
FIG. 3 is a schematic diagram of a first opening and a second opening in a photoresist layer according to one embodiment.
Fig. 4 is a schematic diagram illustrating a position of a first trench in an embodiment.
FIG. 5 is a schematic diagram of ashing a photoresist layer in one embodiment.
FIG. 6 is a schematic diagram of isolating shallow trenches from shallow trenches in an embodiment.
FIG. 7 is a schematic illustration of a spacer medium in one embodiment.
FIG. 8 is a schematic diagram of a shallow trench isolation structure and an isolation pillar in an embodiment.
Fig. 9 is a schematic diagram of forming a drift region in an embodiment.
FIG. 10 is a schematic diagram of forming a well region in an embodiment.
FIG. 11 is a schematic diagram illustrating a gate material layer formed in an embodiment.
FIG. 12 is a schematic diagram of forming a gate structure in an embodiment.
Fig. 13 is a schematic view of a sidewall structure in an embodiment.
Fig. 14 is a schematic view of a semiconductor device in an embodiment.
Description of the reference numerals:
100. a substrate; 110. A pad oxide layer; 111. a gate oxide layer; 120. pad nitriding layer; 130. a photoresist layer; 131. a first opening; 132. a second opening; 133. a first trench; 141. a shallow trench; 142. isolating the shallow trench; 150. an insulating medium; 151. shallow trench isolation structures; 152. a separation column; 160. a first patterned photoresist layer; 170. a drift region; 180. a second patterned photoresist layer; 190. a well region; 211. a gate material layer; 200. a third patterned photoresist layer; 210. a gate structure; 220. a side wall structure; 230. a first doped region; 240. a second doped region; 20. masking plate; 201. a substrate; 202. a barrier layer; 203. a light shielding layer.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The semiconductor device and the manufacturing method thereof provided by the application have the advantages of excellent performance, simple manufacturing method and low manufacturing cost. The obtained semiconductor device can be widely applied to various fields of communication, traffic, energy, medicine, household appliances, aerospace and the like.
Referring to fig. 1, in an embodiment of the present application, a substrate 100 is provided first, and the substrate 100 may be any material suitable for forming a semiconductor device, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compounds, and the like, and further includes a stacked structure formed of these semiconductor materials, or a silicon-on-insulator, a stacked silicon-on-insulator, a silicon-germanium-on-insulator, and a germanium-on-insulator. The material of the substrate 100 is not limited in the present application, and the substrate 100 may be a P-doped semiconductor substrate or an N-doped semiconductor substrate, and in this embodiment, the substrate 100 is, for example, a P-doped semiconductor substrate.
Referring to fig. 1, in an embodiment of the present application, a pad oxide layer 110 is formed on a substrate 100, wherein the pad oxide layer 110 is made of a dense silicon oxide, and the pad oxide layer 110 is formed on the substrate 100 by a thermal oxidation method, an in situ vapor growth method, or a chemical vapor deposition method, for example. In this embodiment, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900-1150 ℃, oxygen is introduced, and the substrate 100 reacts with oxygen at a high temperature to produce a dense pad oxide layer 110. The thickness of the pad oxide layer 110 is, for example, 10nm to 50nm, specifically, 25nm, 35nm, 40nm, 45nm, 50nm, or the like.
Referring to fig. 2, in an embodiment of the present application, a pad nitride layer 120 is formed on the pad oxide layer 110, and the pad nitride layer 120 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. Wherein the pad oxide layer 110 serves as a buffer layer to improve the stress between the substrate 100 and the pad nitride layer 120. In the present application, the pad nitride layer 120 may be formed on the pad oxide layer 110 by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD). Specifically, for example, the substrate 100 with the pad oxide layer 110 is placed in a furnace filled with dichlorosilane and ammonia gas, and the pad nitride layer 120 is deposited by reacting at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 800 ℃. The thickness of the pad nitride layer 120 is, for example, 50nm to 120nm, specifically, 60nm, 75nm, 80nm, 100nm, 110nm, 120nm, or the like. The pad nitride layer 120 may protect the substrate 100 from planarization processes such as chemical mechanical polishing (Chemical Mechanical Polishing, CMP) involved in the fabrication of shallow trench isolation structures. And the pad nitride layer 120 can be used as a mask in the shallow trench formation process to protect the substrate 100 at other positions from damage during etching of the substrate 100.
Referring to fig. 1 to 2, in an embodiment of the present application, a photoresist layer 130, such as a positive photoresist, may be formed on the pad nitride layer 120 by, for example, spin coating. The photoresist layer 130 is exposed, and the exposure amounts of the different areas are different, and the exposure amount of the photoresist corresponding to the shallow trenches between the LDMOS devices is larger than that of the photoresist corresponding to the shallow trenches in the LDMOS devices. In this embodiment, the exposure of different areas is controlled, for example, by the mask 20, wherein the mask 20 includes a substrate 201, a barrier layer 202, and a light shielding layer 203. And the barrier layer 202 is arranged on the substrate 201, the light shielding layer 203 is arranged on the barrier layer 202, and the proportion of light transmittance in different areas is controlled by different light transmittance of the barrier layer 202 and the light shielding layer 203.
Referring to fig. 2, in an embodiment of the present application, the substrate 201 is a transparent substrate made of a material such as silicon dioxide or aluminum oxide, the barrier layer 202 is a semi-transparent film made of a material such as germanium oxide (GeO), and the light shielding layer 203 is an opaque film made of a material such as germanium (Ge). In other embodiments, the barrier layer 202 and the light shielding layer 203 are made of different light-transmitting materials, so that the light transmittance of the barrier layer 202 is ensured to be greater than that of the light shielding layer 203, and the light transmittance of the barrier layer 202 is 2 times to 5 times that of the light shielding layer 203. Wherein, the mask 20 on the shallow trench between the LDMOS devices only has the substrate 201, and neither the barrier layer 202 nor the light shielding layer 203 is provided for positioning the shallow trench isolation structure between the LDMOS devices. A reticle 20, located over a shallow trench in the LDMOS device, presents a substrate 201 and a barrier layer 202 for locating the position of the isolation column in the LDMOS device. A substrate 201, a barrier layer 202, and a light shielding layer 203 are provided in the remaining regions for protecting other regions on the substrate.
Referring to fig. 2 to 3, in an embodiment of the application, the thickness of the barrier layer 202 is, for example, two-thirds to one-fifth of the thickness of the light shielding layer 203, and the exposure of the photoresist layer 130 in different areas is controlled by controlling the light transmittance and the multiple of the thickness of the barrier layer 202 and the light shielding layer 203. In this embodiment, after exposure through the mask 20, the photoresist layer 130 is developed, and a first opening 131 and a second opening 132 are formed in the photoresist layer 130, with the second opening 132 being located between adjacent first openings 131. The first opening 131 penetrates the photoresist layer 130 and is exposed to the pad nitride layer 120, and the second opening 132 is disposed in the photoresist layer 130 and does not penetrate the photoresist layer 130. The first opening 131 is used to locate the position of the shallow trench isolation structure between the LDMOS devices and the second opening 132 is used to locate the position of the isolation column within the LDMOS devices.
Referring to fig. 3 to 4, in an embodiment of the present application, a substrate with a photoresist layer 130 having a first opening 131 and a second opening 132 is placed in an etching chamber, and etching is performed by using the photoresist layer 130 as a mask, so as to remove the pad nitride layer 120, the pad oxide layer 110 and a portion of the substrate 100 exposed by the first opening 131, thereby forming a first trench 133 for positioning the shallow trench isolation structure between the LDMOS devices. In the present embodiment, for example, the first trench 133 is selectively formed by dry etching, and the etching gas includes, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), or a mixture of them with oxygen (O) 2 ) And (5) combining.
Referring to fig. 4 to 5, in an embodiment of the present application, after the first etching is completed, the gas introduced into the etching chamber is replaced, and the photoresist at the bottom of the second opening 132 on the photoresist layer 130 is processed and exposed to the pad nitride layer 120. In this embodiment, the photoresist at the bottom of the second opening 132 is removed, for example, by an ashing process, for example, after the first etching is completed, the gas introduced into the chamber is replaced with oxygen, and the photoresist layer 130 is ashed until the second opening 132 is exposed to the pad nitride layer 120. The photoresist layer 130 is left over the remaining area to be thick to meet etching requirements.
Referring to fig. 5 to fig. 6, in an embodiment of the present application, the ashed photoresist layer 130 is used as a mask, etching gas is continuously introduced into the chamber to etch, remove a portion of the substrate 100 at the bottom of the first trench 133, form a shallow trench 141, and remove the pad nitride layer 120, the pad oxide layer 110 and a portion of the substrate 100 exposed by the second opening 132, so as to form an isolation shallow trench 142. In this embodiment, for example, a dry etching is selectively used to form the shallow trench, and the etching gas includes, for example, one or more of chlorine, trifluoromethane, difluoromethane, nitrogen trifluoride, sulfur hexafluoride, and hydrogen bromide, or a combination of these and oxygen, and after etching, the photoresist layer 130 remaining on the substrate 100 is removed. The shallow trench 141 is disposed between the LDMOS devices, the isolation shallow trench 142 is disposed in the LDMOS devices, and the depth of the shallow trench 141 is, for example, 1.2 times to 2 times the depth of the isolation shallow trench 142, and the specific depth difference can be controlled by the depth of the first trench 133, the thickness of the pad nitride layer 120, and the thickness of the pad oxide layer 110 formed by the first etching, that is, the depth difference is equal to the sum of the product of the depth of the first trench 133, the thickness of the pad nitride layer 120, and the etching selectivity ratio of the substrate 100 and the pad nitride layer 120, and the product of the etching selectivity ratio of the pad oxide layer 110, and the substrate 100 and the pad oxide layer 110, that is, the depth difference between the shallow trench 141 and the isolation shallow trench 142 is obtained by the following formula:
H=d+T 1 ×S 1 +T 2 ×S 2 ；
where H is the depth difference between the shallow trench 141 and the isolation shallow trench 142, d is the depth of the first trench 133 in the substrate, T 1 To pad the thickness of the nitride layer 120, S 1 T for the etch selectivity of substrate 100 and pad nitride layer 120 2 To the thickness of the pad oxide layer 110, S 2 The controllability of the depth difference of the shallow trench 141 and the isolation shallow trench 142 is high for the etching selectivity ratio of the substrate 100 and the pad oxide layer 110. When shallow trenches with different depths are formed, only one photoresist layer is arranged, and etching is completed in the same cavity, so that the shallow trenches with different depths are formed, the performance requirements of semiconductor devices can be met, the controllability is high, the process can be simplified, and the production cost of enterprises can be reduced.
Referring to fig. 6 to 7, in an embodiment of the present application, an insulating medium 150 is deposited in the shallow trenches 141 and the isolation shallow trenches 142, and the insulating medium 150 is deposited until the surface of the pad nitride layer 120 is covered. Optionally, the substrate 100 may be annealed in an oxygen atmosphere prior to depositing the insulating medium 150 to form a liner oxide layer (not shown) within the shallow trenches 141 and the isolation shallow trenches 142 to reduce leakage. The present application is not limited to the deposition of the insulating medium 150, and the corresponding insulating medium 150 may be formed by, for example, high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the deposition of the insulating medium 150, a high temperature (e.g., 800-1200 ℃) tempering process may be performed to increase the density and stress of the insulating medium 150. The insulating medium 150 is, for example, silicon oxide with high adaptability to the grinding tool, and in other embodiments, the insulating medium 150 may be an insulating material such as fluorosilicone glass.
Referring to fig. 6 to 8, in an embodiment of the present application, after forming the insulating medium 150, the insulating medium 150 is subjected to a planarization process, for example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is used to planarize the insulating medium 150 and a portion of the pad nitride layer 120, so that the heights of the insulating medium 150 and the pad nitride layer 120 are uniform. The pad nitride layer 120 after polishing is etched and removed, and the application is not limited to the removal method of the pad nitride layer 120, for example, dry etching, wet etching, or the like. In this embodiment, for example, an acid solution is used for etching, specifically, phosphoric acid with a volume fraction of, for example, 85% -88%, and the pad nitride layer 120 is etched at, for example, 150 ℃ -165 ℃. After removing the pad nitride layer 120, a portion of the pad oxide layer 110 and the insulating medium 150 are removed, ensuring that the remaining pad oxide layer 110 and insulating medium 150 are flush, to form the gate oxide layer 111, the shallow trench isolation structure 151, and the isolation pillars 152. The remaining pad oxide layer 110 is defined as a gate oxide layer 111, and the thickness of the gate oxide layer 111 is, for example, 2nm to 10nm. The shallow trench isolation structure 151 is formed in the shallow trench 141, the isolation pillar 152 is formed in the isolation shallow trench 142, and the depth difference between the shallow trench isolation structure 151 and the isolation pillar 152 is equal to the depth difference between the shallow trench 141 and the isolation shallow trench 142, i.e., the depth of the shallow trench isolation structure 151 is 1.2 times to 2 times the depth of the isolation pillar 152. The depth difference between the shallow trench isolation structure 151 and the isolation column 152 and the thickness of the gate oxide layer 111 are controlled by a one-time photoresist process, and the manufacturing process is simplified.
Referring to fig. 8 to 9, in an embodiment of the present application, a first patterned photoresist layer 160 is formed on the substrate 100, and the first patterned photoresist layer 160 exposes the gate oxide layer 111 between the shallow trench isolation structure 151 and the isolation pillar 152 on one side, exposes the isolation pillar 152, and exposes a portion of the gate oxide layer 111 near the other side of the isolation pillar 152. The drift region 170 is formed by implanting first ions into the substrate using the first patterned photoresist layer 160 as a mask. The first ions are N-type ions such As phosphorus (P) or arsenic (As), that is, the drift region 170 is an N-type doped region. And the drift region 170 contacts the shallow trench isolation structure 151 at one side and wraps the isolation pillar 152. After forming the drift region 170, the first patterned photoresist layer 160 is removed, for example, by a wet etch or an oxidation process.
Referring to fig. 9 to 10, in an embodiment of the application, after forming the drift region 170, a second patterned photoresist layer 180 is formed on the substrate 100, and the second patterned photoresist layer 180 exposes a portion of the gate oxide layer 111 between the shallow trench isolation structure 151 and the drift region 170 on the other side, i.e. the second patterned photoresist layer 180 covers a portion of the gate oxide layer 111 on one side of the drift region 170. The well region 190 is formed by implanting second ions into the substrate using the second patterned photoresist layer 180 as a mask. The second ion is a P-type impurity such as boron (B) or gallium (Ga), that is, the well region 190 is a P-type well region, and the well region 190 and the drift region 170 have a predetermined distance. After forming the well region 190, the second patterned photoresist layer 180 is removed, for example, by a wet etching or oxidation process. And the depth of the well region 190 is less than or equal to the depth of the drift region 170 to increase the withstand voltage of the device.
Referring to fig. 10 to 11, in an embodiment of the present application, after forming the well region 190, a gate material layer 211 is formed on the gate oxide layer 111. The gate material layer 211 is, for example, a polysilicon layer, and the polysilicon layer may be P-type or N-type, and the doping type of the gate material layer 211 is different from the doping type of the substrate 100. In this embodiment, the gate material layer 211 is, for example, N-type, and the thickness of the gate material layer 211 is, for example, 300nm to 400nm, and in other embodiments, the thickness of the gate material layer 211 can be set according to actual needs. A third patterned photoresist layer 200 is formed on the gate material layer 211, wherein the third patterned photoresist layer 200 covers a portion of the isolation pillars 152 and the drift region 170, a portion of the well region 190, and a substrate between the drift region 170 and the well region 190 on one side of the isolation pillars 152.
Referring to fig. 11 to 12, after forming the third patterned photoresist layer 200, the gate material layer 211 is etched using the third patterned photoresist layer 200 as a mask, for example, by a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process. In this embodiment, the gate material layer 211 and the gate oxide layer 111 are sequentially etched, for example, using the anisotropy of a dry etching process, to form the gate structure 210. And the gate structure 210 covers a portion of the isolation pillars 152, reducing the width of the isolation pillars 152 and decreasing the specific on-resistance. In the etching process, the gate oxide layer 111 and the gate material layer 211 are synchronously etched, the number of photomasks is not additionally increased, the production cost is reduced, the self alignment of the gate oxide layer 111 and the gate material layer 211 can be realized, and the performance of the LDMOS device is improved.
Referring to fig. 12 to 13, in an embodiment of the present application, after forming the gate structure 210, a sidewall dielectric layer (not shown) is formed on the substrate 100 and the gate structure 210, and the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After forming the sidewall dielectric layer, for example, the gate structure 210, the shallow trench isolation structure 151, the isolation pillars 152, and a portion of the sidewall dielectric layer on the substrate 100 may be removed by using an etching process such as dry etching or wet etching, so as to retain the sidewall dielectric layers on both sides of the gate structure 210. The sidewall structure 220 is defined by the remaining sidewall dielectric layer, the height of the sidewall structure 220 is identical to that of the gate structure 210, the width of the sidewall structure 220 is gradually increased from top to bottom of the gate structure 210, and the insulating sidewall structure 220 is arranged to prevent the manufactured LDMOS device from generating electric leakage. In this embodiment, the shape of the sidewall 220 is, for example, arc, and in other embodiments, the shape of the sidewall 220 may be triangular or L-shaped.
Referring to fig. 13 to 14, in an embodiment of the present application, after the sidewall structure 220 is formed, doped regions are formed in the drift region 170 and the well region 190. A first doped region 230 is disposed between the shallow trench isolation structure 151 and the isolation pillar 152 at the top of the drift region 170 to serve as a drain doped region of the LDMOS device, and a second doped region 240 is disposed at the top of the well region 190 to serve as a source doped region of the LDMOS device. The doping types of the first doped region 230 and the second doped region 240 are the same, and may be P-type or N-type. In this embodiment, the doping type of the first doped region 230 and the second doped region 240 is, for example, N-type. The drain doping region, the grid structure and the source doping region are arranged to form a complete loop, electrons flow from the source doping region to the drain doping region in the working process of the LDMOS device, the current at the drain doping region is larger, the depth of the isolation column is smaller than that of the shallow trench isolation structure, the on-current of the LDMOS device is improved, namely the specific on-resistance of the device is reduced, the electric field distribution at the edge of the grid structure is improved, the withstand voltage of the device is improved, meanwhile, the hot carrier effect can be reduced, and the performance of the LDMOS device is improved.
In summary, the application provides a semiconductor device and a manufacturing method thereof, and the manufacturing method of the semiconductor device is improved, and the unexpected effects of the application are that the exposure of the mask plate to different areas of the photoresist layer is different, so that shallow trenches with different depths are formed in one photoresist layer, and etching is completed in the same chamber, thereby meeting the performance requirement of the semiconductor device, having high controllability, simplifying the process and reducing the production cost of enterprises. The depth difference between the shallow trench isolation structure and the isolation column and the thickness of the gate oxide layer are controlled through a one-time photoresist process, so that the manufacturing process is simplified. The depth of the isolation column is smaller than that of the shallow trench isolation structure, so that the on-state current of the semiconductor device is improved, the specific on-state resistance of the semiconductor device is reduced, the electric field distribution at the edge of the grid structure is improved, the withstand voltage of the device is improved, and meanwhile, the hot carrier effect can be reduced, so that the performance of the semiconductor device is improved.
The embodiments of the application disclosed above are intended only to help illustrate the application. The examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (6)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming shallow trench isolation structures in the substrate, wherein the shallow trench isolation structures are arranged between adjacent semiconductor devices;
forming an isolation column in the substrate, wherein the depth of the isolation column is smaller than that of the shallow trench isolation structure, and the isolation column and the shallow trench isolation structure are formed synchronously;
forming a well region and a drift region which are arranged in parallel in the substrate, wherein the drift region wraps the isolation column;
forming a gate structure on the substrate, wherein the gate structure is positioned on part of the isolation column, the drift region at one side of the isolation column and part of the well region;
forming a drain doping region in the drift region; and
forming a source doping region in the well region;
a gate oxide layer is further formed between the gate structure and the substrate, the gate oxide layer is arranged close to the isolation column, the surface of the gate oxide layer is flush with the surface of the isolation column, and the gate oxide layer and the isolation column are formed synchronously;
the method for forming the isolation column and the shallow trench isolation structure comprises the following steps:
forming a pad oxide layer and a pad nitride layer on the substrate, the pad nitride layer being formed on the pad oxide layer;
forming a photoresist layer on the pad nitride layer;
exposing and developing the photoresist layer by using a mask plate to form a first opening and a second opening, wherein the second opening is positioned between adjacent first openings, the first opening exposes the pad nitride layer, and the second opening is positioned in the photoresist layer;
placing the substrate into a cavity, and etching the pad nitride layer, the pad oxide layer and part of the substrate at the bottom of the first opening to form a first groove;
changing etching gas, and ashing the photoresist layer until the second opening exposes the pad nitride layer;
using the photoresist layer as a mask, replacing etching gas, and etching part of the substrate in the first groove, the pad nitride layer, the pad oxide layer and part of the substrate at the bottom of the second opening to form a shallow groove and an isolation shallow groove; and
depositing an insulating medium in the shallow trench and the isolation shallow trench to form the shallow trench isolation structure and the isolation column;
the depth difference between the shallow trench isolation structure and the isolation column is obtained by the following formula:
H=d+T 1 ×S 1 +T 2 ×S 2 ；
wherein H is the depth difference between the shallow trench isolation structure and the isolation column, d is the depth of the first trench in the substrate, T 1 S is the thickness of the pad nitride layer 1 T for the etching selection ratio of the substrate and the pad nitride layer 2 S is the thickness of the pad oxide layer 2 And etching the substrate and the pad oxide layer according to the selection ratio.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a depth of the shallow trench isolation structure is 1.2 to 2 times a depth of the isolation column.
3. The method for manufacturing the semiconductor device according to claim 1, wherein a depth of the well region is smaller than or equal to a depth of the drift region.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the mask includes a substrate, a barrier layer, and a light shielding layer, wherein the substrate has a light transmittance greater than the barrier layer, and wherein the barrier layer has a light transmittance greater than the light shielding layer.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the reticle on the second opening includes the substrate and the barrier layer.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that the manufacturing method further comprises:
depositing an insulating medium in the shallow trenches and the isolation shallow trenches, wherein the insulating medium covers the pad nitride layer;
planarizing the insulating medium and the pad nitride layer;
removing the pad nitride layer; and
and removing part of the pad oxide layer and the insulating medium, wherein the surface of the pad oxide layer is flush with the surface of the insulating medium so as to form a gate oxide layer and the isolation column.
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