CN113937056A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113937056A CN113937056A CN202111139817.3A CN202111139817A CN113937056A CN 113937056 A CN113937056 A CN 113937056A CN 202111139817 A CN202111139817 A CN 202111139817A CN 113937056 A CN113937056 A CN 113937056A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 40
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- 238000000227 grinding Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 56
- 230000007547 defect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- -1 silicon gallium compound Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate with a high-voltage device area and a medium-voltage device area; forming a plurality of shallow trench isolation structures; etching the substrate of the high-voltage device area to form a first groove; and forming a first gate oxide structure in the first groove and forming a second gate oxide structure on the surface of the substrate of the medium-voltage device area. The invention also provides a semiconductor device. This application is through form first gate oxide structure in the substrate in high-voltage device district and reduce the height of the first gate oxide structure in high-voltage device district improves follow-up the dummy's high homogeneity that the first gate oxide structure top formed has avoided in follow-up ILD0CMP technology the dummy in high-voltage device district is by the condition of excessive mistake grinding, has laid a good foundation for the smooth filling of follow-up metal gate.
Description
Technical Field
The application relates to the technical field of MOS devices, in particular to a semiconductor device and a manufacturing method thereof.
Background
The 28nm HV MOS device has the characteristics of high voltage, large current and strong driving capability, and the working voltages of an MV (medium voltage) device and an HV (high voltage) device in the HV MOS device are respectively 8V and 32V, so that the high voltage device needs to adopt a thicker gate oxide layer, a deeper junction depth and a larger channel length. The great difference of the working voltages of different devices causes the thickness of the gate oxide layer of the device to be greatly different, and the gate oxide layer of the high-voltage device is at least thicker than that of the medium-voltage device
In HV MOS devices, a relatively common metal gate process usually includes fabricating a dummy gate (dummy poly) on a gate oxide layer, removing the dummy gate by an ILD0CMP (inter-layer insulation chemical mechanical polishing) process, a dry etching process and/or a wet etching process in a subsequent process to leave a trench, and filling a metal material into the original trench to form a metal gate. When an ILD0CMP (interlayer insulating chemical mechanical polishing) process is performed, because the thickness of the gate oxide of the high-voltage device is greater than that of the gate oxide of the medium-voltage device, and because all devices (medium-voltage and high-voltage) on the HVMOS device are simultaneously subjected to ILD0CMP polishing, the pseudogate above the gate oxide of the high-voltage device is excessively and erroneously polished because the pseudogate is higher than that of the medium-voltage device, which may affect the formation of the metal gate in the high-voltage device. Even in extreme cases, after the ILD0CMP process, the pseudogate of the high voltage device is completely worn away, thereby affecting the filling of the metal material, i.e., affecting the formation of the metal gate of the high voltage device, and easily causing the performance failure of the device.
In addition, the thermal oxidation growth process for forming the gate oxide layer has certain limitations, which causes the gate oxide layer at the corner position of the junction of the medium voltage device AA and the STI (shallow trench isolation) to have a void defect, thereby reducing the reliability of the medium voltage device.
Disclosure of Invention
The application provides a semiconductor device and a manufacturing method thereof, which can solve the problems that in an HV MOS device, the height of a gate oxide layer of a high-voltage device is too high, and the gate oxide layer of a medium-voltage device has defects.
In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
providing a substrate with a high-voltage device area and a medium-voltage device area;
forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high-voltage device area and the medium-voltage device area and are distributed in the high-voltage device area and the medium-voltage device area at intervals;
etching the substrate between two adjacent shallow trench isolation structures in the high-voltage device area to form a first trench;
forming a first gate oxide structure, wherein the first gate oxide structure fills the first groove; and the number of the first and second groups,
and forming a second gate oxide structure, wherein the second gate oxide structure is positioned on the surface of the substrate between two adjacent shallow trench isolation structures in the medium-voltage device area.
Optionally, in the manufacturing method of the semiconductor device, two adjacent shallow trench isolation structures in the high-voltage device region and the substrate between the shallow trench isolation structures are etched to form the first trench.
Optionally, in the manufacturing method of the semiconductor device, the sizes of the etched and opened shallow trench isolation structures in the width direction are all the same
Optionally, in the manufacturing method of the semiconductor device, the etching thickness is
The shallow trench isolation structure is etched to a thickness of
To form the stepped first trench.
Optionally, in the manufacturing method of the semiconductor device, the step of forming the second gate oxide structure includes:
forming a mask layer, wherein the mask layer covers the shallow trench isolation structure, the first gate oxide structure and part of the substrate;
etching the mask layer on two adjacent shallow trench isolation structures in the medium-voltage device area to form a second trench in the mask layer;
forming a first gate oxide layer by adopting a thermal oxidation process, wherein the first gate oxide layer covers the bottom wall of the second groove;
forming a second gate oxide layer by adopting an ALD (atomic layer deposition) process, wherein the second gate oxide layer covers the first gate oxide layer, the side wall of the second groove and the mask layer;
removing the mask layer and the second gate oxide layer on the side wall of the second groove; and the number of the first and second groups,
and removing the residual mask layer.
Optionally, in the manufacturing method of the semiconductor device, the thickness of the first gate oxide layer is
Optionally, in the manufacturing method of the semiconductor device, the thickness of the second gate oxide layer is
Optionally, in the manufacturing method of the semiconductor device, the first gate oxide structure is formed by using a thermal oxidation process.
Optionally, in the manufacturing method of the semiconductor device, the thickness of the first gate oxide structure is
On the other hand, the embodiment of the present application further provides a semiconductor device, including:
a substrate having a high voltage device region and a medium voltage device region therein;
the shallow trench isolation structures are positioned at the junction of the high-voltage device area and the medium-voltage device area and are distributed in the high-voltage device area and the medium-voltage device area at intervals, wherein a first trench is formed in the substrate between two adjacent shallow trench isolation structures in the high-voltage device area;
the first gate oxide structure fills the first groove; and
and the second gate oxide structure is positioned on the surface of the substrate between two adjacent shallow trench isolation structures in the medium-voltage device area.
The technical scheme at least comprises the following advantages:
this application is through form first gate oxide structure in the substrate in high-voltage device district and reduce the height of the first gate oxide structure in high-voltage device district improves follow-up the dummy's high homogeneity that the first gate oxide structure top formed has avoided in follow-up ILD0CMP technology the dummy in high-voltage device district is by the condition of excessive mistake grinding, has established the basis for the smooth filling of follow-up metal gate to the performance and the reliability of high-voltage device have been improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIGS. 1-9 are schematic views of a semiconductor structure at various process steps in the manufacture of a semiconductor device according to an embodiment of the present invention;
100-substrate, 101-shallow trench isolation structure, 102-first trench, 103-second trench;
10-a high-voltage device area, 11-a first gate oxide structure and 12-a mask layer;
20-medium voltage device area, 21-second gate oxide structure, 211-first gate oxide layer, 212-second gate oxide layer.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps:
the first step is as follows: providing a substrate with a high-voltage device area and a medium-voltage device area;
the second step is as follows: forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are positioned at the junction of the high-voltage device area and the medium-voltage device area and are distributed in the high-voltage device area and the medium-voltage device area at intervals;
the third step: etching the substrate between two adjacent shallow trench isolation structures in the high-voltage device area to form a first trench;
the fourth step: forming a first gate oxide structure, wherein the first trench is filled with the gate oxide structure;
the fifth step: and forming a second gate oxide structure, wherein the second gate oxide structure is positioned on the surface of the substrate between two adjacent shallow trench isolation structures in the medium-voltage device area.
Specifically, referring to fig. 1-9, fig. 1-9 are schematic views of semiconductor structures in various process steps of manufacturing a semiconductor device according to an embodiment of the present invention.
First, referring to fig. 1, a substrate 100 having a high voltage device region 10 and a medium voltage device region 20 is provided. Specifically, the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, the substrate 100 may also be gallium arsenide, a silicon gallium compound, and the like, and the substrate 100 may also have a silicon-on-insulator or silicon-on-silicon epitaxial layer structure; the substrate 100 may also be other semiconductor materials, which are not listed here. The high voltage device region 10 is on the same wafer as and adjacent to the medium voltage device region 20.
Then, with continued reference to fig. 1, a plurality of shallow trench isolation structures 101 are formed, where the shallow trench isolation structures 101 are located at the boundary between the high voltage device region 10 and the medium voltage device region 20 and are distributed at intervals in the high voltage device region 10 and the medium voltage device region 20. Specifically, the shallow trench isolation structure 101 located at the boundary between the high voltage device region 10 and the medium voltage device region 20 isolates the high voltage device region 10 from the medium voltage device region 20. AA (active area) is formed in the substrate between two adjacent shallow trench isolation structures 101 in the high voltage device region 10, and similarly, AA (active area) is formed in the substrate between two adjacent shallow trench isolation structures 101 in the medium voltage device region 20. This embodiment only focuses on the process of forming the gate oxide structure in the AA region.
Next, referring to fig. 2, the substrate 100 between two adjacent shallow trench isolation structures 101 in the high-voltage device region 10 is etched to form a first trench 102. In particular, when opening the area in the high voltage device region 10, the entire liner will be coveredOn the basis that a hard mask layer is formed on the surface of the substrate 100, the high-voltage device area 10 is subjected to a photoetching process and an etching process, so that other substrates 10 which do not need to be etched and the shallow trench isolation structure 101 can be protected, and the substrates 10 which do not need to be etched and the shallow trench isolation structure 101 are prevented from being etched by mistake. Further, in this embodiment, while the substrate 100 between the shallow trench isolation structures 101 in the high-voltage device region 10 is etched, edges of two adjacent shallow trench isolation structures 101 may also be etched, that is, the first trench extends in width 102 to the shallow trench isolation structures 101 on two sides thereof. Preferably, the width of the shallow trench isolation structure 101 that is etched and opened may be the same as the width of the shallow trench isolation structure
Further, this embodiment can etch to a thickness of
And the shallow trench isolation structure 101 is etched to a thickness of
To form the first trench 102 in a stepped manner.
Further, referring to fig. 3, a first gate oxide structure 11 is formed, and the first gate oxide structure 11 fills the first trench 102. Specifically, the first gate oxide structure 11 is formed by a thermal oxidation process. Due to the particularity of the thermal oxidation process, a portion of the substrate 100 at the bottom wall of the first trench 102 is also oxidized to become a portion of the first gate oxide structure 11, and the ratio of the depth of the first trench 102 to the thickness of the finally formed first gate oxide structure 11 is about 0.54: 1. The last step etches the substrate 100 to a thickness of
I.e. the depth of the first trench 102 is
Final formed articleThe thickness of the first gate oxide structure 11 is approximately within
The upper surface of the finally formed first gate oxide structure 11 is flush with the upper surfaces of two adjacent shallow trench isolation structures 101. This application is through form the first gate oxide structure 11 that buries deeply in the substrate 100 in high-voltage device district 10 and reduce the height of the first gate oxide structure 11 in high-voltage device district 10 improves subsequently the height homogeneity of the dummyply that forms above the first gate oxide structure 11 has avoided in follow-up ILD0CMP technology the dummyply of high-voltage device district 10 is by the condition of excessive mistake grinding, has established the basis for the smooth filling of follow-up metal gate to the performance and the reliability of high-voltage device have been improved.
Finally, referring to fig. 4 to fig. 9, a second gate oxide structure 21 is formed, where the second gate oxide structure 21 is located on the substrate surface between two adjacent shallow trench isolation structures 101 in the medium voltage device region 20.
Specifically, the step of forming the second gate oxide structure 21 includes:
the first step is as follows: referring to fig. 4, a mask layer 12 is formed, and the mask layer 12 covers the shallow trench isolation structure 101, the first gate oxide structure 11, and a portion of the substrate 100. Specifically, the mask layer 12 may be silicon nitride. In this embodiment, a photoresist is coated on the mask layer 12, and then the photoresist on the mask layer 12 is opened through a photolithography process to form a defined photolithography window.
The second step is as follows: referring to fig. 5, the mask layer 12 on two adjacent shallow trench isolation structures 101 in the medium voltage device region 20 is etched to form a second trench 103 in the mask layer. Specifically, according to the lithography window defined in the previous step (the first step), a dry etching process is performed on the mask layer 12 on two adjacent shallow trench isolation structures 101 in the medium voltage device region 20, and the mask layer 12 under the defined lithography window is etched and removed to expose the substrate 100 between the two adjacent shallow trench isolation structures 101 in the medium voltage device region 20.
The third step: referring to fig. 6, a thermal oxidation process is used to form a first gate oxide layer 211, and the first gate oxide layer 211 covers the bottom wall of the second trench 103. Specifically, due to the particularity of the thermal oxidation process, the first gate oxide layer 211 is only formed on the bottom wall of the second trench 103. The thickness of the first gate oxide layer 211 grown may be
The fourth step: referring to fig. 7, an ALD (atomic layer deposition) process is used to form a second gate oxide layer 212, where the second gate oxide layer 212 covers the first gate oxide layer 211, the sidewalls of the second trench 103, and the mask layer 12. Specifically, the thickness of the second gate oxide layer 212 may be
The fifth step: referring to fig. 8, the mask layer 12 and the second gate oxide layer 212 on the sidewalls of the second trench 103 are removed. Specifically, a wet etching process may be used to remove the mask layer 12 and the second gate oxide layer 212 on the sidewall of the second trench 103.
Referring to fig. 9, the remaining mask layer 12 is removed. Specifically, the remaining mask layer 12 may be removed by a dry etching process, a wet etching process, or a wet cleaning process.
Due to the particularity of the thermal oxidation process, a void appears at a corner of a junction position (close to two sides of the lower surface of the first gate oxide layer 211) of the first gate oxide layer 211 and the shallow trench isolation structure 101, so that the coverage ratio of the first gate oxide layer 211 at the corner is lower than that of the first gate oxide layer 211 in other areas in the second trench 103. So this application is in the thermal oxidation technology is adopted to the substrate surface in middling pressure device district 20 forms after first gate oxide 211, adopt the ALD technology to form again second gate oxide 212, because second gate oxide 212 adopts ALD technology to grow, so second gate oxide 212 can fill up and cover the cavity defect of first gate oxide 211 both sides corner, second gate oxide structure 21 that this application divides the final formation of two technologies is complete in structure, has compensatied the cavity defect of the corner position of first gate oxide 211, and the structure is complete second gate oxide structure 21 is difficult to be high-voltage breakdown, has improved second gate oxide structure 21's high pressure resistant ability to the performance and the reliability of middling pressure device have been improved.
Based on the same inventive concept, the embodiment of the present application further provides a semiconductor device, including: the device comprises a substrate 100, a plurality of shallow trench isolation structures 101, a first gate oxide structure 11 and a second gate oxide structure 21, wherein the substrate 100 is provided with a high-voltage device region 10 and a medium-voltage device region 20. The shallow trench isolation structures 101 are located at the boundary between the high voltage device region 10 and the medium voltage device region 20 and are distributed in the high voltage device region 10 and the medium voltage device region 20 at intervals, wherein a first trench 102 is formed in the substrate 100 between two adjacent shallow trench isolation structures 101 in the high voltage device region 10. The first gate oxide structure 11 fills the first trench 102. The second gate oxide structure 21 is located on the surface of the substrate 100 between two adjacent shallow trench isolation structures 101 in the medium voltage device region 20.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate with a high-voltage device area and a medium-voltage device area;
forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high-voltage device area and the medium-voltage device area and are distributed in the high-voltage device area and the medium-voltage device area at intervals;
etching the substrate between two adjacent shallow trench isolation structures in the high-voltage device area to form a first trench;
forming a first gate oxide structure, wherein the first gate oxide structure fills the first groove; and the number of the first and second groups,
and forming a second gate oxide structure, wherein the second gate oxide structure is positioned on the surface of the substrate between two adjacent shallow trench isolation structures in the medium-voltage device area.
2. The method for manufacturing the semiconductor device according to claim 1, wherein the substrate between two adjacent shallow trench isolation structures of the high-voltage device region and the shallow trench isolation structure is etched to form the first trench.
3. The method of claim 2, wherein the shallow trench isolation structures etched open are all sized in width
4. The method for manufacturing a semiconductor device according to claim 2, wherein the etching thickness is
The shallow trench isolation structure is etched to a thickness of
To form the stepped first trench.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the second gate oxide structure comprises:
forming a mask layer, wherein the mask layer covers the shallow trench isolation structure, the first gate oxide structure and part of the substrate;
etching the mask layer on two adjacent shallow trench isolation structures in the medium-voltage device area to form a second trench in the mask layer;
forming a first gate oxide layer by adopting a thermal oxidation process, wherein the first gate oxide layer covers the bottom wall of the second groove;
forming a second gate oxide layer by adopting an ALD (atomic layer deposition) process, wherein the second gate oxide layer covers the first gate oxide layer, the side wall of the second groove and the mask layer;
removing the mask layer and the second gate oxide layer on the side wall of the second groove; and the number of the first and second groups,
and removing the residual mask layer.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the first gate oxide layer has a thickness of
7. The method of manufacturing a semiconductor device according to claim 5, wherein the second gate oxide layer has a thickness of
8. The method for manufacturing a semiconductor device according to claim 1, wherein the first gate oxide structure is formed by a thermal oxidation process.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the first gate oxide structure has a thickness of
10. A semiconductor device, comprising:
a substrate having a high voltage device region and a medium voltage device region therein;
the shallow trench isolation structures are positioned at the junction of the high-voltage device area and the medium-voltage device area and are distributed in the high-voltage device area and the medium-voltage device area at intervals, wherein a first trench is formed in the substrate between two adjacent shallow trench isolation structures in the high-voltage device area;
the first gate oxide structure fills the first groove; and
and the second gate oxide structure is positioned on the surface of the substrate between two adjacent shallow trench isolation structures in the medium-voltage device area.
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| CN202111139817.3A CN113937056A (en) | 2021-09-28 | 2021-09-28 | Semiconductor device and method for manufacturing the same |
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| CN202111139817.3A CN113937056A (en) | 2021-09-28 | 2021-09-28 | Semiconductor device and method for manufacturing the same |
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