CN109494255A - Deep-groove power device and its manufacturing method - Google Patents
Deep-groove power device and its manufacturing method Download PDFInfo
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- CN109494255A CN109494255A CN201811607712.4A CN201811607712A CN109494255A CN 109494255 A CN109494255 A CN 109494255A CN 201811607712 A CN201811607712 A CN 201811607712A CN 109494255 A CN109494255 A CN 109494255A
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 106
- 230000001413 cellular effect Effects 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000992 sputter etching Methods 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 48
- 238000010586 diagram Methods 0.000 description 5
- 210000000746 body region Anatomy 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 210000002706 plastid Anatomy 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
This disclosure relates to a kind of deep-groove power device, wherein, the power device is divided into cellular region and termination environment, the power device includes: substrate, it is provided with drain metal below substrate, epitaxial layer is provided on substrate, is provided with body area on said epitaxial layer there, cellular region groove is set in the body area and termination environment groove, the cellular region groove and termination environment groove extend downwardly into epitaxial layer from the surface in body area.Filled with the first conductive polycrystalline silicon being connected with source electrode and the second conductive polycrystalline silicon being connected with grid in the groove.The second dielectric body is provided between the first conductive polycrystalline silicon and the second conductive polycrystalline silicon.
Description
Technical field
The present invention relates to semiconductor fields, and in particular, to a kind of deep-groove power device and its manufacturing method.
Background technique
In power semiconductor field, deep trench MOSFET can effectively improve gully density, reduce feature conducting
Resistance and parasitic capacitance, therefore deep trench MOSFET has been widely adopted.Limitation deep trench MOSFET problem is that technique is multiple at present
Miscellaneous and control difficulty is high, and source polysilicon and grid polycrystalline silicon are formed in the groove of very little, and accurate control insulation is needed to be situated between
Plastid thickness and grid oxide layer thickness are proposed very high requirement, device performance and parameter to production equipment and manufacturing process
Consistency is also difficult to ensure.
Summary of the invention
In view of this, the purpose of the disclosure is at least partly to provide a kind of deep-groove power device with improvement structure
Part and its manufacturing method and electronic equipment including this power device.
According to an aspect of this disclosure, present disclose provides a kind of deep-groove power devices, wherein the power device quilt
It is divided into cellular region (01) and termination environment (02), the cellular region (01) is located at the center of the power device, the terminal
Area (02) is located at the outer ring of the cellular region (01) and around the cellular region (01) is surrounded, and the power device includes: substrate
(2), it is provided with drain metal (1) below substrate (2), epitaxial layer (3) is provided on substrate (2), are set on the epitaxial layer (3)
It is equipped with body area (11), setting cellular region groove (6) and termination environment groove (16), the cellular region groove in the body area (11)
(6) it is extended downwardly into epitaxial layer (3) with the surface of termination environment groove (16) Cong Tiqu.It is filled in the groove (6) and source
Extremely connected the first conductive polycrystalline silicon (5) and the second conductive polycrystalline silicon (10) being connected with grid.First conductive polycrystalline silicon
(5) it is with the first dielectric body (4) outside, is with gate oxide (8) outside second conductive polycrystalline silicon (10), in the first conduction
The second dielectric body (7) is provided between polysilicon (5) and the second conductive polycrystalline silicon (10).It is filled in the groove (16)
The third conductive polycrystalline silicon (15) of electric potential floating is with third dielectric body, institute outside the third conductive polycrystalline silicon (15)
It is identical as the material of the third dielectric body (14) to state the first dielectric body.
Wherein, the second conductive polycrystalline silicon (10) being connected with grid is located at the first conductive polycrystalline silicon (5) being connected with source electrode
Top, and the two passes through second dielectric body (7) mutually insulated.
Wherein, it is conductive to be greater than first for the center cross-sectional width of the trench region of the second conductive polycrystalline silicon (10) present position
The center cross-sectional width of trench region locating for polysilicon (5).And the center cross-sectional of the second conductive polycrystalline silicon (10) is wide
Degree is greater than the center cross-sectional width of the first conductive polycrystalline silicon (5).
Wherein, it is additionally provided with source region (12) in the body area (11), the body area (11) and the source region (12) pass through miscellaneous
Matter is injected to be formed, and implantation dosage range is 1 × 1012~1 × 1016, Implantation Energy range is 20KeV~200Kev.
Wherein, body area (11) bottom surface horizontal plane is located on the second conductive polycrystalline silicon (10) bottom surface horizontal plane.
Wherein, in cellular region (01), source metal (13), the source metal are provided with above the body area (11)
Both floor (13) and body area (11) and source region (12) all conductive contacts.
Wherein, in termination environment (02), the third conductive polycrystalline silicon (15) from termination environment groove (16) opening down
Extend.
Wherein, the substrate, the epitaxial layer and the source region are the first conduction type；The body area is second conductive
Type.
Wherein, the power device includes N-type power device and p-type power device, when the power device is the N-type
When power device, the first conduction type is N-type, and the second conduction type is p-type；When the power device is the p-type power device
When part, the first conduction type is p-type, and the second conduction type is N-type.
According to another aspect of the disclosure, present disclose provides a kind of methods for manufacturing deep-groove power device, comprising: mentions
For substrate, the substrate includes cellular region and termination environment；Then grown epitaxial layer over the substrate etches on epitaxial layer
Multiple grooves；
Photoresist is deposited, the photoresist of the groove two sides in cellular region is removed, carries out ion etching, again to expand cellular
Area's groove opening, thus the cellular region groove that shape is at T-shaped；The first dielectric is formed on cellular region channel bottom and side wall
Body is then filled with conductive polycrystalline silicon, carve, removes the conductive polycrystalline silicon on groove opening surface or more；It etches in T shape groove
Conductive polycrystalline silicon a part, the top surface position of remaining conductive polycrystalline silicon is controlled in T shape groove by adjusting etch amount；
The second dielectric body is deposited in T shape groove, isotropic etching the second dielectric body is in the upper area of T shape groove
It is middle to retain certain thickness second dielectric body；Sacrificial oxide layer is grown in T shape groove, etches away sacrificial oxide layer, then
Oxide layer is grown, etching oxidation layer is to form gate oxide on T shape trenched side-wall；Conductive polycrystalline silicon is deposited, then etching is led
Electric polysilicon forms the second conductive polycrystalline silicon for being used as Gate Electrode Conductive polysilicon；Inject the second conductive type impurity, thermal annealing shape
Adult area is then injected into the first conductive type impurity, forms source region after activation.
The method also includes: metal is deposited above body area and the source region and is performed etching, to form source metal；
The substrate bottom is carried out back thinning and metal layer on back makes, to form drain metal.
According to the another aspect of the disclosure, present disclose provides a kind of electronic equipment, including at least partly by such as above-mentioned
The integrated circuit that deep-groove power device described in any one in technical solution is formed.
Thus the power device of the disclosure forms the cellular region with T shape deep trench, and T shape deep trench helps to effectively improve
Gully density reduces specific on-resistance and parasitic capacitance, at the same time, since deep trench uses T-shape, relative increase
The width of insulating medium layer between conductive polycrystalline silicon so reducing technology difficulty and technique controlling difficulty, such as reduces
The manufacture difficulty of insulating medium layer between conductive polycrystalline silicon improves the insulating reliability of insulating medium layer, can also be accurate
It controls dielectric body thickness and grid oxide layer thickness and ensure that function to reduce the requirement to production equipment and manufacturing process
The yields of rate device and the consistency of power device performance and parameter.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 is the schematic diagram of T shape deep-groove power device according to an embodiment of the present disclosure；
Fig. 2 to Fig. 7 is the cross section for manufacturing each stage of T shape deep-groove power device according to an embodiment of the present disclosure
Block diagram；
Fig. 8 is the flow chart for manufacturing T shape deep-groove power device according to an embodiment of the present disclosure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
Power device according to the embodiment of the present disclosure may include the cellular region formed in epitaxial layer square on substrate and
Termination environment.Cellular region includes grid, cellular region groove, the conductive polycrystalline silicon in the groove of cellular region as the active area of device
With dielectric body, source electrode and drain electrode.Wherein, cellular region groove is T-shape.Cellular region includes underlying first
The second part for dividing and being located above, second part are wider than first part, that is, second part center cross-sectional width is greater than first
Partial center cross-sectional width.Conductive polycrystalline silicon in the groove of cellular region is divided into the first conductive polycrystalline silicon and the second conduction
Polysilicon, the first conductive polycrystalline silicon are located at the lower section of cellular region groove, that is, are located in relatively narrow first part, the second conductive polycrystalline
Silicon is located at the top of cellular region groove, that is, is located in wider second part.First conductive polycrystalline silicon and the second conductive polycrystalline silicon
Between, between the first conductive polycrystalline silicon and cellular region trenched side-wall and bottom, the side of the second conductive polycrystalline silicon and cellular region groove
Dielectric body is respectively formed between wall.Wherein, what is formed between the second conductive polycrystalline silicon and the side wall of cellular region groove is exhausted
Edge dielectric is used as gate oxide.First conductive polycrystalline silicon and the second conductive polycrystalline silicon, should by dielectric body mutually insulated
Dielectric body is mainly formed in the second part of cellular region groove.
Fig. 1 is the schematic diagram of T shape deep-groove power device according to an embodiment of the present disclosure.As shown in Figure 1, deep trench function
Rate device may include: substrate 2, the epitaxial layer formed on substrate 23 and the body area 11 being arranged in epitaxial layer 3.Deep trench
Power device can be divided into cellular region 01 and termination environment 02.The cellular region 01 is located in the deep-groove power device
Heart district, the termination environment 02 are located at the outer ring of the cellular region 01 and around the encirclement cellular regions 01.The shape in cellular region 01
At multiple cellular region grooves 6, multiple termination environment grooves 16 are formed in the termination region.Cellular region groove 6 and termination environment groove 16 from
The upper surface in body area 11 extends downwardly into epitaxial layer 3.Termination environment groove 16 is common straight-through groove, and cellular region groove 6
For T shape groove.Conductive polycrystalline silicon and dielectric body are filled in termination environment groove 16 and cellular region groove 6.Specifically, first
It is filled with the first conductive polycrystalline silicon 5 and the second conductive polycrystalline silicon 10 in born of the same parents area groove 6, is led in termination environment groove 16 filled with third
Electric polysilicon 15.First conductive polycrystalline silicon 5 is located at 10 lower section of the second conductive polycrystalline silicon, and the first conductive polycrystalline silicon 5 and source electrode phase
Even, the second conductive polycrystalline silicon 10 is connected with grid.15 electric potential floating of third conductive polycrystalline silicon.It is with outside first conductive polycrystalline silicon 5
First dielectric body 4 is with gate oxidation outside the second conductive polycrystalline silicon 10 to insulate with the bottom and inner sidewall of cellular region groove 6
Layer 8 is provided with the second dielectric body 7 between the first conductive polycrystalline silicon 5 and the second conductive polycrystalline silicon 10 to realize that first leads
Mutually insulated between electric polysilicon 5 and the second conductive polycrystalline silicon 10.Third dielectric is with outside third conductive polycrystalline silicon 15
Body 14 with the bottom and inner sidewall of termination environment groove 16 to insulate.First dielectric body 4 and the third dielectric body 14
Material it is identical.As shown in Figure 1, deep-groove power device further includes the source region 12 in the body area 11 of cellular region and is located at
The drain electrode 1 of substrate back.
The substrate 2, the epitaxial layer 3 and the source region 12 are the first conduction type；It is led for second in the body area 11
Electric type.Deep-groove power device includes N-type power device and p-type power device, when the power device is the N-type power
When device, the first conduction type is N-type, and the second conduction type is p-type；When the power device is the p-type power device,
First conduction type is p-type, and the second conduction type is N-type.
Fig. 2 to Fig. 7 is the cross section for manufacturing each stage of T shape deep-groove power device according to an embodiment of the present disclosure
Block diagram.
As shown in Fig. 2, providing substrate 1, substrate 1 for example can be silicon substrate, be epitaxially-formed epitaxial layer on substrate 1
2, both substrate 1 and epitaxial layer 2 can be the first conduction type, such as N-type.Then selective etch goes out on epitaxial layer 2
Multiple deep trench, the etching can for example use ion etching.Multiple deep trench in termination environment 02 are formed as terminal
Area's groove 16.
As shown in figure 3, deposit photoresist, removes the photoresist of active area deep trench two sides, carries out ion etching again, with
The opening for expanding the groove being located in cellular region, thus in the at T-shaped groove of cellular region shape, i.e. the at T-shaped cellular region groove 6 of shape.Such as
Shown in Fig. 3, T shape cellular region groove 6 is formed to have wider top and relatively narrow lower part, that is, the top of cellular region groove 6
Center cross-sectional width is greater than the center cross-sectional width of the lower part of cellular region groove 6.
As shown in figure 4, forming dielectric body 4 in the bottom and side wall of cellular region groove 6 and termination environment groove 16 respectively
With 14；It is then filled with conductive polycrystalline silicon, carve, removes leading for the top of cellular region groove 6 and termination environment groove 16 or more
Electric polysilicon；Then photoresist is deposited, selective etch falls in the groove of T shape cellular region 6 partially electronically conductive polysilicon, passes through adjusting
Etch amount controls the top position of conductive polycrystalline silicon, so that the conductive polycrystalline silicon in the top of T shape cellular region groove 6 is gone
It removes, so that retaining the conductive polycrystalline silicon being located in relatively narrow lower part in cellular region groove 6 only for use as the first conductive polycrystalline
Silicon 5.The first dielectric body 4 is with outside first conductive polycrystalline silicon 5 to insulate with the bottom and inner sidewall of cellular region groove 6, the
Third dielectric body 14 is with outside three conductive polycrystalline silicons 15 to insulate with the bottom and inner sidewall of termination environment groove 16.
As shown in figure 5, being separately filled with the second dielectric body 7, gate oxide 8 in the top of T shape cellular region groove 6
With the second conductive polycrystalline silicon 10.Specifically, in the T shape cellular region for being filled with the first conductive polycrystalline silicon 5 and the first dielectric body 4
Deposit dielectric body material in groove 6, isotropic etching dielectric body material is partially to remove the top of T shape groove 6
Dielectric body material in region, monitors the thickness of remaining dielectric body material, to retain the upper zone for being located at groove 6
Dielectric body material on the bottom in domain is for use as the second dielectric body 7.
Wherein it is possible to be insulated by the thickness for monitoring remaining dielectric body material come real-time control finally formed second
The thickness of dielectric 7.Further, since the second dielectric body 7 is formed in the wider upper area of T shape groove 6, therefore can
To control the formation process of the second dielectric body accurately to guarantee the reliability of power device.
As shown in figure 5, carry out sacrificing oxidation and etch, it is thermally grown to be formed on the upper area side wall for being located at T shape groove 6
Gate oxide 8 specifically grows sacrificial oxide layer above T shape groove the second dielectric body and then etches away sacrifice oxidation
Thus layer, regrowth gate oxide 8 utilize the lattice defect of the growth restoring area of sacrificial oxide layer and reduce harmful particle
And ion, to facilitate gate oxide 8 best in quality at growth.After forming gate oxide 8, conductive polycrystalline is deposited
Silicon, then etching conductive polysilicon forms the second conductive polycrystalline silicon 10 for being used as Gate Electrode Conductive polysilicon.
As shown in fig. 6, it is miscellaneous to inject the second conduction type between cellular region groove 6 and between termination environment groove 16
Matter, thermal annealing form the second conductivity type body region 11, then inject the first conductive type impurity in the cellular region area Zhong Ti 11,
The first conduction type source region 12 is formed after activation.Wherein, the implantation dosage range for carrying out ion implanting is 1 × 1012~1 ×
1016, Implantation Energy range is 20KeV~200Kev.In addition, the 11 bottom surface horizontal plane of the second conductivity type body region being formed by
On the 10 bottom surface horizontal plane of the second conductive polycrystalline silicon.
As shown in fig. 7, dielectric body is deposited above entire device to form interlayer dielectric body 9, and to interlayer
Dielectric body 9 is masked etching to form opening until exposing body area upper surface, then etches body area silicon materials, then infuses
Enter the second conductive type impurity, and activate, deposits source metal 13, finally to form source electrode.As shown in fig. 7, source metal
Both the area Ceng13Yu Ti 11 and source region 12 all conductive contacts.
In addition, as shown in fig. 7,2 bottom of substrate is carried out back thinning and metal layer on back production, with formed drain electrode
Metal layer 1, to form the drain electrode of power device.Drain metal layer 1 covers the back side of entire substrate 2.It is possible thereby to form tool
There is the power device of T shape groove.
Fig. 8 is the flow chart for manufacturing T shape deep-groove power device according to an embodiment of the present disclosure.Wherein, specific to record
Following steps:
Step S110: substrate is provided, the substrate includes cellular region and termination environment；
Step S120: then grown epitaxial layer over the substrate etches multiple grooves on epitaxial layer；
Step S130: deposit photoresist removes the photoresist of the groove two sides in cellular region, carries out ion etching again,
To expand cellular region groove opening, thus the cellular region groove that shape is at T-shaped；
Step S140: the first dielectric body is formed on cellular region channel bottom and side wall, is then filled with conductive polycrystalline
Silicon carve, removes the conductive polycrystalline silicon on groove opening surface or more；
Step S150: a part of the conductive polycrystalline silicon in etching T shape groove controls T shape ditch by adjusting etch amount
The top surface position of remaining conductive polycrystalline silicon in slot；
Step S160: depositing the second dielectric body in T shape groove, isotropic etching the second dielectric body with
Retain certain thickness second dielectric body in the upper area of T shape groove；
Step S170: growing sacrificial oxide layer in T shape groove, etches away sacrificial oxide layer, regrowth oxide layer, etching
Oxide layer is to form gate oxide on T shape trenched side-wall；
Step S180: deposit conductive polycrystalline silicon, then etching conductive polysilicon, which is formed, is used as the of Gate Electrode Conductive polysilicon
Two conductive polycrystalline silicons；
Step S190: the second conductive type impurity of injection, thermal annealing form body area, it is miscellaneous to be then injected into the first conduction type
Matter forms source region after activation；
Step S200: metal is deposited above body area and the source region and is performed etching, to form source metal, to described
Substrate bottom is carried out back thinning to be made with metal layer on back, to form drain metal.
By above-mentioned processing step, the power device with T shape deep trench according to the embodiment of the present disclosure is formed, wherein T
Shape groove is formed in cellular region, and T shape groove planform wide at the top and narrow at the bottom helps to be easy wherein filling leading for different layers
Electric polysilicon, it helps accurate control is filled in the thickness of the dielectric body between upper and lower level conductive polycrystalline silicon, to protect
The reliability for having demonstrate,proved the dielectric body of filling, to improve the yields and performance of power device, while reducing technique
It is required that.
Although it have been described that example embodiment, it should be apparent to those skilled in the art that not
In the case where the spirit and scope for being detached from present inventive concept, it can make various changes and modifications.It will thus be appreciated that above-mentioned
Example embodiment is not limiting, but illustrative.
Claims (12)
1. a kind of deep-groove power device, wherein the power device is divided into cellular region (01) and termination environment (02), described
Cellular region (01) is located at the center of the power device, and the termination environment (02) is located at the outer ring of the cellular region (01) and ring
Around the cellular region (01) is surrounded, the power device includes: substrate (2), is provided with drain metal (1), serves as a contrast below substrate (2)
It is provided with epitaxial layer (3) on bottom (2), is provided on the epitaxial layer (3) body area (11), cellular is set in the body area (11)
The surface of area's groove (6) and termination environment groove (16), the cellular region groove (6) and termination environment groove (16) Cong Tiqu are to downward
It reaches in epitaxial layer (3).It is filled with the first conductive polycrystalline silicon (5) being connected with source electrode in the groove (6) and is connected with grid
The second conductive polycrystalline silicon (10).It is with the first dielectric body (4) outside first conductive polycrystalline silicon (5), described second leads
Gate oxide (8) are with outside electric polysilicon (10), are arranged between the first conductive polycrystalline silicon (5) and the second conductive polycrystalline silicon (10)
There is the second dielectric body (7).The third conductive polycrystalline silicon (15) of electric potential floating is filled in the groove (16), described the
Third dielectric body, the first dielectric body and the third dielectric body are with outside three conductive polycrystalline silicons (15)
(14) material is identical.
2. deep-groove power device according to claim 1, wherein the second conductive polycrystalline silicon (10) position being connected with grid
Above the first conductive polycrystalline silicon (5) being connected with source electrode, and the two passes through second dielectric body (7) mutually insulated.
3. deep-groove power device according to claim 2, wherein the groove of the second conductive polycrystalline silicon (10) present position
The center cross-sectional width in region is greater than the center cross-sectional width of trench region locating for the first conductive polycrystalline silicon (5).And
The center cross-sectional width of second conductive polycrystalline silicon (10) is greater than the center cross-sectional width of the first conductive polycrystalline silicon (5).
4. deep-groove power device according to claim 1, wherein source region (12) are additionally provided in the body area (11),
The body area (11) and the source region (12) are injected to be formed by impurity, and implantation dosage range is 1 × 1012~1 × 1016, injection
Energy range is 20KeV~200Kev.
5. deep-groove power device according to claim 4, wherein body area (11) bottom surface horizontal plane is located at described second
On conductive polycrystalline silicon (10) bottom surface horizontal plane.
6. deep-groove power device according to claim 1, wherein in cellular region (01), above the body area (11)
It is provided with source metal (13), the source metal (13) and both body area (11) and source region (12) all conductive contacts.
7. deep-groove power device according to claim 1, wherein in termination environment (02), the third conductive polycrystalline
Silicon (15) extends down from termination environment groove (16) opening.
8. deep-groove power device according to claim 1 or 4, wherein the substrate, the epitaxial layer and the source region
It is the first conduction type；The body area is the second conduction type.
9. deep-groove power device according to claim 8, wherein the power device includes N-type power device and p-type
Power device, when the power device is the N-type power device, the first conduction type is N-type, and the second conduction type is P
Type；When the power device is the p-type power device, the first conduction type is p-type, and the second conduction type is N-type.
10. a kind of method for manufacturing deep-groove power device, comprising:
Substrate is provided, the substrate includes cellular region and termination environment；
Then grown epitaxial layer over the substrate etches multiple grooves on epitaxial layer；
Photoresist is deposited, the photoresist of the groove two sides in cellular region is removed, carries out ion etching, again to expand cellular region ditch
Channel opening, thus the cellular region groove that shape is at T-shaped；
The first dielectric body is formed on cellular region channel bottom and side wall, is then filled with conductive polycrystalline silicon, carve, is gone
Except conductive polycrystalline silicon more than groove opening surface；
The a part for etching the conductive polycrystalline silicon in T shape groove is controlled remaining conductive more in T shape groove by adjusting etch amount
The top surface position of crystal silicon；
The second dielectric body is deposited in T shape groove, isotropic etching the second dielectric body is on the top of T shape groove
Retain certain thickness second dielectric body in region；
Sacrificial oxide layer is grown in T shape groove, etches away sacrificial oxide layer, regrowth oxide layer, etching oxidation layer is in T shape
Gate oxide is formed on trenched side-wall；
Conductive polycrystalline silicon is deposited, then etching conductive polysilicon forms the second conductive polycrystalline silicon for being used as Gate Electrode Conductive polysilicon；
The second conductive type impurity is injected, thermal annealing forms body area, is then injected into the first conductive type impurity, forms source after activation
Area.
11. the method for manufacture deep-groove power device according to claim 10, further includes:
Metal is deposited above body area and the source region and is performed etching, to form source metal；
The substrate bottom is carried out back thinning and metal layer on back makes, to form drain metal.
12. a kind of electronic equipment, including at least partly by deep-groove power as in one of claimed in any of claims 1 to 9
The integrated circuit that device is formed.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047757A (en) * | 2019-04-24 | 2019-07-23 | 贵州芯长征科技有限公司 | The preparation method of the trench-type power semiconductor device of low cost |
| CN112951914A (en) * | 2019-12-11 | 2021-06-11 | 恒泰柯半导体（上海）有限公司 | Deep trench MOSFET terminal structure and preparation method thereof |
| CN113257902A (en) * | 2021-06-10 | 2021-08-13 | 南京晟芯半导体有限公司 | IGBT device with oscillation suppression effect and manufacturing method thereof |
| CN118016593A (en) * | 2024-04-09 | 2024-05-10 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060214221A1 (en) * | 2003-05-20 | 2006-09-28 | Ashok Challa | Power semiconductor devices and methods of manufacture |
| US20180337236A1 (en) * | 2017-05-19 | 2018-11-22 | Super Group Semiconductor Co., Ltd. | Trench power semiconductor component and method of manufacturing the same |
| CN209461469U (en) * | 2018-12-26 | 2019-10-01 | 上海昱率科技有限公司 | Deep-groove power device and electronic equipment |
-
2018
- 2018-12-26 CN CN201811607712.4A patent/CN109494255A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060214221A1 (en) * | 2003-05-20 | 2006-09-28 | Ashok Challa | Power semiconductor devices and methods of manufacture |
| US20180337236A1 (en) * | 2017-05-19 | 2018-11-22 | Super Group Semiconductor Co., Ltd. | Trench power semiconductor component and method of manufacturing the same |
| CN209461469U (en) * | 2018-12-26 | 2019-10-01 | 上海昱率科技有限公司 | Deep-groove power device and electronic equipment |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047757A (en) * | 2019-04-24 | 2019-07-23 | 贵州芯长征科技有限公司 | The preparation method of the trench-type power semiconductor device of low cost |
| CN112951914A (en) * | 2019-12-11 | 2021-06-11 | 恒泰柯半导体（上海）有限公司 | Deep trench MOSFET terminal structure and preparation method thereof |
| CN113257902A (en) * | 2021-06-10 | 2021-08-13 | 南京晟芯半导体有限公司 | IGBT device with oscillation suppression effect and manufacturing method thereof |
| CN113257902B (en) * | 2021-06-10 | 2021-09-21 | 南京晟芯半导体有限公司 | IGBT device with oscillation suppression effect and manufacturing method thereof |
| CN118016593A (en) * | 2024-04-09 | 2024-05-10 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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