CN110047757A - The preparation method of the trench-type power semiconductor device of low cost - Google Patents
The preparation method of the trench-type power semiconductor device of low cost Download PDFInfo
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- CN110047757A CN110047757A CN201910334710.0A CN201910334710A CN110047757A CN 110047757 A CN110047757 A CN 110047757A CN 201910334710 A CN201910334710 A CN 201910334710A CN 110047757 A CN110047757 A CN 110047757A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 123
- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 633
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 20
- 210000000746 body region Anatomy 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 183
- 239000002184 metal Substances 0.000 claims description 95
- 229910052751 metal Inorganic materials 0.000 claims description 95
- 230000001413 cellular effect Effects 0.000 claims description 73
- 239000012535 impurity Substances 0.000 claims description 34
- 238000001259 photo etching Methods 0.000 claims description 33
- 238000002161 passivation Methods 0.000 claims description 32
- 239000002019 doping agent Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 230000003628 erosive effect Effects 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 37
- 230000004913 activation Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The present invention relates to a kind of preparation methods of the trench-type power semiconductor device of low cost, substrate terminal groove is arranged in the termination environment of semiconductor substrate in it, second conductivity type body region of termination environment and substrate terminal groove cooperatively form required terminal plot structure, and it obtains not needing mask when the second conductivity type body region, compared with the prior art, trench-type power semiconductor device is enabled, less with one piece of mask, to effectively reduce the preparation cost of power semiconductor in Facad structure preparation.Utilize the second conduction type base region of substrate existing in active area, it is able to achieve and the doping concentration of the second conduction type in active area is adjusted, it ensure that the on state characteristic of the prepared breakdown characteristics for obtaining power semiconductor termination environment and active area, entire technical process is compatible with prior art, securely and reliably.
Description
Technical field
The present invention relates to a kind of preparation method, especially a kind of preparation side of the trench-type power semiconductor device of low cost
Method belongs to the technical field of power semiconductor preparation process.
Background technique
Currently, power semiconductor develops rapidly, on the one hand, the technology of IGBT and VDMOS is constantly reformed, to realize
Excellent performance；On the other hand, low cost also becomes pursuing a goal for power semiconductor development.Power semiconductor processing charges
In, the cost of mask plate and corresponding photoetching process are often main, therefore reduce mask plate quantity as reduction device
The key of cost.In most of the cases, the relationship often compromised between high performance device and low cost, unless there is new device
Part, process etc..
It is the step of preparation process of existing trench-type power semiconductor device Facad structure, specifically as shown in Fig. 1~Figure 11
Ground,
As shown in Figure 1, providing the semiconductor substrate 1 of N-type, and the first light of coated substrate on the front of semiconductor substrate 1
Photoresist layer 2 carries out photoetching to the first photoresist layer of substrate 2 using the first mask of substrate 3, to obtain the first photoetching of through substrate
The first photoresist layer of substrate window 4 of glue-line 2.
As shown in Fig. 2, using the first photoresist layer of substrate 2 and the first photoresist layer of substrate window 4 to semiconductor substrate 1
Front injected, to obtain the end ring 5 positioned at termination environment, the substrate of the end ring 5 and the first photoresist layer of substrate 2
First photoresist layer window 4 is corresponding.
As shown in figure 3, removal the first photoresist layer of aforesaid substrate 2, and in the front setting field oxygen of above-mentioned semiconductor substrate 1
Change layer 7, the second photoresist layer of substrate 8 being covered on the field oxide 7, using the second mask of substrate 6 to substrate second
Photoresist layer 8 carries out photoetching, and using the second photoresist layer of substrate 8 after photoetching to field oxide 7 corresponding with active area into
Row etching, so as to obtain the field oxide 7 being located on termination environment；
As shown in figure 4, removal the second photoresist layer of aforesaid substrate 8, and in the active area of above-mentioned semiconductor substrate 1 and field
Coated substrate third photoresist layer 9 in oxide layer 7 carries out light to substrate third photoresist layer 9 using substrate third mask 10
It carves, to obtain the substrate third photoresist layer window 12 of through substrate third photoresist layer 9；Utilize substrate third photoresist layer 9
And substrate third photoresist layer window 12 performs etching the semiconductor substrate 1 of active area, with what is be located in active area
Active area groove 11.
As shown in figure 5, removal aforesaid substrate third photoresist layer 9, the growth insulation grid oxygen in above-mentioned active area groove 11
Change layer 13, and fills groove conductive polycrystalline silicon 14 in the active area groove 11 that growth has insulation gate oxide 13, and etch away
Extra polysilicon.
As shown in fig. 6, carrying out the injection and propulsion of P-type ion in the top of above-mentioned semiconductor substrate 1, have to obtain being located at
Substrate P type base area 15 in source region, meanwhile, P-type ion can be stopped to be placed to end using the field oxide 7 on semiconductor substrate 1
Petiolarea, substrate P type base area 15 are located at the top of 11 slot bottom of active area groove.
As shown in fig. 7, carrying out the merging and propulsion of N-type ion in the top of above-mentioned semiconductor substrate 1, have to obtain being located at
Substrate N+ active layer 16 in source region, the substrate N+ active layer 16 are located at the top of substrate P type base area 15, utilize field oxide
7 can stop N-type ion to be injected into terminal area.
As shown in figure 8, the dielectric layer deposition on the front of above-mentioned semiconductor substrate 1, the dielectric layer are covered on substrate N+
On active layer 16 and field oxide 7, to obtain substrate medium layer 17, the substrate medium layer 17 covers active area groove 11
Notch；The 4th photoresist layer 18 of coated substrate on substrate medium layer 17, using the 4th mask 19 of substrate to the 4th light of substrate
Photoresist layer 18 carries out photoetching, to obtain the 4th photoresist layer window 20 of substrate of the 4th photoresist layer 18 of through substrate, the base
The 4th photoresist layer window 20 of plate is located at the top of active area.
As shown in figure 9, using the 4th photoresist layer 18 of substrate and the 4th photoresist layer window 20 of substrate to substrate media
Layer 17, substrate N+ active layer 16 perform etching, to obtain substrate contact hole 24 corresponding with the 4th photoresist layer window 20 of substrate,
The 24 through substrate dielectric layer 17 of substrate contact hole, and substrate N+ source region 23 is obtained in the two sides of active area groove 11.
As shown in Figure 10, the 4th photoresist layer 18 of aforesaid substrate is removed, and carries out metal shallow lake in the front of semiconductor substrate 1
Product, to obtain front metal layer, the front metal layer is covered on substrate medium layer 17 and is filled in substrate contact hole 24.
The 5th photoresist layer 26 of coated substrate on front metal layer, and using the 5th mask 27 of substrate to substrate the 5th
Photoresist layer 26 carries out photoetching, described to obtain the 5th photoresist layer window 28 of substrate of the 5th photoresist layer 26 of through substrate
The 5th photoresist layer window 28 of substrate is located at the top of termination environment.Utilize the 5th photoresist layer 26 of substrate and the 5th photoetching of substrate
Glue-line window 28 performs etching substrate front side metal layer, separates hole 22 to obtain substrate metal, front metal layer passes through substrate
Metal separation hole 22 forms substrate terminal front metal 25 and substrate cellular front metal 21 after separating.
As shown in figure 11, it is passivated layer deposit in the positive top of above-mentioned semiconductor substrate 1, it is blunt to obtain substrate front side
Change layer 29, the substrate front side passivation layer 29 is covered on substrate terminal front metal layer 25 and substrate cellular front metal layer 21
On, and substrate front side passivation layer 29 is filled in substrate metal and separates in hole 22.
The 6th photoresist layer 30 of coated substrate on substrate front side passivation layer 29, and using the 6th mask 31 of substrate to base
The 6th photoresist layer 30 of plate carries out photoetching, and using the 6th photoresist layer 30 of substrate after photoetching to substrate front side passivation layer 29 into
Capable etching can be incited somebody to action with obtaining the substrate source pad hole 32 of through substrate front passivation layer 29 by substrate source pad hole 32
Substrate cellular front metal layer 21 exposes.
After removing the 6th photoresist layer 30 of substrate, the procedure of processing of source pad can be carried out；In addition, in semiconductor substrate
1 back side also needs to carry out back process, according to the available required MOSFET element of difference or IGBT device of back process
Part, back process can use existing common processing step, no longer superfluous herein specially known to those skilled in the art
It states.
To sum up, at least need to provide six masks when carrying out positive technique for MOSFET element or IGBT device
Version, with using the corresponding lithographic process steps of corresponding mask progress so that the MOSFET element that is prepared or
The preparation cost of IGBT device is higher.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, the groove type power for providing a kind of low cost is partly led
The preparation method of body device, can be compatible with prior art, reduces the preparation cost of power semiconductor, securely and reliably.
According to technical solution provided by the invention, a kind of preparation method of the trench-type power semiconductor device of low cost,
The preparation method includes the following steps:
Step 1 provides the semiconductor substrate with the first conduction type, and carries out groove quarter to the semiconductor substrate
Erosion, to obtain required substrate trenches, the substrate trenches include positioned at the substrate cellular groove of active area and positioned at terminal
The substrate terminal groove in area；
Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain covering substrate cellular trench wall
Cellular insulating oxide and the terminating insulation oxide layer for covering substrate terminal trench wall；There is cellular insulating oxide in growth
Substrate cellular groove in fill substrate cellular conductive polycrystalline silicon, meanwhile, have the substrate terminal of terminating insulation oxide layer in growth
Substrate terminal conductive polycrystalline silicon is filled in groove；
Step 3, the injection and propulsion that the second conductive type impurity ion is carried out on the front of above-mentioned semiconductor substrate, with
Obtain crossing the second conductivity type body region of semiconductor substrate internal upper part, second conductivity type body region is located at substrate trenches slot
The top at bottom；
Step 4, the front surface coated photoresist layer in above-mentioned semiconductor substrate, using the second mask of substrate to coated
Photoresist layer carries out photoetching, to obtain the second photoresist layer of substrate being covered in semiconductor substrate terminal area；
Step 5 carries out the first conductive type impurity ion, the to above-mentioned semiconductor substrate using the second photoresist layer of substrate
The injection of two conductive type impurity ions, and the second photoresist layer of substrate is removed after the implantation, it obtains being located at semiconductor after annealing
The second conduction type base region of substrate the first conduction type source dopant region and substrate in the active area of substrate, the substrate second
Conduction type base region is located at the top of substrate cellular groove slot bottom, and substrate the first conduction type source dopant region is located at substrate second and leads
Above electric type base area, first conduction type of substrate source dopant region, the second conduction type base region of substrate are and respective substrate
The lateral wall of cellular groove contacts；
Step 6 carries out dielectric layer deposition in the front of above-mentioned semiconductor substrate, positive to obtain covering semiconductor substrate
Substrate dielectric layer；The coated substrate third photoresist layer on substrate dielectric layer, using substrate third mask to substrate third light
Photoresist layer carries out photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer；
Step 7, using above-mentioned substrate third photoresist layer and substrate third photoresist layer window to substrate dielectric layer into
Row etching, to obtain the media contact hole of Through-substrate dielectric layer and the first conduction type of substrate source dopant region, substrate first
Conduction type source dopant region can form required substrate the first conduction type source region by media contact hole；
Step 8, the above-mentioned substrate third photoresist layer of removal, and the deposited metal on above-mentioned substrate dielectric layer, to obtain
Substrate face metal layer, the substrate face metal layer are covered on substrate dielectric layer and are filled in media contact hole, filling
In substrate face metal layer and the second conduction type base region of substrate the first conduction type source region and substrate in media contact hole
Ohmic contact；
Step 9, the 4th photoresist layer of coated substrate on above-mentioned substrate face metal layer, utilize the 4th mask pair of substrate
The 4th photoresist layer of substrate carries out photoetching, to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate, benefit
Substrate face metal layer is performed etching with the 4th photoresist layer of substrate and the 4th photoresist layer window of substrate, to be penetrated through
The substrate metal of substrate face metal layer separates hole, and can separate to obtain by substrate face metal layer using substrate metal separation hole
Substrate cellular front metal layer and substrate terminal front metal layer, the substrate cellular front metal layer and substrate first are conductive
Type source region and substrate the second conduction type base region Ohmic contact；
Step 10, above-mentioned the 4th photoresist layer of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate cellular
Substrate face passivation layer on front metal layer, substrate terminal front metal layer, and the substrate face passivation layer also fill up in
Substrate metal separates in hole；
Step 11, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, utilize the 5th mask layer of substrate
Photoetching is carried out to the 5th photoresist layer of substrate, and substrate face passivation layer is carried out using the 5th photoresist layer of substrate after photoetching
Etching, to obtain the substrate source pad hole of Through-substrate front passivation layer, by substrate source pad hole can make with it is described
The just corresponding substrate cellular front metal layer of substrate source pad hole exposes；
Step 12, above-mentioned the 5th photoresist layer of substrate of removal, and required back side work is carried out at the back side of semiconductor substrate
Skill.
In step 1, in the first photoresist layer of front surface coated substrate of the semiconductor substrate, the first mask of substrate is utilized
Photoetching is carried out to the first photoresist layer of substrate, to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate,
After etching using the first photoresist layer of substrate and substrate the first photoresist layer window to the front of semiconductor substrate, institute can be obtained
The substrate trenches needed.
The material of the semiconductor substrate includes silicon.
In step 2, cellular insulating oxide and terminating insulation oxide layer are same processing step layer, cellular insulating oxide
Layer, terminating insulation oxide layer are silicon dioxide layer.
The doping concentration of second conduction type base region of substrate is greater than the doping concentration of the second conductivity type body region.
In " first conduction type " and " the second conduction type " the two, N-type power semiconductor, first is led
Electric type refers to N-type, and the second conduction type is p-type；For p-type power semiconductor, the first conduction type and the second conductive-type
The type and N-type power semiconductor of type meaning are exactly the opposite.
Advantages of the present invention: substrate terminal groove is set in the termination environment of semiconductor substrate, and in substrate terminal groove
Terminating insulation oxide layer and substrate terminal conductive polycrystalline silicon are set, and it is miscellaneous to carry out the second conduction type in the front of semiconductor substrate
Matter ion implanting, can obtain the second conductivity type body region, and the second conductivity type body region of termination environment and substrate terminal groove cooperate
Terminal plot structure needed for being formed, and obtain not needing mask when the second conductivity type body region, compared with the prior art, so that
Trench-type power semiconductor device can effectively reduce power semiconductor less with one piece of mask when prepared by Facad structure
Preparation cost.
Using the second photoresist layer of substrate N-type impurity ion implanting, p type impurity can be carried out to the active area of semiconductor substrate
Ion can obtain substrate the first conduction type source dopant region and lining after removal the second photoresist layer of substrate and annealing activation
The second conduction type base region of bottom can be reduced in the case where guaranteeing the second conduction type base region of substrate doping concentration using mask
Version, further reduces the cost.Using the second conduction type base region of substrate in active area, it is able to achieve conductive in active area second
The doping concentration of type is adjusted, and ensure that prepared breakdown characteristics for obtaining power semiconductor termination environment and active
The on state characteristic in area, entire technical process is compatible with prior art, securely and reliably.
Detailed description of the invention
Fig. 1~Figure 11 is the specific step of preparation process cross-sectional view of existing power semiconductor, wherein
Fig. 1 is to obtain the cross-sectional view after substrate the first photoresist layer window.
Fig. 2 is the cross-sectional view after obtaining end ring.
Fig. 3 is the schematic diagram after performing etching to the field oxide of active area.
Fig. 4 is to obtain the cross-sectional view after active area groove.
Fig. 5 is to obtain the cross-sectional view after groove conductive polycrystalline silicon.
Fig. 6 is to obtain the cross-sectional view behind substrate P type base area.
Fig. 7 is to obtain the cross-sectional view after substrate N+ active layer.
Fig. 8 is to obtain the cross-sectional view after the 4th photoresist layer window of substrate.
Fig. 9 is to obtain the cross-sectional view after substrate contact hole.
Figure 10 is to obtain substrate metal to separate the cross-sectional view behind hole.
Figure 11 is to obtain the cross-sectional view behind substrate source pad hole.
Figure 12~Figure 19 is specific implementation process step cross-sectional view of the present invention, wherein
Figure 12 is that the present invention obtains the cross-sectional view after substrate trenches.
Figure 13 is that the present invention obtains the cross-sectional view after substrate cellular conductive polycrystalline silicon, substrate terminal conductive polycrystalline silicon.
Figure 14 is that the present invention obtains the cross-sectional view behind p-type base area.
Figure 15 is that the present invention obtains the cross-sectional view after the second photoresist layer of substrate.
Figure 16 is that the present invention obtains the cross-sectional view behind the source dopant region substrate N+.
Figure 17 is that the present invention obtains the cross-sectional view after substrate third photoresist layer window.
Figure 18 is that the present invention obtains the cross-sectional view behind media contact hole.
Figure 19 is that the present invention obtains the cross-sectional view behind substrate metal separation hole.
Figure 20 is that the present invention obtains the cross-sectional view after substrate source pad hole.
Description of symbols: 1- semiconductor substrate, the first photoresist layer of 2- substrate, the first mask of 3- substrate, 4- substrate
First photoresist layer window, 5- end ring, the second mask of 6- substrate, 7- field oxide, the second photoresist layer of 8- substrate, 9- base
Plate third photoresist layer, 10- substrate third mask, 11- active area groove, 12- substrate third photoresist layer window, 13- are exhausted
Edge gate oxide, 14- groove conductive polycrystalline silicon, 15- substrate P type base area, 16- substrate N+ active layer, 17- substrate medium layer, 18-
The 4th photoresist layer of substrate, the 4th mask of 19- substrate, the 4th photoresist layer window of 20- substrate, 21- substrate cellular front gold
Belong to, 22- substrate metal separates hole, 23- substrate N+ source region, 24- substrate contact hole, 25- substrate terminal front metal, 26- substrate
5th photoresist layer, the 5th mask of 27- substrate, the 5th photoresist layer window of 28- substrate, 29- substrate front side passivation layer, 30-
The 6th photoresist layer of substrate, the 6th mask of 31- substrate, 32- substrate source pad hole, the first photoresist layer of 33- substrate, 34-
The first mask of substrate, 35- substrate terminal groove, 36- substrate cellular groove, 37- terminating insulation oxide layer, 38- substrate terminal
Conductive polycrystalline silicon, the area 39-P Xing Ti, the second photoresist layer of 40- substrate, the second mask of 41- substrate, 42- substrate p-type base area,
43- substrate third photoresist layer, 44- substrate third mask, 45- substrate third photoresist layer window, 46- substrate N+ source doping
Area, 47- substrate N+ source region, 48- media contact hole, the 4th mask of 49- substrate, the 4th photoresist layer of 50- substrate, 51- substrate
Terminal front side metal layer, the 4th photoresist layer window of 52- substrate, 53- substrate dielectric layer, 54- substrate face passivation layer, 55- lining
The 5th photoresist layer of bottom, the 5th mask of 56- substrate, 57- substrate source pad hole, 58- semiconductor substrate, 59- substrate cellular
Conductive polycrystalline silicon, 60- cellular insulating oxide, 61- substrate cellular front metal layer and 62- substrate metal separate hole.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
As shown in Figure 12~Figure 19: the trench-type power semiconductor device in order to which low cost is prepared, with N-type power
Semiconductor devices is in order to be illustrated specific step of preparation process of the invention, and specifically, the preparation method includes as follows
Step:
Step 1 provides the semiconductor substrate 58 of N-type, and carries out etching groove to the semiconductor substrate 58, to obtain
The substrate trenches needed, the substrate trenches include that the substrate cellular groove 36 positioned at active area and the substrate positioned at termination environment are whole
Hold groove 35；
Specifically, the material of semiconductor substrate 58 includes silicon, and certainly, semiconductor substrate 58 can also be common using other
Semiconductor material, concrete type, which can according to need, to be selected, no longer superfluous herein specially known to those skilled in the art
It states.When it is implemented, utilizing the first mask of substrate in the first photoresist layer of front surface coated substrate 33 of the semiconductor substrate 58
34 pairs of first photoresist layers of substrate 33 of version carry out photoetching, to obtain the first photoresist of substrate of the first photoresist layer of Through-substrate 33
Layer window etches the front of semiconductor substrate using the first photoresist layer of substrate 33 and substrate the first photoresist layer window
Afterwards, required substrate trenches can be obtained, as shown in figure 12.
In the embodiment of the present invention, substrate cellular groove 36 is located in the active area of semiconductor substrate 58, substrate terminal groove
35 are located in the termination environment of semiconductor substrate 58, and active area is normally at the central area of semiconductor substrate 58, and termination environment is located at
The outer ring of active area, the relative positional relationship between active area, termination environment are that those skilled in the art sets as needed,
Specially known to those skilled in the art, details are not described herein again.Substrate cellular groove 36, substrate terminal groove 35 have identical
Depth, substrate cellular groove 36, substrate terminal groove 35 depth be respectively less than the thickness of semiconductor substrate 58, substrate cellular ditch
Slot 36, substrate terminal groove 35 are extended downwardly from the front vertical of semiconductor substrate 58.
Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain covering 36 inner wall of substrate cellular groove
Cellular insulating oxide 60 and cover 35 inner wall of substrate terminal groove terminating insulation oxide layer 37；There is cellular exhausted in growth
Substrate cellular conductive polycrystalline silicon 59 is filled in the substrate cellular groove 36 of edge oxide layer 60, meanwhile, there is terminating insulation oxygen in growth
Change and fills substrate terminal conductive polycrystalline silicon 38 in the substrate terminal groove 35 of layer 37；
Specifically, cellular insulating oxide 60 and terminating insulation oxide layer 37 are prepared by thermal oxidation technology, member
Born of the same parents' insulating oxide 60 covers the side wall and bottom wall of substrate cellular groove 36, and terminating insulation oxide layer 37 covers substrate terminal groove
35 side wall and bottom wall, cellular insulating oxide 60, terminating insulation oxide layer 37 are generally silicon dioxide layer.Substrate cellular is conductive
Polysilicon 59 is filled in substrate cellular groove 36, and substrate cellular conductive polycrystalline silicon 59 passes through cellular insulating oxide 60 and half
Conductor substrate 58 is dielectrically separated from, and substrate terminal conductive polycrystalline silicon 38 is insulated by terminating insulation oxide layer 37 and semiconductor substrate 58
Isolation, as shown in figure 12.When it is implemented, needing before carrying out thermal oxidation technology by the lining on 58 front of semiconductor substrate
The first photoresist layer of bottom 33 removes, and the specific technical process for removing the first photoresist layer of substrate 33 is ripe for those skilled in the art
Know.Furthermore, it is possible to cellular insulating oxide 60 be prepared using the common thermal oxidation technology of the art and terminal is exhausted
Edge oxide layer 37, it is the art that substrate cellular conductive polycrystalline silicon 59, which is filled in technical process in substrate cellular groove 36 etc.,
Known to personnel, details are not described herein again.
Step 3, the injection and propulsion that p type impurity ion is carried out on the front of above-mentioned semiconductor substrate 58, to obtain cross
The area PXing Ti 39 of 58 internal upper part of semiconductor substrate is worn, the area PXing Ti 39 is located at the top of substrate trenches slot bottom；
Specifically, the injection and propulsion of p type impurity ion can be carried out using existing common process conditions, generally,
It also needs to carry out activation step after carrying out ion implanting, when being activated, the temperature of high annealing is generally 800 DEG C or more, tool
The condition of temperature, which can according to need, to be selected, and specially known to those skilled in the art, details are not described herein again.This
Outside, the type of p type impurity ion, which can according to need, is selected, and details are not described herein again.The obtained area PXing Ti 39 is covered with half
The top in semiconductor substrate 58 is crossed in top in conductor substrate 58, the area JiPXing Ti 39, and the area PXing Ti 39 is located at semiconductor lining
In the corresponding active area in bottom 58 and termination environment.Positive corresponding, the p-type of the upper surface in the area PXing Ti 39 and semiconductor substrate 58
Body area 39 is located at the top of substrate trenches slot bottom, as shown in figure 14.
Step 4, in the front surface coated photoresist layer of above-mentioned semiconductor substrate 58, applied for 41 pairs using the second mask of substrate
The photoresist layer covered carries out photoetching, to obtain the second photoresist layer of substrate 40 being covered on 58 termination environment of semiconductor substrate；
Specifically, using the common technological means of the art above-mentioned semiconductor substrate 58 front surface coated photoresist
Layer, the front of semiconductor substrate 58 can be covered using photoresist layer.Light is carried out to photoresist layer using the second mask of substrate 41
It carves, the photoresist layer on removal covering 58 active area of semiconductor substrate, so as to obtain being covered in the terminal of semiconductor substrate 58
The second photoresist layer of substrate 40 in area can carry out the termination environment of semiconductor substrate 58 using the second photoresist layer of substrate 40
It blocks, the active area of semiconductor substrate 58 is in unobstructed exposing state, as shown in figure 15.
Step 5, using the second photoresist layer of substrate 40 to above-mentioned semiconductor substrate 58 carry out N-type impurity ion, P impurity from
The injection of son, and the second photoresist layer of substrate 40 is removed after the implantation, the active area positioned at semiconductor substrate 58 is obtained after annealing
The interior source dopant region substrate N+ 46 and substrate p-type base area 42, substrate p-type base area 42 are located at 36 slot bottom of substrate cellular groove
Top, the source dopant region substrate N+ 46 is located at the top of substrate p-type base area 42, the source dopant region the substrate N+ 46, substrate p-type base area
42 contact with the lateral wall of respective substrate cellular groove 36；
Specifically, N-type impurity ion, p type impurity ion implanting sequence can according to need and selected, it can first
N-type impurity ion implanting is carried out, then in the injection for carrying out p type impurity ion, or first carries out p type impurity ion implanting, then
N-type impurity ion implanting is carried out, when specific injection is sequentially different, N-type impurity ion implanting, p type impurity ion implanting are corresponding
Process conditions are different, and specially known to those skilled in the art, details are not described herein again.It is logical in the embodiment of the present invention
The window for crossing the second photoresist layer of substrate 40 needs after injection in progress N-type impurity ion, p type impurity ion implanting
First the second photoresist layer of substrate 40 is removed from semiconductor substrate 58, to carry out subsequent annealing activation technology, when annealing
Temperature is generally at 800 DEG C or more, and the condition of actual temp is known to those skilled in the art, and details are not described herein again.
Below first to carry out p type impurity ion implanting, then carry out specifically for the technical process of N-type impurity ion
It is bright, specifically:
When carrying out p type impurity ion implanting, using the second photoresist layer of substrate 40 to the corresponding end of semiconductor substrate 58
Petiolarea is blocked, so that p type impurity ion can only be infused in the active area of semiconductor substrate 58, so as to be located at
Substrate p-type base area 42 in active area, i.e., by the area PXing Ti 39 of active area carry out p type impurity ion injection with push away
Into substrate p-type base area 42 can be obtained, so that the doping concentration of substrate p-type base area 42 is greater than the doping concentration in the area PXing Ti 39, that is, exist
The active area of semiconductor substrate 58 can be served as a contrast using the p type impurity and the above-mentioned area active area NeiPXing Ti 39 that obtains of injection
Bottom p-type base area 42, meanwhile, after being blocked by the second photoresist layer of substrate 40, semiconductor substrate corresponding with termination environment
58 areas NeiPXing Ti 39 remain unchanged.
Specifically, when carrying out N-type impurity ion implanting, still termination environment is carried out using the second photoresist layer of substrate 40
It blocks, so that N-type impurity ion can be only infused in active area, the specific technical process for carrying out N-type impurity ion is this
Known to technical field personnel, details are not described herein again.It, can be in the upper of substrate p-type base area 42 after carrying out N-type impurity ion implanting
The source dopant region substrate N+ 46 can be obtained, the source dopant region substrate N+ 46 and substrate p-type base area 42 are in parallelly distribute on, and substrate N+ mixes in source
The outer wall of miscellaneous area 46, substrate p-type base area 42 substrate cellular groove 36 neighbouring with correspondence contacts, the source dopant region substrate N+ 46 with
The notch of substrate cellular groove 36 is corresponding, as shown in figure 16.
Step 6, again above-mentioned semiconductor substrate 58 front carry out dielectric layer deposition, with obtain covering semiconductor substrate 58
Positive substrate dielectric layer 53；The coated substrate third photoresist layer 43 on substrate dielectric layer 53, utilizes substrate third mask
44 pairs of substrate third photoresist layers 43 carry out photoetching, to obtain the substrate third photoresist layer of Through-substrate third photoresist layer 43
Window 45；
Specifically, the second photoresist layer of substrate 40 is removed using the common technological means of the art, and is served as a contrast in removal
Dielectric layer deposition is carried out after the second photoresist layer of bottom 40, to obtain the covering positive substrate dielectric layer 53 of semiconductor substrate 58, institute
Stating substrate dielectric layer 53 can be silicon dioxide layer.After obtaining substrate dielectric layer 53, coats and obtain on substrate dielectric layer 53
Substrate third photoresist layer 43 carries out photoetching to substrate third photoresist layer 43 using substrate third mask 44, obtains substrate
Third photoresist layer window 45, the 45 Through-substrate third photoresist layer 43 of substrate third photoresist layer window, and substrate
Three photoresist layer windows 45 are located at the surface of active area, as shown in figure 17.
Step 7, using above-mentioned substrate third photoresist layer 43 and substrate third photoresist layer window 45 to substrate dielectric
Layer 53 performs etching, to obtain the media contact hole 48 of Through-substrate dielectric layer 53 and the source dopant region substrate N+ 46, substrate N+
Source dopant region 46 can form required substrate N+ source region 47 by media contact hole 48；
Specifically, using substrate third photoresist layer 43 and substrate third photoresist layer window 45 to substrate dielectric layer 53
It performs etching, obtains and the just corresponding media contact hole 48 of substrate third photoresist layer window 45, the perforation of media contact hole 48 lining
Bottom dielectric layer 53 and the source dopant region substrate N+ 46.On the section of the power semiconductor, media contact hole 48 is penetrated through
Behind the source dopant region substrate N+ 46, obtain the substrate N+ source region 47 positioned at 36 two sides of substrate cellular groove, substrate N+ source region 47 with it is right
The lateral wall of substrate cellular groove 36 that should be neighbouring contacts, as shown in figure 18.
Step 8, the above-mentioned substrate third photoresist layer 43 of removal, and the deposited metal on above-mentioned substrate dielectric layer 53, with
Substrate face metal layer is obtained, the substrate face metal layer is covered on substrate dielectric layer 53 and is filled in media contact hole 48
Interior, the substrate face metal layer being filled in media contact hole 48 connects with 42 ohm of substrate N+ source region 47 and substrate p-type base area
Touching；
Specifically, substrate third photoresist layer 43 is removed using the art common technological means, then, is used
The common technological means of the art carries out metal layer deposit, and metal layer can use common material, specifically can basis
It is selected, details are not described herein again.Substrate face metal layer is covered on substrate dielectric layer 53 and is filled in media contact
In hole 48, after substrate face metal layer is filled in media contact hole 48, substrate face metal layer can be with substrate N+ source region 47, lining
42 Ohmic contact of bottom p-type base area.
Step 9, the 4th photoresist layer 50 of coated substrate on above-mentioned substrate face metal layer, utilize the 4th mask of substrate
49 pairs of the 4th photoresist layers 50 of substrate carry out photoetching, to obtain the 4th photoresist layer of substrate of the 4th photoresist layer 50 of Through-substrate
Window 52 carves substrate face metal layer using the 4th photoresist layer 50 of substrate and the 4th photoresist layer window 52 of substrate
Erosion separates hole 62 to obtain the substrate metal of Through-substrate front metal layer, and separating hole 62 using substrate metal can be by substrate
Front metal layer separates to obtain substrate cellular front metal layer 61 and substrate terminal front metal layer 51, and the substrate cellular is just
Face metal layer 61 and substrate N+ source region 47 and substrate p-type base area 42 and Ohmic contact；
Specifically, coating obtains the 4th photoresist layer 50 of substrate on above-mentioned substrate face metal layer, utilizes substrate the 4th
Mask 49 carries out photoetching to the 4th photoresist layer 50 of substrate, obtains the 4th photoresist layer window 52 of substrate, the 4th photoetching of substrate
Glue-line window 52 is located at the top of termination environment.Utilizing the 4th photoresist layer 50 of substrate and the 4th photoresist layer window 52 of substrate
When being performed etching to substrate face metal, it can obtain being located at the substrate metal above termination environment and separate hole 62, substrate metal separates
62 Through-substrate front metal layer of hole, so as to by substrate face metal layer separate to obtain substrate cellular front metal layer 61 and
Substrate terminal front metal layer 51, substrate terminal front metal layer 51 separate hole 62 and substrate cellular front gold by substrate metal
Belong to layer 61 to be separately isolated, substrate terminal front metal layer 51 is located in termination environment, substrate cellular front metal layer 61 and substrate N+
Source region 47,42 Ohmic contact of substrate p-type base area, as shown in figure 19.
Step 10, above-mentioned the 4th photoresist layer 50 of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate element
Substrate face passivation layer 54 on born of the same parents' front metal layer 61, substrate terminal front metal layer 51, and the substrate face passivation layer
54 also fill up in substrate metal separation hole 62；
Specifically, the 4th photoresist layer 50 of substrate is removed using the art common technological means, and using this
The common technological means of technical field realizes passivation layer deposit, and the material of passivation layer can be silicon nitride, substrate face passivation layer
54 are covered on substrate cellular front metal layer 61, substrate terminal front metal layer 51, meanwhile, substrate face passivation layer 54 also fills up
Separate in hole 62 in substrate metal.
Step 11, the 5th photoresist layer 55 of coated substrate on above-mentioned substrate face passivation layer 54, are covered using substrate the 5th
Film layer 56 carries out photoetching to the 5th photoresist layer 55 of substrate, and using the 5th photoresist layer 55 of substrate after photoetching to substrate face
Passivation layer 54 performs etching, and to obtain the substrate source pad hole 57 of Through-substrate front passivation layer 54, is welded by substrate source
Disk hole 57 can make substrate cellular front metal layer 61 just corresponding with the substrate source pad hole 57 expose；
Specifically, coating obtains the 5th photoresist layer 55 of substrate on substrate face passivation layer 54, is covered using substrate the 5th
Template 56 carries out photoetching to the 5th photoresist layer 55 of substrate, then performs etching to substrate face passivation layer 54, to obtain substrate
Source pad hole 57,57 Through-substrate front passivation layer 54 of substrate source pad hole, substrate source pad hole 57 are located at active area
Top, substrate cellular front metal layer 61 corresponding with substrate source pad hole 57 can be made by substrate source pad hole 57
Expose, as shown in figure 20, consequently facilitating the source electrode of semiconductor devices is formed after substrate cellular front metal layer 61 is drawn, tool
The process that body forms source electrode is known to those skilled in the art.
Step 12, above-mentioned the 5th photoresist layer 55 of substrate of removal, and required back is carried out at the back side of semiconductor substrate 58
Face technique.
Specifically, the 5th photoresist layer 55 of substrate is removed using the common technological means of the art, completed required
Positive technique, the back process needed for then being carried out as needed at the back side of semiconductor substrate 58, not according to back process
With different power semiconductors can be obtained, MOSFET element or IGBT device, specific back process and the back side are such as obtained
Structure is known to those skilled in the art, and details are not described herein again.
As shown in the above description, substrate terminal groove 35 is set in the termination environment of semiconductor substrate 58, and in substrate terminal
Setting terminating insulation oxide layer 37 and substrate terminal conductive polycrystalline silicon 38 in groove 35 carry out in the front of semiconductor substrate 58
P type impurity ion implanting can obtain the area PXing Ti 39, needed for the area PXing Ti 39 of termination environment and substrate terminal groove 35 cooperatively form
Terminal plot structure, and obtain not needing mask when the area 39 PXing Ti, compared with the prior art, so that groove type power is partly led
Body device can effectively reduce the preparation cost of power semiconductor less with one piece of mask when prepared by Facad structure.
Using the second photoresist layer of substrate 40 N-type impurity ion implanting, p-type can be carried out to the active area of semiconductor substrate 58
Foreign ion can obtain the source dopant region substrate N+ 46 and substrate P after removal the second photoresist layer of substrate 40 and annealing activation
Type base area 42 can be reduced using mask in the case where guaranteeing substrate p-type 42 doping concentration of base area, further reduce the cost.
Using the substrate p-type base area 42 in active area, it is able to achieve and the doping concentration of p-type in active area is adjusted, ensure that made
It is standby to obtain the breakdown characteristics of power semiconductor termination environment and the on state characteristic of active area, entire technical process and existing work
Skill is compatible, securely and reliably.
In the embodiment of the present invention, the p-type doping concentration in active area should be high, to prevent base area under high pressure conditions from wearing
Logical, when the concentration that p-type is adulterated in active area is lower, the p-type base area 42 under high pressure in active area will be completely depleted, and electric field is just
It can be extended to the substrate cellular front metal layer 61 being filled into media contact hole 48 or N+ source region 47, so that break-through occur.
When by the way that substrate p-type base area 42 being prepared in active area, the pressure-resistant needs of active area are able to satisfy, that is, ensure that prepared obtain
To the breakdown characteristics of power semiconductor termination environment and the on state characteristic of active area.The tool of p-type doping concentration in active area
Body situation is known to those skilled in the art, herein not to the process and mode of p-type doping concentration adjusting in active area
It repeats again.
Claims (5)
1. a kind of preparation method of the trench-type power semiconductor device of low cost, characterized in that the preparation method includes such as
Lower step:
Step 1 provides the semiconductor substrate with the first conduction type, and carries out etching groove to the semiconductor substrate, with
Required substrate trenches are obtained, the substrate trenches include the lining positioned at the substrate cellular groove of active area and positioned at termination environment
Bottom terminal trenches；
Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain the cellular of covering substrate cellular trench wall
Insulating oxide and the terminating insulation oxide layer for covering substrate terminal trench wall；There is the lining of cellular insulating oxide in growth
Substrate cellular conductive polycrystalline silicon is filled in the cellular groove of bottom, meanwhile, there is the substrate terminal groove of terminating insulation oxide layer in growth
Interior filling substrate terminal conductive polycrystalline silicon；
Step 3, the injection and propulsion that the second conductive type impurity ion is carried out on the front of above-mentioned semiconductor substrate, to obtain
The second conductivity type body region of semiconductor substrate internal upper part is crossed, second conductivity type body region is located at substrate trenches slot bottom
Top；
Step 4, the front surface coated photoresist layer in above-mentioned semiconductor substrate, using the second mask of substrate to coated photoetching
Glue-line carries out photoetching, to obtain the second photoresist layer of substrate being covered in semiconductor substrate terminal area；
Step 5 leads the first conductive type impurity ion of above-mentioned semiconductor substrate progress, second using the second photoresist layer of substrate
The injection of electric type dopant ion, and the second photoresist layer of substrate is removed after the implantation, it obtains being located at semiconductor substrate after annealing
Active area in the second conduction type base region of substrate the first conduction type source dopant region and substrate, the substrate second is conductive
Type base area is located at the top of substrate cellular groove slot bottom, and substrate the first conduction type source dopant region is located at the second conductive-type of substrate
Above type base area, first conduction type of substrate source dopant region, the second conduction type base region of substrate with respective substrate cellular
The lateral wall of groove contacts；
Step 6 carries out dielectric layer deposition in the front of above-mentioned semiconductor substrate, to obtain the covering positive substrate of semiconductor substrate
Dielectric layer；The coated substrate third photoresist layer on substrate dielectric layer, using substrate third mask to substrate third photoresist
Layer carries out photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer；
Step 7 carves substrate dielectric layer using above-mentioned substrate third photoresist layer and substrate third photoresist layer window
Erosion, to obtain the media contact hole of Through-substrate dielectric layer and the first conduction type of substrate source dopant region, substrate first is conductive
Type source dopant region can form required substrate the first conduction type source region by media contact hole；
Step 8, the above-mentioned substrate third photoresist layer of removal, and the deposited metal on above-mentioned substrate dielectric layer, to obtain substrate
Front metal layer, the substrate face metal layer are covered on substrate dielectric layer and are filled in media contact hole, are filled in Jie
Substrate face metal layer and substrate the first conduction type source region and substrate the second conduction type base region ohm in matter contact hole
Contact；
Step 9, the 4th photoresist layer of coated substrate on above-mentioned substrate face metal layer, using the 4th mask of substrate to substrate
4th photoresist layer carries out photoetching and utilizes lining to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate
The 4th photoresist layer of bottom and the 4th photoresist layer window of substrate perform etching substrate face metal layer, to obtain Through-substrate
The substrate metal of front metal layer separates hole, and can separate substrate face metal layer to obtain substrate using substrate metal separation hole
Cellular front metal layer and substrate terminal front metal layer, the substrate cellular front metal layer and the first conduction type of substrate
Source region and substrate the second conduction type base region Ohmic contact；
Step 10, above-mentioned the 4th photoresist layer of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate cellular front
Substrate face passivation layer on metal layer, substrate terminal front metal layer, and the substrate face passivation layer is also filled up in substrate
In metal separation hole；
Step 11, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, using the 5th mask layer of substrate to lining
The 5th photoresist layer of bottom carries out photoetching, and is carved using the 5th photoresist layer of substrate after photoetching to substrate face passivation layer
Erosion, to obtain the substrate source pad hole of Through-substrate front passivation layer, can be made and the lining by substrate source pad hole
The just corresponding substrate cellular front metal layer in bottom source pad hole exposes；
Step 12, above-mentioned the 5th photoresist layer of substrate of removal, and required back process is carried out at the back side of semiconductor substrate.
2. the preparation method of the trench-type power semiconductor device of low cost according to claim 1, it is characterized in that: step
In 1, in the first photoresist layer of front surface coated substrate of the semiconductor substrate, using the first mask of substrate to the first light of substrate
Photoresist layer carries out photoetching and utilizes substrate first to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate
After photoresist layer and substrate the first photoresist layer window etch the front of semiconductor substrate, required substrate ditch can be obtained
Slot.
3. the preparation method of the trench-type power semiconductor device of low cost according to claim 1, it is characterized in that: described
The material of semiconductor substrate includes silicon.
4. the preparation method of the trench-type power semiconductor device of low cost according to claim 1, it is characterized in that: step
In 2, cellular insulating oxide and terminating insulation oxide layer are same processing step layer, cellular insulating oxide, terminating insulation
Oxide layer is silicon dioxide layer.
5. the preparation method of the trench-type power semiconductor device of low cost according to claim 1, it is characterized in that: described
The doping concentration of the second conduction type base region of substrate is greater than the doping concentration of the second conductivity type body region.
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