CN110071043A - A kind of preparation method of power semiconductor - Google Patents
A kind of preparation method of power semiconductor Download PDFInfo
- Publication number
- CN110071043A CN110071043A CN201910335673.5A CN201910335673A CN110071043A CN 110071043 A CN110071043 A CN 110071043A CN 201910335673 A CN201910335673 A CN 201910335673A CN 110071043 A CN110071043 A CN 110071043A
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- photoresist layer
- semiconductor
- cellular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 708
- 230000001413 cellular effect Effects 0.000 claims abstract description 81
- 230000004888 barrier function Effects 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000008569 process Effects 0.000 claims abstract description 20
- 210000000746 body region Anatomy 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 186
- 229910052751 metal Inorganic materials 0.000 claims description 96
- 239000002184 metal Substances 0.000 claims description 96
- 239000000463 material Substances 0.000 claims description 33
- 238000001259 photo etching Methods 0.000 claims description 33
- 238000002161 passivation Methods 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 239000002019 doping agent Substances 0.000 claims description 24
- 238000009413 insulation Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- 230000003628 erosive effect Effects 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 3
- 239000003292 glue Substances 0.000 claims 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- -1 after high annealing Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to a kind of preparation methods of power semiconductor, second conductivity type body region of its termination environment and substrate terminal groove cooperatively form required terminal plot structure, and it obtains not needing mask when the second conductivity type body region, compared with the prior art, trench-type power semiconductor device is enabled, less with one piece of mask, to effectively reduce the preparation cost of power semiconductor in Facad structure preparation.Since substrate barrier layer from cellular insulating oxide there is different etching selection ratios to avoid to cellular insulating oxide over etching, it is ensured that obtain the reliability of power semiconductor when removing substrate barrier layer.There are the second conduction type base regions of substrate in active area, ensure that the on state characteristic of the prepared breakdown characteristics for obtaining power semiconductor termination environment and active area, entire technical process is compatible with prior art, securely and reliably.
Description
Technical field
The present invention relates to a kind of preparation method, especially a kind of preparation method of power semiconductor belongs to power half
The technical field of conductor device preparation process.
Background technique
Currently, power semiconductor develops rapidly, on the one hand, the technology of IGBT and VDMOS is constantly reformed, to realize
Excellent performance；On the other hand, low cost also becomes pursuing a goal for power semiconductor development.Power semiconductor processing charges
In, the cost of mask plate and corresponding photoetching process are often main, therefore reduce mask plate quantity as reduction device
The key of cost.In most of the cases, the relationship often compromised between high performance device and low cost, unless there is new device
Part, process etc..
It is the step of preparation process of existing trench-type power semiconductor device Facad structure, specifically as shown in Fig. 1~Figure 11
Ground,
As shown in Figure 1, providing the semiconductor substrate 1 of N-type, and the first light of coated substrate on the front of semiconductor substrate 1
Photoresist layer 2 carries out photoetching to the first photoresist layer of substrate 2 using the first mask of substrate 3, to obtain the first photoetching of through substrate
The first photoresist layer of substrate window 4 of glue-line 2.
As shown in Fig. 2, using the first photoresist layer of substrate 2 and the first photoresist layer of substrate window 4 to semiconductor substrate 1
Front injected, to obtain the end ring 5 positioned at termination environment, the substrate of the end ring 5 and the first photoresist layer of substrate 2
First photoresist layer window 4 is corresponding.
As shown in figure 3, removal the first photoresist layer of aforesaid substrate 2, and in the front setting field oxygen of above-mentioned semiconductor substrate 1
Change layer 7, the second photoresist layer of substrate 8 being covered on the field oxide 7, using the second mask of substrate 6 to substrate second
Photoresist layer 8 carries out photoetching, and using the second photoresist layer of substrate 8 after photoetching to field oxide 7 corresponding with active area into
Row etching, so as to obtain the field oxide 7 being located on termination environment；
As shown in figure 4, removal the second photoresist layer of aforesaid substrate 8, and in the active area of above-mentioned semiconductor substrate 1 and field
Coated substrate third photoresist layer 9 in oxide layer 7 carries out light to substrate third photoresist layer 9 using substrate third mask 10
It carves, to obtain the substrate third photoresist layer window 12 of through substrate third photoresist layer 9；Utilize substrate third photoresist layer 9
And substrate third photoresist layer window 12 performs etching the semiconductor substrate 1 of active area, with what is be located in active area
Active area groove 11.
As shown in figure 5, removal aforesaid substrate third photoresist layer 9, the growth insulation grid oxygen in above-mentioned active area groove 11
Change layer 13, and fills groove conductive polycrystalline silicon 14 in the active area groove 11 that growth has insulation gate oxide 13, and etch away
Extra polysilicon.
As shown in fig. 6, carrying out the injection and propulsion of P-type ion in the top of above-mentioned semiconductor substrate 1, have to obtain being located at
Substrate P type base area 15 in source region, meanwhile, P-type ion can be stopped to be placed to end using the field oxide 7 on semiconductor substrate 1
Petiolarea, substrate P type base area 15 are located at the top of 11 slot bottom of active area groove.
As shown in fig. 7, carrying out the merging and propulsion of N-type ion in the top of above-mentioned semiconductor substrate 1, have to obtain being located at
Substrate N+ active layer 16 in source region, the substrate N+ active layer 16 are located at the top of substrate P type base area 15, utilize field oxide
7 can stop N-type ion to be injected into terminal area.
As shown in figure 8, the dielectric layer deposition on the front of above-mentioned semiconductor substrate 1, the dielectric layer are covered on substrate N+
On active layer 16 and field oxide 7, to obtain substrate medium layer 17, the substrate medium layer 17 covers active area groove 11
Notch；The 4th photoresist layer 18 of coated substrate on substrate medium layer 17, using the 4th mask 19 of substrate to the 4th light of substrate
Photoresist layer 18 carries out photoetching, to obtain the 4th photoresist layer window 20 of substrate of the 4th photoresist layer 18 of through substrate, the base
The 4th photoresist layer window 20 of plate is located at the top of active area.
As shown in figure 9, using the 4th photoresist layer 18 of substrate and the 4th photoresist layer window 20 of substrate to substrate media
Layer 17, substrate N+ active layer 16 perform etching, to obtain substrate contact hole 24 corresponding with the 4th photoresist layer window 20 of substrate,
The 24 through substrate dielectric layer 17 of substrate contact hole, and substrate N+ source region 23 is obtained in the two sides of active area groove 11.
As shown in Figure 10, the 4th photoresist layer 18 of aforesaid substrate is removed, and carries out metal shallow lake in the front of semiconductor substrate 1
Product, to obtain front metal layer, the front metal layer is covered on substrate medium layer 17 and is filled in substrate contact hole 24.
The 5th photoresist layer 26 of coated substrate on front metal layer, and using the 5th mask 27 of substrate to substrate the 5th
Photoresist layer 26 carries out photoetching, described to obtain the 5th photoresist layer window 28 of substrate of the 5th photoresist layer 26 of through substrate
The 5th photoresist layer window 28 of substrate is located at the top of termination environment.Utilize the 5th photoresist layer 26 of substrate and the 5th photoetching of substrate
Glue-line window 28 performs etching substrate front side metal layer, separates hole 22 to obtain substrate metal, front metal layer passes through substrate
Metal separation hole 22 forms substrate terminal front metal 25 and substrate cellular front metal 21 after separating.
As shown in figure 11, it is passivated layer deposit in the positive top of above-mentioned semiconductor substrate 1, it is blunt to obtain substrate front side
Change layer 29, the substrate front side passivation layer 29 is covered on substrate terminal front metal layer 25 and substrate cellular front metal layer 21
On, and substrate front side passivation layer 29 is filled in substrate metal and separates in hole 22.
The 6th photoresist layer 30 of coated substrate on substrate front side passivation layer 29, and using the 6th mask 31 of substrate to base
The 6th photoresist layer 30 of plate carries out photoetching, and using the 6th photoresist layer 30 of substrate after photoetching to substrate front side passivation layer 29 into
Capable etching can be incited somebody to action with obtaining the substrate source pad hole 32 of through substrate front passivation layer 29 by substrate source pad hole 32
Substrate cellular front metal layer 21 exposes.
After removing the 6th photoresist layer 30 of substrate, the procedure of processing of source pad can be carried out；In addition, in semiconductor substrate
1 back side also needs to carry out back process, according to the available required MOSFET element of difference or IGBT device of back process
Part, back process can use existing common processing step, no longer superfluous herein specially known to those skilled in the art
It states.
To sum up, at least need to provide six masks when carrying out positive technique for MOSFET element or IGBT device
Version, with using the corresponding lithographic process steps of corresponding mask progress so that the MOSFET element that is prepared or
The preparation cost of IGBT device is higher.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of preparation side of power semiconductor is provided
Method, can be compatible with prior art, reduces the preparation cost of power semiconductor, securely and reliably.
According to technical solution provided by the invention, a kind of preparation method of power semiconductor, the preparation method packet
Include following steps:
Step 1 provides the semiconductor substrate with the first conduction type, and carries out groove quarter to the semiconductor substrate
Erosion, to obtain required substrate trenches, the substrate trenches include positioned at the substrate cellular groove of active area and positioned at terminal
The substrate terminal groove in area；
Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain covering substrate cellular trench wall
Cellular insulating oxide and the terminating insulation oxide layer for covering substrate terminal trench wall；There is cellular insulating oxide in growth
Substrate cellular groove in fill substrate cellular conductive polycrystalline silicon, meanwhile, have the substrate terminal of terminating insulation oxide layer in growth
Substrate terminal conductive polycrystalline silicon is filled in groove；
Step 3, the injection and propulsion that the second conductive type impurity ion is carried out on the front of above-mentioned semiconductor substrate, with
Obtain crossing the second conductivity type body region of semiconductor substrate internal upper part, second conductivity type body region is located at substrate trenches slot
The top at bottom；
Step 4, the deposition preventing material layer on the front of above-mentioned semiconductor substrate, and coated on the barrier material layer
Photoresist carries out photoetching to the photoresist on barrier material layer using the second mask of substrate, to obtain being located at semiconductor substrate
The second photoresist layer of substrate above termination environment, performs etching barrier material layer using the second photoresist layer of substrate, to obtain
Substrate barrier layer immediately below the second photoresist layer of substrate；
Step 5 blocks semiconductor substrate terminal area using the second photoresist layer of substrate and substrate barrier floor, half-and-half
The active area of conductor substrate carries out the injection of the second conductive type impurity ion, removes the second photoresist of substrate after the completion of injection
Layer, after high annealing, substrate the second conduction type doped region can be obtained in the active area of semiconductor substrate；
Step 6 carries out the first conductive type impurity ion using active area of the substrate barrier layer to above-mentioned semiconductor substrate
Injection, after high annealing, substrate the first conduction type source dopant region and lining can be obtained in the active area of semiconductor substrate
The second conduction type base region of bottom, substrate the first conduction type source dopant region are located at the upper of the second conduction type base region of substrate
Side, the first conduction type of substrate source dopant region, the second conduction type base region of substrate are contacted with the outer wall of respective substrate cellular groove；
Step 7 carries out dielectric layer deposition on a semiconductor substrate, to obtain the covering positive substrate dielectric of semiconductor substrate
Layer, coating obtains substrate third photoresist layer on substrate dielectric layer, using substrate third mask to substrate third photoresist
Layer carries out photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer, the substrate third photoetching
Glue-line window is located at the top of semiconductor substrate active area；
Step 8 carves substrate dielectric layer using substrate third photoresist layer and substrate third photoresist layer window
Erosion, to obtain the media contact hole of Through-substrate dielectric layer and the first conduction type of substrate source dopant region, substrate first is conductive
Type source dopant region can form required substrate the first conduction type source region by media contact hole；
Step 9, the above-mentioned substrate third photoresist layer of removal, and the deposited metal on above-mentioned substrate dielectric layer, to obtain
Substrate face metal layer, the substrate face metal layer are covered on substrate dielectric layer and are filled in media contact hole, filling
In substrate face metal layer and the second conduction type base region of substrate the first conduction type source region and substrate in media contact hole
And Ohmic contact；
Step 10, the 4th photoresist layer of coated substrate on above-mentioned substrate face metal layer, utilize the 4th mask of substrate
Photoetching is carried out to the 4th photoresist layer of substrate, to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate,
Substrate face metal layer is performed etching using the 4th photoresist layer of substrate and the 4th photoresist layer window of substrate, to be passed through
The substrate metal of logical substrate face metal layer separates hole, and can be separated substrate face metal layer using substrate metal separation hole
To substrate cellular front metal layer and substrate terminal front metal layer, the substrate cellular front metal layer is led with substrate first
Electric type source region and substrate the second conduction type base region Ohmic contact；
Step 11, above-mentioned the 4th photoresist layer of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate cellular
Substrate face passivation layer on front metal layer, substrate terminal front metal layer, and the substrate face passivation layer also fill up in
Substrate metal separates in hole；
Step 12, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, utilize the 5th mask layer of substrate
Photoetching is carried out to the 5th photoresist layer of substrate, and substrate face passivation layer is carried out using the 5th photoresist layer of substrate after photoetching
Etching, to obtain the substrate source pad hole of Through-substrate front passivation layer, by substrate source pad hole can make with it is described
The just corresponding substrate cellular front metal layer of substrate source pad hole exposes；
Step 13, above-mentioned the 5th photoresist layer of substrate of removal, and required back side work is carried out at the back side of semiconductor substrate
Skill.
In step 1, in the first photoresist layer of front surface coated substrate of the semiconductor substrate, the first mask of substrate is utilized
Photoetching is carried out to the first photoresist layer of substrate, to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate,
After etching using the first photoresist layer of substrate and substrate the first photoresist layer window to the front of semiconductor substrate, institute can be obtained
The substrate trenches needed.
The substrate barrier layer includes polysilicon layer, silicon dioxide layer or silicon nitride layer.
The material of the semiconductor substrate includes silicon.
In step 2, cellular insulating oxide and terminating insulation oxide layer are same processing step layer, cellular insulating oxide
Layer, terminating insulation oxide layer are silicon dioxide layer.
The doping concentration of second conduction type base region of substrate is greater than the doping concentration of the second conductivity type body region.
The substrate dielectric layer is silicon dioxide layer, when substrate barrier layer is polysilicon layer, before carrying out dielectric layer deposition,
It needs to remove substrate barrier layer from semiconductor substrate.
In " first conduction type " and " the second conduction type " the two, N-type power semiconductor, first is led
Electric type refers to N-type, and the second conduction type is p-type；For p-type power semiconductor, the first conduction type and the second conductive-type
The type and N-type power semiconductor of type meaning are exactly the opposite.
Advantages of the present invention: substrate terminal groove is set in the termination environment of semiconductor substrate, and in substrate terminal groove
Terminating insulation oxide layer and substrate terminal conductive polycrystalline silicon are set, and it is miscellaneous to carry out the second conduction type in the front of semiconductor substrate
Matter ion implanting, can obtain the second conductivity type body region, and the second conductivity type body region of termination environment and substrate terminal groove cooperate
Terminal plot structure needed for being formed, and obtain not needing mask when the second conductivity type body region, compared with the prior art, so that
Trench-type power semiconductor device can effectively reduce power semiconductor less with one piece of mask when prepared by Facad structure
Preparation cost.
The termination environment of semiconductor substrate is blocked using substrate barrier layer and the second photoresist layer of substrate, is served as a contrast in semiconductor
The active area at bottom injects the second conductive type impurity ion, in removal the second photoresist layer of substrate and after being activated, can obtain
Substrate the second conduction type doped region, needed for the doping concentration of substrate the second conduction type doped region and depth can be made to reach
Requirement, realize required blocking voltage requirement, compared with the prior art, do not need to further decrease into using mask
This.In subsequent technique, the second conductivity type body region energy in substrate the second conduction type doped region and active area is utilized
The second conduction type base region of substrate is obtained, it, can be half after being blocked using termination environment of the substrate barrier layer to semiconductor substrate
The active area of conductor substrate obtains the first conduction type of substrate source dopant region, and can be obtained by the first conduction type of substrate source dopant region
To substrate the first conduction type source region.Since substrate barrier layer has different etching selection ratios from cellular insulating oxide,
When removing substrate barrier layer, avoid to cellular insulating oxide over etching, it is ensured that obtain the reliability of power semiconductor.
There are the second conduction type base regions of substrate in active area, are able to achieve dense to the doping of the second conduction type in active area
Degree is adjusted, and ensure that the conducting of the prepared breakdown characteristics for obtaining power semiconductor termination environment and active area is special
Property, entire technical process is compatible with prior art, securely and reliably.
Detailed description of the invention
Fig. 1~Figure 11 is the specific step of preparation process cross-sectional view of existing power semiconductor, wherein
Fig. 1 is to obtain the cross-sectional view after substrate the first photoresist layer window.
Fig. 2 is the cross-sectional view after obtaining end ring.
Fig. 3 is the schematic diagram after performing etching to the field oxide of active area.
Fig. 4 is to obtain the cross-sectional view after active area groove.
Fig. 5 is to obtain the cross-sectional view after groove conductive polycrystalline silicon.
Fig. 6 is to obtain the cross-sectional view behind substrate P type base area.
Fig. 7 is to obtain the cross-sectional view after substrate N+ active layer.
Fig. 8 is to obtain the cross-sectional view after the 4th photoresist layer window of substrate.
Fig. 9 is to obtain the cross-sectional view after substrate contact hole.
Figure 10 is to obtain substrate metal to separate the cross-sectional view behind hole.
Figure 11 is to obtain the cross-sectional view behind substrate source pad hole.
Figure 12~Figure 21 is specific implementation process step cross-sectional view of the present invention, wherein
Figure 12 is that the present invention obtains the cross-sectional view after substrate trenches.
Figure 13 is that the present invention obtains the cross-sectional view after substrate cellular conductive polycrystalline silicon, substrate terminal conductive polycrystalline silicon.
Figure 14 is that the present invention obtains the cross-sectional view behind p-type base area.
Figure 15 is that the present invention obtains the cross-sectional view after the second photoresist layer of substrate.
Figure 16 is that the present invention obtains the cross-sectional view after substrate P-doped zone.
Figure 17 is that the present invention obtains the cross-sectional view behind the source dopant region substrate N+.
Figure 18 is that the present invention obtains the cross-sectional view after substrate third photoresist layer window.
Figure 19 is that the present invention obtains the cross-sectional view behind media contact hole.
Figure 20 is that the present invention obtains the cross-sectional view behind substrate metal separation hole.
Figure 21 is that the present invention obtains the cross-sectional view after substrate source pad hole.
Description of symbols: 1- semiconductor substrate, the first photoresist layer of 2- substrate, the first mask of 3- substrate, 4- substrate
First photoresist layer window, 5- end ring, the second mask of 6- substrate, 7- field oxide, the second photoresist layer of 8- substrate, 9- base
Plate third photoresist layer, 10- substrate third mask, 11- active area groove, 12- substrate third photoresist layer window, 13- are exhausted
Edge gate oxide, 14- groove conductive polycrystalline silicon, 15- substrate P type base area, 16- substrate N+ active layer, 17- substrate medium layer, 18-
The 4th photoresist layer of substrate, the 4th mask of 19- substrate, the 4th photoresist layer window of 20- substrate, 21- substrate cellular front gold
Belong to, 22- substrate metal separates hole, 23- substrate N+ source region, 24- substrate contact hole, 25- substrate terminal front metal, 26- substrate
5th photoresist layer, the 5th mask of 27- substrate, the 5th photoresist layer window of 28- substrate, 29- substrate front side passivation layer, 30-
The 6th photoresist layer of substrate, the 6th mask of 31- substrate, 32- substrate source pad hole, the first photoresist layer of 33- substrate, 34-
The first mask of substrate, 35- substrate terminal groove, 36- substrate cellular groove, 37- terminating insulation oxide layer, 38- substrate terminal
Conductive polycrystalline silicon, the area 39-P Xing Ti, 40- substrate barrier floor, the second photoresist layer of 41- substrate, the second mask of 42- substrate, 43-
The source dopant region substrate N+, 44- substrate dielectric layer, 45- substrate third photoresist layer, 46- substrate third mask, 47- substrate
Three photoresist layer windows, 48- media contact hole, 49- substrate N+ source region, the 4th photoresist layer of 50- substrate, 51- substrate terminal are just
Face metal layer, the 4th mask of 52- substrate, 53- substrate cellular front metal layer, 54- substrate metal separate hole, 55- substrate the
Five photoresist layers, the 5th mask of 56- substrate, 57- substrate source pad hole, 58- semiconductor substrate, 59- substrate cellular are conductive
Polysilicon, 60- cellular insulating oxide, 61- substrate face passivation layer, the base and doped area of 62- substrate p-type and 63- substrate p-type base
Area.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
As shown in Figure 12~Figure 21: the trench-type power semiconductor device in order to which low cost is prepared, with N-type power
Semiconductor devices is in order to be illustrated specific step of preparation process of the invention, and specifically, the preparation method includes as follows
Step:
Step 1 provides the semiconductor substrate 58 of N-type, and carries out etching groove to the semiconductor substrate 58, to obtain
The substrate trenches needed, the substrate trenches include that the substrate cellular groove 36 positioned at active area and the substrate positioned at termination environment are whole
Hold groove 35；
Specifically, the material of semiconductor substrate 58 includes silicon, and certainly, semiconductor substrate 58 can also be common using other
Semiconductor material, concrete type, which can according to need, to be selected, no longer superfluous herein specially known to those skilled in the art
It states.When it is implemented, utilizing the first mask of substrate in the first photoresist layer of front surface coated substrate 33 of the semiconductor substrate 58
34 pairs of first photoresist layers of substrate 33 of version carry out photoetching, to obtain the first photoresist of substrate of the first photoresist layer of Through-substrate 33
Layer window etches the front of semiconductor substrate using the first photoresist layer of substrate 33 and substrate the first photoresist layer window
Afterwards, required substrate trenches can be obtained, as shown in figure 12.
In the embodiment of the present invention, substrate cellular groove 36 is located in the active area of semiconductor substrate 58, substrate terminal groove
35 are located in the termination environment of semiconductor substrate 58, and active area is normally at the central area of semiconductor substrate 58, and termination environment is located at
The outer ring of active area, the relative positional relationship between active area, termination environment are that those skilled in the art sets as needed,
Specially known to those skilled in the art, details are not described herein again.Substrate cellular groove 36, substrate terminal groove 35 have identical
Depth, substrate cellular groove 36, substrate terminal groove 35 depth be respectively less than the thickness of semiconductor substrate 58, substrate cellular ditch
Slot 36, substrate terminal groove 35 are extended downwardly from the front vertical of semiconductor substrate 58.
Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain covering 36 inner wall of substrate cellular groove
Cellular insulating oxide 60 and cover 35 inner wall of substrate terminal groove terminating insulation oxide layer 37；There is cellular exhausted in growth
Substrate cellular conductive polycrystalline silicon 59 is filled in the substrate cellular groove 36 of edge oxide layer 60, meanwhile, there is terminating insulation oxygen in growth
Change and fills substrate terminal conductive polycrystalline silicon 38 in the substrate terminal groove 35 of layer 37；
Specifically, cellular insulating oxide 60 and terminating insulation oxide layer 37 are prepared by thermal oxidation technology, member
Born of the same parents' insulating oxide 60 covers the side wall and bottom wall of substrate cellular groove 36, and terminating insulation oxide layer 37 covers substrate terminal groove
35 side wall and bottom wall, cellular insulating oxide 60, terminating insulation oxide layer 37 are generally silicon dioxide layer.Substrate cellular is conductive
Polysilicon 59 is filled in substrate cellular groove 36, and substrate cellular conductive polycrystalline silicon 59 passes through cellular insulating oxide 60 and half
Conductor substrate 58 is dielectrically separated from, and substrate terminal conductive polycrystalline silicon 38 is insulated by terminating insulation oxide layer 37 and semiconductor substrate 58
Isolation, as shown in figure 12.When it is implemented, needing before carrying out thermal oxidation technology by the lining on 58 front of semiconductor substrate
The first photoresist layer of bottom 33 removes, and the specific technical process for removing the first photoresist layer of substrate 33 is ripe for those skilled in the art
Know.Furthermore, it is possible to cellular insulating oxide 60 be prepared using the common thermal oxidation technology of the art and terminal is exhausted
Edge oxide layer 37, it is the art that substrate cellular conductive polycrystalline silicon 59, which is filled in technical process in substrate cellular groove 36 etc.,
Known to personnel, details are not described herein again.
Step 3, the injection and propulsion that p type impurity ion is carried out on the front of above-mentioned semiconductor substrate 58, to obtain cross
The area PXing Ti 39 of 58 internal upper part of semiconductor substrate is worn, the area PXing Ti 39 is located at the top of substrate trenches slot bottom；
Specifically, the injection and propulsion of p type impurity ion can be carried out using existing common process conditions, generally,
It also needs to carry out activation step after carrying out ion implanting, when being activated, the temperature of high annealing is generally 800 DEG C or more, tool
The condition of temperature, which can according to need, to be selected, and specially known to those skilled in the art, details are not described herein again.This
Outside, the type of p type impurity ion, which can according to need, is selected, and details are not described herein again.The obtained area PXing Ti 39 is covered with half
The top in semiconductor substrate 58 is crossed in top in conductor substrate 58, the area JiPXing Ti 39, and the area PXing Ti 39 is located at semiconductor lining
In the corresponding active area in bottom 58 and termination environment.Positive corresponding, the p-type of the upper surface in the area PXing Ti 39 and semiconductor substrate 58
Body area 39 is located at the top of substrate trenches slot bottom, as shown in figure 14.
Step 4, the deposition preventing material layer on the front of above-mentioned semiconductor substrate 58, and applied on the barrier material layer
Photoresist is covered, photoetching is carried out to the photoresist on barrier material layer using the second mask of substrate 42, to obtain being located at semiconductor
The second photoresist layer of substrate 41 above 58 termination environment of substrate, carves barrier material layer using the second photoresist layer of substrate 41
Erosion, to obtain being located at the substrate barrier layer 40 immediately below the second photoresist layer of substrate 41；
Specifically, barrier material layer includes polysilicon layer, silicon dioxide layer or silicon nitride layer, when barrier material layer is using non-
When the material of silicon dioxide layer, barrier material layer has different etching selection ratios from cellular insulating oxide 60, that is, works as blocking
When material layer uses polysilicon layer or silicon nitride layer, selected between barrier material layer and cellular insulating oxide 60 with different etchings
Select ratio, and barrier material layer be silicon dioxide layer when, etching having the same between barrier material layer and cellular insulating oxide 60
Selection ratio.
Barrier material layer can be obtained in the front deposit of semiconductor substrate 58 using the common technological means of the art,
After obtaining barrier material layer, photoresist layer is coated on the barrier material layer, using substrate the second mask 42 to photoetching
After glue-line etching, the second photoresist layer of substrate 41 can be obtained, wherein the second photoresist layer of substrate 41 is located at semiconductor substrate 58 eventually
The active area that the top of petiolarea, i.e. the second photoresist layer of substrate 41 do not cover semiconductor substrate 58.Pass through the second photoresist of substrate
After 41 pairs of barrier material of layer perform etching, substrate barrier layer 40 can be obtained, i.e. substrate barrier layer 40 is located at the second photoresist of substrate
The underface of layer 41, substrate barrier layer 40 also do not carry out covering to the active area of semiconductor substrate 58 and block, as shown in figure 15.
Step 5 is hidden using the termination environment of 40 pairs of semiconductor substrate 58 of the second photoresist layer of substrate 41 and substrate barrier layer
Gear carries out the injection of p type impurity ion to the active area of semiconductor substrate 58, removes the second photoresist layer of substrate after the completion of injection
40, after high annealing, substrate P-doped zone 62 can be obtained in the active area of semiconductor substrate 58；
Specifically, since the second photoresist layer of substrate 41 and substrate barrier layer 40 can be to the termination environments of semiconductor substrate 58
It is blocked, carries out p type impurity ion implanting so as to the active area to semiconductor substrate 58, it is specific to carry out p type impurity ion
The technical process of injection and the type of p type impurity ion are known to those skilled in the art, and details are not described herein again.It is injecting
Afterwards, it needs to remove the second photoresist layer of substrate 40 using the common technological means of the art, after removal, and carries out height again
After warm anneal processing steps, substrate P-doped zone 62 can be obtained, temperature when high annealing is generally at 800 DEG C or more, specific temperature
The case where spending is selected as needed.In the embodiment of the present invention, the doping concentration of substrate P-doped zone 62 is greater than the area PXing Ti
39 doping concentration ensures that the doping concentration of substrate P-doped zone 62 and depth reach requirement in this way, so as to
It realizes high blocking voltage, and is compared with traditional handicraft, the not additional increase mask plate of this step, as shown in figure 16.
Step 6, the note that N-type impurity ion is carried out using the active area of 40 pairs of substrate barrier layer above-mentioned semiconductor substrates 58
Enter, after high annealing, the source dopant region substrate N+ 43 and substrate p-type base area can be obtained in the active area of semiconductor substrate 58
The source dopant region 63, the substrate N+ 43 is located at the top of substrate p-type base area 62, the source dopant region substrate N+ 43, substrate p-type base area 62
It is contacted with the outer wall of respective substrate cellular groove 36；
Specifically, when being blocked using the termination environment of 40 pairs of semiconductor substrate 58 of substrate barrier layer, semiconductor can be served as a contrast
The active area at bottom 58 carries out N-type impurity ion implanting, and the specific process for carrying out N-type impurity ion implanting is those skilled in the art
Known, details are not described herein again.The temperature of high annealing is generally at 800 DEG C, after high annealing, the source substrate N+ can be activated to mix
Miscellaneous area 43.In addition, utilizing the P in above-mentioned substrate P-doped zone 62 and active area after obtaining the source dopant region substrate N+ 43
The area Xing Ti 39 can obtain substrate p-type base area 63, and substrate p-type base area 62 is located at the lower section of the source dopant region substrate N+ 43.
It as shown in the above description, can be by substrate P-doped zone 62, active area after obtaining the source dopant region substrate N+ 43
The area PXing Ti 39 obtain substrate p-type base area 63 so that the doping concentration of substrate p-type base area 63, depth reach required requirement,
Realize high blocking voltage, the principle for implementing high blocking voltage is known to those skilled in the art, and details are not described herein again.
The source dopant region substrate N+ 43, substrate p-type base area 62 are contacted with the outer wall of respective substrate cellular groove 36, as shown in figure 17.
In the embodiment of the present invention, as shown in the above description, when substrate barrier layer 40 is using polysilicon, silicon nitride and cellular is exhausted
Therefore the material of 60 different etching of edge oxide layer selection ratio when etching to form substrate barrier layer 40 to barrier material layer, can be prevented
Only to the over etching of cellular insulating oxide 60, technology controlling and process is easier, and guarantee obtains the reliability of power semiconductor.
But it when substrate barrier layer 40 is using silicon dioxide layer, by accurately being controlled etching technics, can also prevent exhausted to cellular
The over etching of edge oxide layer 60, but technology difficulty is relatively high, and specific etching technics is selected as known to those skilled in the art, this
Place repeats no more.
Step 7 simultaneously carries out dielectric layer deposition in semiconductor substrate 58, to obtain the covering positive lining of semiconductor substrate 58
Bottom dielectric layer 44, coating obtains substrate third photoresist layer 45 on substrate dielectric layer 44, right using substrate third mask 46
Substrate third photoresist layer 45 carries out photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer 45
47, the substrate third photoresist layer window 47 is located at the top of 58 active area of semiconductor substrate；
Specifically, it is able to achieve substrate barrier layer 40 using the common technological means of the art from semiconductor substrate 58
Upper removal, the specific process for removing substrate barrier layer 40 is known to those skilled in the art, and details are not described herein again.Remove substrate
Behind barrier layer 40, dielectric layer deposition is carried out in semiconductor substrate 58, is situated between with obtaining the covering positive substrate of semiconductor substrate 58
Matter layer 44, the substrate dielectric layer 44 can be silicon dioxide layer.After obtaining substrate dielectric layer 44, on substrate dielectric layer 44
Coating obtains substrate third photoresist layer 45, carries out photoetching to substrate third photoresist layer 45 using substrate third mask 46,
Obtain substrate third photoresist layer window 47, the 47 Through-substrate third photoresist layer 45 of substrate third photoresist layer window,
And substrate third photoresist layer window 47 is located at the surface of active area, as shown in figure 18.
As shown in the above description, the substrate dielectric layer 44 is generally silicon dioxide layer, and substrate barrier layer 40 is polysilicon
When layer, before carrying out dielectric layer deposition, need to remove substrate barrier layer 40 from semiconductor substrate 58.And work as substrate barrier layer
When 40 use silicon dioxide layer or silicon nitride, then when carrying out dielectric layer deposition, it may not be necessary to by substrate barrier layer 40 from partly
It is removed on conductor substrate 58.
Step 8, using substrate third photoresist layer 45 and substrate third photoresist layer window 47 to substrate dielectric layer 44
It performs etching, to obtain the media contact hole 48 of Through-substrate dielectric layer 44 and the source dopant region substrate N+ 43, substrate N+ mixes in source
Miscellaneous area 43 can form required substrate N+ source region 49 by media contact hole 48；
Specifically, using substrate third photoresist layer 45 and substrate third photoresist layer window 47 to substrate dielectric layer 44
It performs etching, obtains and the just corresponding media contact hole 48 of substrate third photoresist layer window 47, the perforation of media contact hole 48 lining
Bottom dielectric layer 44 and the source dopant region substrate N+ 43.On the section of the power semiconductor, media contact hole 48 is penetrated through
Behind the source dopant region substrate N+ 43, obtain the substrate N+ source region 49 positioned at 36 two sides of substrate cellular groove, substrate N+ source region 49 with it is right
The lateral wall of substrate cellular groove 36 that should be neighbouring contacts, as shown in figure 19.
Step 9, the above-mentioned substrate third photoresist layer 45 of removal, and the deposited metal on above-mentioned substrate dielectric layer 44, with
Substrate face metal layer is obtained, the substrate face metal layer is covered on substrate dielectric layer 44 and is filled in media contact hole 48
Interior, the substrate face metal layer being filled in media contact hole 48 connects with 63 ohm of substrate N+ source region 49 and substrate p-type base area
Touching；
Specifically, substrate third photoresist layer 45 is removed using the art common technological means, then, is used
The common technological means of the art carries out metal layer deposit, and metal layer can use common material, specifically can basis
It is selected, details are not described herein again.Substrate face metal layer is covered on substrate dielectric layer 44 and is filled in media contact
In hole 48, after substrate face metal layer is filled in media contact hole 48, substrate face metal layer can be with substrate N+ source region 49, lining
62 Ohmic contact of bottom p-type base area.
Step 10, the 4th photoresist layer 50 of coated substrate on above-mentioned substrate face metal layer, utilize the 4th mask of substrate
52 pairs of the 4th photoresist layers 50 of substrate of version carry out photoetching, to obtain the 4th photoresist of substrate of the 4th photoresist layer 50 of Through-substrate
Layer window, carves substrate face metal layer using the 4th photoresist layer 50 of substrate and the 4th photoresist layer window of substrate
Erosion separates hole 54 to obtain the substrate metal of Through-substrate front metal layer, and separating hole 54 using substrate metal can be by substrate
Front metal layer separates to obtain substrate cellular front metal layer 53 and substrate terminal front metal layer 51, and the substrate cellular is just
Face metal layer 53 and 63 Ohmic contact of substrate N+ source region 49 and substrate p-type base area；
Specifically, coating obtains the 4th photoresist layer 50 of substrate on above-mentioned substrate face metal layer, utilizes substrate the 4th
Mask 52 carries out photoetching to the 4th photoresist layer 50 of substrate, obtains the 4th photoresist layer window of substrate, the 4th photoresist of substrate
Layer window is located at the top of termination environment.In utilization the 4th photoresist layer 50 of substrate and the 4th photoresist layer window of substrate to substrate
When front metal performs etching, it can obtain being located at the substrate metal above termination environment and separate hole 54, substrate metal separates hole 54 and passes through
Logical substrate face metal layer, so as to separate substrate face metal layer to obtain substrate cellular front metal layer 53 and substrate end
Front metal layer 51 is held, substrate terminal front metal layer 51 separates hole 54 and substrate cellular front metal layer 53 by substrate metal
Separately isolation, substrate terminal front metal layer 51 is located in termination environment, substrate cellular front metal layer 53 and substrate N+ source region 49,
62 Ohmic contact of substrate p-type base area, as shown in figure 20.
Step 11, above-mentioned the 4th photoresist layer 50 of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate element
Substrate face passivation layer 61 on born of the same parents' front metal layer 53, substrate terminal front metal layer 51, and the substrate face passivation layer
61 also fill up in substrate metal separation hole 54；
Specifically, the 4th photoresist layer 50 of substrate is removed using the art common technological means, and using this
The common technological means of technical field realizes passivation layer deposit, and the material of passivation layer can be silicon nitride, substrate face passivation layer
61 are covered on substrate cellular front metal layer 53, substrate terminal front metal layer 51, meanwhile, substrate face passivation layer 61 also fills up
Separate in hole 54 in substrate metal.
Step 12, the 5th photoresist layer 55 of coated substrate on above-mentioned substrate face passivation layer 61, are covered using substrate the 5th
Film layer 56 carries out photoetching to the 5th photoresist layer 55 of substrate, and using the 5th photoresist layer 55 of substrate after photoetching to substrate face
Passivation layer 61 performs etching, and to obtain the substrate source pad hole 57 of Through-substrate front passivation layer 61, is welded by substrate source
Disk hole 57 can make substrate cellular front metal layer 53 just corresponding with the substrate source pad hole 57 expose；
Specifically, coating obtains the 5th photoresist layer 55 of substrate on substrate face passivation layer 61, is covered using substrate the 5th
Template 56 carries out photoetching to the 5th photoresist layer 55 of substrate, then performs etching to substrate face passivation layer 61, to obtain substrate
Source pad hole 57,57 Through-substrate front passivation layer 61 of substrate source pad hole, substrate source pad hole 57 are located at active area
Top, substrate cellular front metal layer 53 corresponding with substrate source pad hole 57 can be made by substrate source pad hole 57
Expose, as shown in figure 21, consequently facilitating the source electrode of semiconductor devices is formed after substrate cellular front metal layer 53 is drawn, tool
The process that body forms source electrode is known to those skilled in the art.
Step 13, above-mentioned the 5th photoresist layer 55 of substrate of removal, and required back is carried out at the back side of semiconductor substrate 58
Face technique.
Specifically, the 5th photoresist layer 55 of substrate is removed using the common technological means of the art, completed required
Positive technique, the back process needed for then being carried out as needed at the back side of semiconductor substrate 58, not according to back process
With different power semiconductors can be obtained, MOSFET element or IGBT device, specific back process and the back side are such as obtained
Structure is known to those skilled in the art, and details are not described herein again.
As shown in the above description, substrate terminal groove 35 is set in the termination environment of semiconductor substrate 58, and in substrate terminal
Setting terminating insulation oxide layer 37 and substrate terminal conductive polycrystalline silicon 38 in groove 35 carry out in the front of semiconductor substrate 58
P type impurity ion implanting can obtain the area PXing Ti 39, needed for the area PXing Ti 39 of termination environment and substrate terminal groove 35 cooperatively form
Terminal plot structure, and obtain not needing mask when the area 39 PXing Ti, compared with the prior art, so that groove type power is partly led
Body device can effectively reduce the preparation cost of power semiconductor less with one piece of mask when prepared by Facad structure.
The termination environment of semiconductor substrate 58 is blocked using substrate barrier layer 40 and the second photoresist layer of substrate 41, half
The active area injecting p-type foreign ion of conductor substrate 58 can be obtained in removal the second photoresist layer of substrate 41 and after being activated
Substrate P-doped zone 62 can make the doping concentration of substrate P-doped zone 62 and depth reach required requirement, realize institute
The blocking voltage requirement needed, compared with the prior art, does not need using mask, can further reduce the cost.In subsequent work
In skill, substrate p-type base area 63 can be obtained using substrate P-doped zone 62 and the area active area NeiPXing Ti 39, is hindered using substrate
After barrier 40 blocks the termination environment of semiconductor substrate 58, the source substrate N+ can be obtained in the active area of semiconductor substrate 58 and mixed
Miscellaneous area 43, and substrate N+ source region 49 can be obtained by the source dopant region substrate N+ 43.Due to substrate barrier layer 40 and cellular insulating oxide
Layer 60 can have different etching selection ratios, when removing substrate barrier layer 40, avoid to 60 over etching of cellular insulating oxide,
Ensure to obtain the reliability of power semiconductor.
Using, there are substrate p-type base area 63, being able to achieve and the doping concentration of p-type in active area be adjusted in active area,
It ensure that the on state characteristic of the prepared breakdown characteristics for obtaining power semiconductor termination environment and active area, entire technique mistake
Journey is compatible with prior art, securely and reliably.
In the embodiment of the present invention, the p-type doping concentration in active area should be high, to prevent base area under high pressure conditions from wearing
Logical, when the concentration that p-type is adulterated in active area is lower, the p-type base area 42 under high pressure in active area will be completely depleted, and electric field is just
It can be extended to the substrate cellular front metal layer 53 being filled in media contact hole 48 or N+ source region 47, so that break-through occur.
When by the way that substrate p-type base area 42 being prepared in active area, the pressure-resistant needs of active area are able to satisfy, that is, ensure that prepared obtain
To the breakdown characteristics of power semiconductor termination environment and the on state characteristic of active area.The tool of p-type doping concentration in active area
Body situation is known to those skilled in the art, herein not to the process and mode of p-type doping concentration adjusting in active area
It repeats again.
Claims (7)
1. a kind of preparation method of power semiconductor, characterized in that the preparation method includes the following steps:
Step 1 provides the semiconductor substrate with the first conduction type, and carries out etching groove to the semiconductor substrate, with
Required substrate trenches are obtained, the substrate trenches include the lining positioned at the substrate cellular groove of active area and positioned at termination environment
Bottom terminal trenches；
Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain the cellular of covering substrate cellular trench wall
Insulating oxide and the terminating insulation oxide layer for covering substrate terminal trench wall；There is the lining of cellular insulating oxide in growth
Substrate cellular conductive polycrystalline silicon is filled in the cellular groove of bottom, meanwhile, there is the substrate terminal groove of terminating insulation oxide layer in growth
Interior filling substrate terminal conductive polycrystalline silicon；
Step 3, the injection and propulsion that the second conductive type impurity ion is carried out on the front of above-mentioned semiconductor substrate, to obtain
The second conductivity type body region of semiconductor substrate internal upper part is crossed, second conductivity type body region is located at substrate trenches slot bottom
Top；
Step 4, the deposition preventing material layer on the front of above-mentioned semiconductor substrate, and photoetching is coated on the barrier material layer
Glue carries out photoetching to the photoresist on barrier material layer using the second mask of substrate, to obtain being located at semiconductor substrate terminal
The second photoresist layer of substrate above area, performs etching barrier material layer using the second photoresist layer of substrate, to be located at
Substrate barrier layer immediately below the second photoresist layer of substrate；
Step 5 blocks semiconductor substrate terminal area using the second photoresist layer of substrate and substrate barrier floor, to semiconductor
The active area of substrate carries out the injection of the second conductive type impurity ion, and the second photoresist layer of substrate is removed after the completion of injection, high
After temperature annealing, substrate the second conduction type doped region can be obtained in the active area of semiconductor substrate；
Step 6, the note for carrying out the first conductive type impurity ion to the active area of above-mentioned semiconductor substrate using substrate barrier layer
Enter, after high annealing, substrate the first conduction type source dopant region and substrate can be obtained in the active area of semiconductor substrate
Two conduction type base regions, substrate the first conduction type source dopant region are located at the top of the second conduction type base region of substrate, lining
Bottom the first conduction type source dopant region, the second conduction type base region of substrate are contacted with the outer wall of respective substrate cellular groove；
Step 7 carries out dielectric layer deposition on a semiconductor substrate, to obtain the covering positive substrate dielectric layer of semiconductor substrate,
On substrate dielectric layer coating obtain substrate third photoresist layer, using substrate third mask to substrate third photoresist layer into
Row photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer, the substrate third photoresist layer
Window is located at the top of semiconductor substrate active area；
Step 8 performs etching substrate dielectric layer using substrate third photoresist layer and substrate third photoresist layer window, with
Obtain the media contact hole of Through-substrate dielectric layer and the first conduction type of substrate source dopant region, the first conduction type of substrate source
Doped region can form required substrate the first conduction type source region by media contact hole；
Step 9, the above-mentioned substrate third photoresist layer of removal, and the deposited metal on above-mentioned substrate dielectric layer, to obtain substrate
Front metal layer, the substrate face metal layer are covered on substrate dielectric layer and are filled in media contact hole, are filled in Jie
Substrate face metal layer in matter contact hole and substrate the first conduction type source region and the second conduction type base region of substrate and
Ohmic contact；
Step 10, the 4th photoresist layer of coated substrate on above-mentioned substrate face metal layer, using the 4th mask of substrate to lining
The 4th photoresist layer of bottom carries out photoetching, to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate, utilizes
The 4th photoresist layer of substrate and the 4th photoresist layer window of substrate perform etching substrate face metal layer, to obtain perforation lining
The substrate metal of bottom front metal layer separates hole, and can separate substrate face metal layer using substrate metal separation hole and be served as a contrast
Bottom cellular front metal layer and substrate terminal front metal layer, the substrate cellular front metal layer and the first conductive-type of substrate
Type source region and substrate the second conduction type base region Ohmic contact；
Step 11, above-mentioned the 4th photoresist layer of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate cellular front
Substrate face passivation layer on metal layer, substrate terminal front metal layer, and the substrate face passivation layer is also filled up in substrate
In metal separation hole；
Step 12, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, using the 5th mask layer of substrate to lining
The 5th photoresist layer of bottom carries out photoetching, and is carved using the 5th photoresist layer of substrate after photoetching to substrate face passivation layer
Erosion, to obtain the substrate source pad hole of Through-substrate front passivation layer, can be made and the lining by substrate source pad hole
The just corresponding substrate cellular front metal layer in bottom source pad hole exposes；
Step 13, above-mentioned the 5th photoresist layer of substrate of removal, and required back process is carried out at the back side of semiconductor substrate.
2. the preparation method of power semiconductor according to claim 1, it is characterized in that: partly being led in step 1 described
The first photoresist layer of front surface coated substrate of body substrate carries out light to the first photoresist layer of substrate using the first mask of substrate
Carve, to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate, using the first photoresist layer of substrate and
After substrate the first photoresist layer window is to the front etching of semiconductor substrate, required substrate trenches can be obtained.
3. the preparation method of power semiconductor according to claim 1, it is characterized in that: the substrate barrier layer includes
Polysilicon layer, silicon dioxide layer or silicon nitride layer.
4. the preparation method of power semiconductor according to claim 1, it is characterized in that: the material of the semiconductor substrate
Material includes silicon.
5. the preparation method of power semiconductor according to claim 1, it is characterized in that: in step 2, cellular insulation oxygen
Change layer and terminating insulation oxide layer is same processing step layer, cellular insulating oxide, terminating insulation oxide layer are titanium dioxide
Silicon layer.
6. the preparation method of power semiconductor according to claim 1, it is characterized in that: the second conductive-type of the substrate
The doping concentration of type base area is greater than the doping concentration of the second conductivity type body region.
7. the preparation method of power semiconductor according to claim 3, it is characterized in that: the substrate dielectric layer is two
Silicon oxide layer when substrate barrier layer is polysilicon layer, before carrying out dielectric layer deposition, needs to serve as a contrast substrate barrier layer from semiconductor
It is removed on bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910335673.5A CN110071043A (en) | 2019-04-24 | 2019-04-24 | A kind of preparation method of power semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910335673.5A CN110071043A (en) | 2019-04-24 | 2019-04-24 | A kind of preparation method of power semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110071043A true CN110071043A (en) | 2019-07-30 |
Family
ID=67368784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910335673.5A Pending CN110071043A (en) | 2019-04-24 | 2019-04-24 | A kind of preparation method of power semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110071043A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110444583A (en) * | 2019-08-08 | 2019-11-12 | 南京芯长征科技有限公司 | Power semiconductor of low cost and high reliability and preparation method thereof |
| CN113380621A (en) * | 2021-04-07 | 2021-09-10 | 厦门士兰集科微电子有限公司 | Semiconductor device and method for manufacturing the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030006454A1 (en) * | 2001-07-03 | 2003-01-09 | Siliconix, Inc. | Trench MOSFET having implanted drain-drift region and process for manufacturing the same |
| CN104576720A (en) * | 2011-01-17 | 2015-04-29 | 英飞凌科技奥地利有限公司 | Power device and a reverse conducting power IGBT |
| CN104701361A (en) * | 2013-12-04 | 2015-06-10 | 株式会社东芝 | Semiconductor device |
| CN105914230A (en) * | 2016-05-06 | 2016-08-31 | 张家港凯思半导体有限公司 | Ultra-low power consumption semiconductor power device and preparation method thereof |
| US20160284838A1 (en) * | 2015-03-27 | 2016-09-29 | Freescale Semiconductor, Inc. | Trench mosfet shield poly contact |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| CN107251233A (en) * | 2015-09-16 | 2017-10-13 | 富士电机株式会社 | Semiconductor device |
-
2019
- 2019-04-24 CN CN201910335673.5A patent/CN110071043A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030006454A1 (en) * | 2001-07-03 | 2003-01-09 | Siliconix, Inc. | Trench MOSFET having implanted drain-drift region and process for manufacturing the same |
| CN104576720A (en) * | 2011-01-17 | 2015-04-29 | 英飞凌科技奥地利有限公司 | Power device and a reverse conducting power IGBT |
| CN104701361A (en) * | 2013-12-04 | 2015-06-10 | 株式会社东芝 | Semiconductor device |
| US20160284838A1 (en) * | 2015-03-27 | 2016-09-29 | Freescale Semiconductor, Inc. | Trench mosfet shield poly contact |
| CN107251233A (en) * | 2015-09-16 | 2017-10-13 | 富士电机株式会社 | Semiconductor device |
| CN105914230A (en) * | 2016-05-06 | 2016-08-31 | 张家港凯思半导体有限公司 | Ultra-low power consumption semiconductor power device and preparation method thereof |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110444583A (en) * | 2019-08-08 | 2019-11-12 | 南京芯长征科技有限公司 | Power semiconductor of low cost and high reliability and preparation method thereof |
| CN110444583B (en) * | 2019-08-08 | 2023-04-11 | 江苏芯长征微电子集团股份有限公司 | Low-cost high-reliability power semiconductor device and preparation method thereof |
| CN113380621A (en) * | 2021-04-07 | 2021-09-10 | 厦门士兰集科微电子有限公司 | Semiconductor device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101529570B (en) | Lateral trench mosfet with direct trench polysilicon contact and method of forming the same | |
| TWI446416B (en) | High density trench mosfet with single mask pre-defined gate and contact trenches | |
| EP1281200B1 (en) | Method of making a semiconductor device having a recessed insulating layer of varying thickness | |
| US20110049564A1 (en) | Integrated schottky diode in high voltage semiconductor device | |
| CN102169898B (en) | Containing buried insulating layer with through its electronic device of vertical conductive structure and method | |
| CN102097470B (en) | Semiconductor device and method for manufacturing the same | |
| CN102097378B (en) | Method for manufacturing trench metal-oxide semiconductor field effect transistor (MOSFET) | |
| US20110121386A1 (en) | Trench MOSFET with trenched floating gates as termination | |
| CN105321824B (en) | Method for manufacturing semiconductor device | |
| CN111509035B (en) | Low-cost high-performance groove type power semiconductor device and preparation method thereof | |
| CN101645457A (en) | Super-self-aligned trench-dmos structure and method | |
| US20050176192A1 (en) | Planarization method of manufacturing a superjunction device | |
| EP1733431A1 (en) | Trench semiconductor device and method of manufacturing it | |
| CN110429129B (en) | High-voltage groove type power semiconductor device and preparation method | |
| CN103022094A (en) | Semiconductor device and method for manufacturing same | |
| CN101258588A (en) | Method of manufacturing a semiconductor power device | |
| CN103295907A (en) | Semiconductor device and method of manufacture thereof | |
| CN104979213B (en) | Form the technique with the electronic device of the terminator including insulation layer | |
| CN110071043A (en) | A kind of preparation method of power semiconductor | |
| CN108028203A (en) | Vertical JFET and its manufacture method | |
| CN105489649B (en) | Improve the method for termination environment low breakdown voltage in groove-type power device | |
| JP2005191241A (en) | Semiconductor device and method for manufacturing the same | |
| CN102254826A (en) | Bi-grid oxide groove mosfet and three or four mask process with passage stop groove | |
| CN106847700A (en) | A kind of high pressure VDMOS structures and preparation method thereof | |
| CN110047757A (en) | The preparation method of the trench-type power semiconductor device of low cost |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200421 Address after: 550081 Guizhou city of Guiyang Province Lake District Forest City West Morgan center A block 10 layer A-10-003 Applicant after: GUIZHOU MARCHING POWER TECHNOLOGY CO.,LTD. Applicant after: Nanjing Xinchangzheng Technology Co.,Ltd. Address before: 550081 No. 11, Building A, Morgan Center, Lincheng West Road, Guanshan Lake District, Guiyang City, Guizhou Province Applicant before: GUIZHOU MARCHING POWER TECHNOLOGY Co.,Ltd. |
|
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190730 |