CN110444583A - Power semiconductor of low cost and high reliability and preparation method thereof - Google Patents
Power semiconductor of low cost and high reliability and preparation method thereof Download PDFInfo
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- CN110444583A CN110444583A CN201910729788.2A CN201910729788A CN110444583A CN 110444583 A CN110444583 A CN 110444583A CN 201910729788 A CN201910729788 A CN 201910729788A CN 110444583 A CN110444583 A CN 110444583A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 176
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 949
- 230000001413 cellular effect Effects 0.000 claims abstract description 304
- 239000002184 metal Substances 0.000 claims abstract description 120
- 229910052751 metal Inorganic materials 0.000 claims abstract description 120
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 94
- 210000000746 body region Anatomy 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 195
- 238000002161 passivation Methods 0.000 claims description 45
- 238000002347 injection Methods 0.000 claims description 40
- 239000007924 injection Substances 0.000 claims description 40
- 238000009413 insulation Methods 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 35
- 238000001259 photo etching Methods 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 7
- 230000003628 erosive effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims 2
- 239000002019 doping agent Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 238000000926 separation method Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 241000209140 Triticum Species 0.000 description 1
- 235000021307 Triticum Nutrition 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 235000013312 flour Nutrition 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The present invention relates to power semiconductors of a kind of low cost and high reliability and preparation method thereof, and the cellular in active area uses groove structure；It include substrate cellular groove and cellular edge groove in active area, the width of cellular edge groove is greater than the width of substrate cellular groove；At cellular edge, cellular edge groove the second conduction type doped region is arranged in the underface of groove slot bottom, and at cellular edge, the second conductivity type body region of substrate is arranged in the two sides of groove；Edge groove conductive polycrystalline silicon and substrate insulating medium layer are filled in cellular edge groove, substrate source metal layer is supported on substrate insulating medium layer, the second conductivity type body region of substrate Ohmic contact of substrate source metal layer and the second conduction type base region of substrate, substrate the first conduction type source region and cellular edge groove two sides.The present invention can improve the breakdown voltage of terminal area, reduce manufacturing cost, improve the UIS ability of power semiconductor, compatible with prior art, securely and reliably.
Description
Technical field
The present invention relates to a kind of power semiconductor and preparation method thereof, especially a kind of function of low cost and high reliability
Rate semiconductor devices and preparation method thereof belongs to the technical field of power semiconductor.
Background technique
Currently, power semiconductor develops rapidly, on the one hand, the technology of IGBT and VDMOS is constantly reformed, to realize
Excellent performance；On the other hand, low cost also becomes pursuing a goal for power semiconductor development.Power semiconductor processing charges
In, the cost of mask plate and corresponding photoetching process are often main, therefore reduce mask plate quantity as reduction device
The key of cost.In most of the cases, the relationship often compromised between high performance device and low cost, unless there is new device
Part, process etc..
It is the step of preparation process of existing trench-type power semiconductor device Facad structure, specifically as shown in Fig. 1~Figure 11
Ground,
As shown in Figure 1, providing the semiconductor substrate 1 of N-type, and the first light of coated substrate on the front of semiconductor substrate 1
Photoresist layer 2 carries out photoetching to the first photoresist layer of substrate 2 using the first mask of substrate 3, to obtain the first photoetching of through substrate
The first photoresist layer of substrate window 4 of glue-line 2.
As shown in Fig. 2, using the first photoresist layer of substrate 2 and the first photoresist layer of substrate window 4 to semiconductor substrate 1
Front injected, to obtain the end ring 5 positioned at termination environment, the substrate of the end ring 5 and the first photoresist layer of substrate 2
First photoresist layer window 4 is corresponding.
As shown in figure 3, removal the first photoresist layer of aforesaid substrate 2, and in the front setting field oxygen of above-mentioned semiconductor substrate 1
Change layer 7, the second photoresist layer of substrate 8 being covered on the field oxide 7, using the second mask of substrate 6 to substrate second
Photoresist layer 8 carries out photoetching, and using the second photoresist layer of substrate 8 after photoetching to field oxide 7 corresponding with active area into
Row etching, so as to obtain the field oxide 7 being located on termination environment；
As shown in figure 4, removal the second photoresist layer of aforesaid substrate 8, and in the active area of above-mentioned semiconductor substrate 1 and field
Coated substrate third photoresist layer 9 in oxide layer 7 carries out light to substrate third photoresist layer 9 using substrate third mask 10
It carves, to obtain the substrate third photoresist layer window 12 of through substrate third photoresist layer 9；Utilize substrate third photoresist layer 9
And substrate third photoresist layer window 12 performs etching the semiconductor substrate 1 of active area, with what is be located in active area
Active area groove 11.
As shown in figure 5, removal aforesaid substrate third photoresist layer 9, the growth insulation grid oxygen in above-mentioned active area groove 11
Change layer 13, and fills groove conductive polycrystalline silicon 14 in the active area groove 11 that growth has insulation gate oxide 13, and etch away
Extra polysilicon.
As shown in fig. 6, carrying out the injection and propulsion of P-type ion in the top of above-mentioned semiconductor substrate 1, have to obtain being located at
Substrate P type base area 15 in source region, meanwhile, P-type ion can be stopped to be placed to end using the field oxide 7 on semiconductor substrate 1
Petiolarea, substrate P type base area 15 are located at the top of 11 slot bottom of active area groove.
As shown in fig. 7, carrying out the merging and propulsion of N-type ion in the top of above-mentioned semiconductor substrate 1, have to obtain being located at
Substrate N+ active layer 16 in source region, the substrate N+ active layer 16 are located at the top of substrate P type base area 15, utilize field oxide
7 can stop N-type ion to be injected into terminal area.
As shown in figure 8, the dielectric layer deposition on the front of above-mentioned semiconductor substrate 1, the dielectric layer are covered on substrate N+
On active layer 16 and field oxide 7, to obtain substrate medium layer 17, the substrate medium layer 17 covers active area groove 11
Notch；The 4th photoresist layer 18 of coated substrate on substrate medium layer 17, using the 4th mask 19 of substrate to the 4th light of substrate
Photoresist layer 18 carries out photoetching, to obtain the 4th photoresist layer window 20 of substrate of the 4th photoresist layer 18 of through substrate, the base
The 4th photoresist layer window 20 of plate is located at the top of active area.
As shown in figure 9, using the 4th photoresist layer 18 of substrate and the 4th photoresist layer window 20 of substrate to substrate media
Layer 17, substrate N+ active layer 16 perform etching, to obtain substrate contact hole 24 corresponding with the 4th photoresist layer window 20 of substrate,
The 24 through substrate dielectric layer 17 of substrate contact hole, and substrate N+ source region 23 is obtained in the two sides of active area groove 11.
As shown in Figure 10, the 4th photoresist layer 18 of aforesaid substrate is removed, and carries out metal shallow lake in the front of semiconductor substrate 1
Product, to obtain front metal layer, the front metal layer is covered on substrate medium layer 17 and is filled in substrate contact hole 24.
The 5th photoresist layer 26 of coated substrate on front metal layer, and using the 5th mask 27 of substrate to substrate the 5th
Photoresist layer 26 carries out photoetching, described to obtain the 5th photoresist layer window 28 of substrate of the 5th photoresist layer 26 of through substrate
The 5th photoresist layer window 28 of substrate is located at the top of termination environment.Utilize the 5th photoresist layer 26 of substrate and the 5th photoetching of substrate
Glue-line window 28 performs etching substrate front side metal layer, separates hole 22 to obtain substrate metal, front metal layer passes through substrate
Metal separation hole 22 forms substrate terminal front metal 25 and substrate cellular front metal 21 after separating.
As shown in figure 11, it is passivated layer deposit in the positive top of above-mentioned semiconductor substrate 1, it is blunt to obtain substrate front side
Change layer 29, the substrate front side passivation layer 29 is covered on substrate terminal front metal layer 25 and substrate cellular front metal layer 21
On, and substrate front side passivation layer 29 is filled in substrate metal and separates in hole 22.
The 6th photoresist layer 30 of coated substrate on substrate front side passivation layer 29, and using the 6th mask 31 of substrate to base
The 6th photoresist layer 30 of plate carries out photoetching, and using the 6th photoresist layer 30 of substrate after photoetching to substrate front side passivation layer 29 into
Capable etching can be incited somebody to action with obtaining the substrate source pad hole 32 of through substrate front passivation layer 29 by substrate source pad hole 32
Substrate cellular front metal layer 21 exposes.
After removing the 6th photoresist layer 30 of substrate, the procedure of processing of source pad can be carried out；In addition, in semiconductor substrate
1 back side also needs to carry out back process, according to the available required MOSFET element of difference or IGBT device of back process
Part, back process can use existing common processing step, no longer superfluous herein specially known to those skilled in the art
It states.
To sum up, at least need to provide six masks when carrying out positive technique for MOSFET element or IGBT device
Version, with using the corresponding lithographic process steps of corresponding mask progress so that the MOSFET element that is prepared or
The preparation cost of IGBT device is higher.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of power half of low cost and high reliability is provided
Conductor device and preparation method thereof can improve the breakdown voltage of terminal area, reduce manufacturing cost, improve power semiconductor device
The UIS ability of part, it is compatible with prior art, securely and reliably.
According to technical solution provided by the invention, the power semiconductor of the low cost and high reliability, including have
Active area is arranged in the center of the semiconductor substrate, in the outer of the active area in the semiconductor substrate of first conduction type
Terminal protection area is arranged in circle, and the cellular in the active area uses groove structure；
It include substrate cellular groove and cellular marginal ditch in active area on the section of the power semiconductor
Slot, the engaging portion of the cellular edge groove adjacent active regions and terminal protection area in semiconductor substrate, cellular edge groove
Width be greater than substrate cellular groove width；
At cellular edge, cellular edge groove the second conduction type doped region, the cellular is arranged in the underface of groove slot bottom
Groove the second conduction type doped region in edge is contacted with the slot bottom of cellular edge groove, and lining is arranged in the two sides of substrate cellular groove
The second conduction type base region of bottom, the second conduction type base region of substrate are contacted with the lateral wall of respective substrate cellular groove；In cellular
The second conductivity type body region of substrate is arranged in the two sides of edge groove, and the second conductivity type body region of substrate is outer with cellular edge groove
Side wall contact, the doping that the doping concentration of second conduction type base region of substrate is greater than the second conductivity type body region of substrate are dense
Degree；The first conduction type of substrate source region, the first conduction type source region and lining are set in the second conduction type base region of substrate
The lateral wall of bottom cellular groove contacts；
Substrate cellular conductive polycrystalline silicon is filled in substrate cellular groove, the substrate cellular conductive polycrystalline silicon passes through life
It is longer than the side wall of the substrate cellular insulated gate oxide layer and place substrate cellular groove on substrate cellular trenched side-wall and bottom wall
And bottom wall is dielectrically separated from；Edge groove conductive polycrystalline silicon and substrate insulating medium layer are filled in cellular edge groove,
The substrate insulating medium layer is also covered on the front of semiconductor substrate, and edge groove conductive polycrystalline silicon is in cellular edge groove
The outer ring of substrate insulating medium layer in cellular edge groove, edge groove conductive polycrystalline silicon pass through edge insulated trench gate
Oxide layer and the side wall and bottom wall of cellular edge groove are dielectrically separated from；
Substrate source metal layer is set in semiconductor substrate positive top, the substrate source metal layer is supported on substrate
On insulating medium layer, substrate source metal layer and the second conduction type base region of substrate, substrate the first conduction type source region and member
The second conductivity type body region of substrate Ohmic contact of born of the same parents edge groove two sides.
On the section of the power semiconductor, terminal protection area uses groove structure, and terminal protection area includes eventually
Isolated groove is held, the second conductivity type body region of substrate, second conductive-type of substrate is arranged in the two sides of the terminal isolated groove
The area Xing Ti is located above the slot bottom of terminal isolated groove, and the lateral wall of substrate the second conductivity type body region and terminal isolated groove
Contact is filled with terminal isolated groove conductive polycrystalline silicon, the terminal isolated groove conductive polycrystalline silicon in terminal isolated groove
Pass through the side wall of the terminal isolated groove of the terminal isolated groove insulation gate oxide and place that are grown in terminal isolated groove
And bottom wall is dielectrically separated from, substrate insulating medium layer is covered on the notch of terminal isolated groove.
Further include the wide groove of terminal in terminal protection area, the width of the wide groove of terminal be greater than terminal isolated groove with
And the width of substrate cellular groove；Wide the second conduction type of the groove doping of setting terminal in the underface of the wide groove slot bottom of terminal
Area, wide groove the second conduction type doped region of terminal are contacted with the slot bottom of the wide groove of terminal, above the wide groove slot bottom of terminal
Two sides have the second conductivity type body region of substrate；The wide groove conductive polycrystalline silicon of terminal and substrate are filled in the wide groove of terminal
Insulating medium layer, the substrate that the wide groove conductive polycrystalline silicon of terminal is located in the wide groove of the terminal in the wide groove of terminal, which insulate, to be situated between
The outer ring of matter layer, the wide groove conductive polycrystalline silicon of terminal by the side wall of the wide channel insulation gate oxide of terminal and the wide groove of terminal with
And bottom wall is dielectrically separated from；
The wide groove of terminal and terminal isolated groove, substrate cellular groove and cellular edge groove pass through same technique
Step obtains, and the wide groove of terminal and terminal isolated groove, substrate cellular groove and cellular edge groove are in semiconductor substrate
Depth having the same, the wide groove of terminal are located between terminal isolated groove and cellular edge groove.
Substrate face passivation layer is set on the substrate source metal layer, lining is set in the substrate face passivation layer
Bottom source pad hole, substrate source pad hole Through-substrate front passivation layer, can be by substrate by substrate face passivation layer
Source metal is isolated with substrate terminal metal layer.
A kind of preparation method of the power semiconductor of low cost and high reliability, the preparation method include following step
It is rapid:
Step 1 provides the semiconductor substrate with the first conduction type, and carries out groove quarter to the semiconductor substrate
Erosion, to obtain required substrate trenches, the substrate trenches include substrate cellular groove, the cellular edge groove positioned at active area
And the terminal isolated groove positioned at termination environment, the width of cellular edge groove are greater than substrate cellular groove, cellular edge
Groove adjacent terminals protection zone in active area；
Step 2 carries out oxide layer growth and polysilicon filling in the front of above-mentioned semiconductor substrate, to obtain substrate oxygen
Change layer and substrate polysilicon body, the liner oxidation layer be grown in semiconductor substrate front and substrate trenches side wall with
Bottom wall, substrate polysilicon body are filled in substrate trenches, and substrate polysilicon body also covers the positive substrate oxygen of semiconductor substrate
Change on layer；
Step 3 carries out anisotropy time quarter to above-mentioned substrate polysilicon body, and performs etching to liner oxidation layer, with
The substrate cellular insulated gate oxide layer being located in substrate cellular groove and substrate cellular conductive polycrystalline silicon are obtained, at cellular edge
Edge channel insulation gate oxide, edge groove conductive polycrystalline silicon are obtained in groove and positioned at cellular marginal ditch groove center area
Edge groove injects location hole, and terminal isolated groove insulation gate oxide and terminal isolating trenches are obtained in terminal isolated groove
Slot conductive polycrystalline silicon, injecting location hole by edge groove can make the slot bottom of cellular edge groove exposed；
Step 4, above-mentioned semiconductor substrate front the second conductive type impurity ion injection and annealing, to obtain cross
Second conductive type layer of substrate on semiconductor substrate top is passed through, second conductive type layer of substrate is located at substrate trenches slot bottom
Top, and cellular edge groove the second conduction type doped region, the cellular edge are obtained immediately below cellular edge groove
Groove the second conduction type doped region is contacted with the slot bottom of cellular edge groove；
Step 5, the front surface coated photoresist layer in above-mentioned semiconductor substrate, and using the second mask plate of substrate to photoresist
Layer carries out photoetching, and to obtain the second photoresist layer of substrate, the terminal of the second photoresist layer of substrate covering semiconductor substrate is protected
Area is protected, the second photoresist layer of substrate, which is also filled up, to be injected positioning hole in edge groove and cover the notch of cellular edge groove；
Step 6 blocks semiconductor substrate using the second photoresist layer of substrate, carries out first to above-mentioned semiconductor substrate
Needed for being carried out after conductive type impurity ion, the injection of the second conductive type impurity ion and removal the second photoresist layer of substrate
Annealing process, to obtain the second conduction type base region of substrate in the active area of semiconductor substrate and be located at the substrate second
Substrate the first conduction type source region in conduction type base region, and the second conduction type of substrate below the second photoresist layer of substrate
Layer forms the second conductivity type body region of substrate, and the doping concentration of the second conduction type base region of substrate is greater than the second conduction type of substrate
The doping concentration in body area, the second conduction type base region of substrate, substrate the first conduction type source region and respective substrate cellular groove
Lateral wall contact；
Step 7 carries out dielectric layer deposition on the front of above-mentioned semiconductor substrate, to obtain covering semiconductor substrate front
Substrate insulating medium layer, the substrate insulating medium layer also fill up edge groove inject positioning hole；
Step 8, the coated substrate third photoresist layer on above-mentioned substrate insulating medium layer, and utilize substrate third mask
Photoetching is carried out to substrate third photoresist layer, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer；
Step 9, using substrate third photoresist layer and substrate third photoresist layer window to substrate insulating medium layer into
Row etching, the substrate to obtain the substrate insulating medium layer contact hole of Through-substrate insulating medium layer, on the outside of substrate cellular groove
Insulating medium layer contact hole also the first conduction type of Through-substrate source region；
Step 10, the above-mentioned substrate third photoresist layer of removal, and metal is carried out in the upper front of above-mentioned semiconductor substrate
Layer deposit, with the substrate metal layer being supported on substrate insulating medium layer, the substrate metal layer also fills up exhausted in substrate
In edge dielectric layer contact hole；The 4th photoresist layer of coated substrate on substrate metal layer, and using the 4th mask of substrate to lining
The 4th photoresist layer of bottom carries out photoetching, to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate；
Step 11 carves substrate metal layer using the 4th photoresist layer of substrate and the 4th photoresist layer window of substrate
Erosion separates hole to obtain the substrate metal of Through-substrate metal layer, and substrate metal layer is obtained active by substrate metal separation hole
Substrate source metal layer above area and the substrate terminal metal layer above terminal protection area, the substrate source gold
Belong to layer and the first conduction type of substrate source region, the second conduction type base region of substrate and the substrate second of cellular edge groove two sides
Conductivity type body region Ohmic contact；
Step 12, above-mentioned the 4th photoresist layer of substrate of removal, and be passivated layer in the front of above-mentioned semiconductor substrate and form sediment
Product, to obtain substrate face passivation layer, the substrate face passivation layer is filled in substrate metal and separates in hole, and substrate face is blunt
Change layer and is also covered on substrate source metal layer, on substrate terminal metal layer；
Step 13, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, and utilize the 5th mask of substrate
Version carries out photoetching to the 5th photoresist layer of substrate, to obtain the 5th photoresist layer window of substrate of the 5th photoresist layer of Through-substrate
Mouthful, substrate face passivation layer is performed etching using the 5th photoresist layer of substrate and the 5th photoresist layer window of substrate, with
To the substrate source pad hole of Through-substrate front passivation layer, the substrate source pad hole is corresponding with substrate source metal layer；
Step 14 carries out required back process at the back side of above-mentioned semiconductor substrate, to obtain required substrate back
Structure.
Further include the wide groove of terminal in terminal protection area, the width of the wide groove of terminal be greater than terminal isolated groove with
And the width of substrate cellular groove；Wide the second conduction type of the groove doping of setting terminal in the underface of the wide groove slot bottom of terminal
Area, wide groove the second conduction type doped region of terminal are contacted with the slot bottom of the wide groove of terminal, above the wide groove slot bottom of terminal
Two sides have the second conductivity type body region of substrate；The wide groove conductive polycrystalline silicon of terminal and substrate are filled in the wide groove of terminal
Insulating medium layer, the substrate that the wide groove conductive polycrystalline silicon of terminal is located in the wide groove of the terminal in the wide groove of terminal, which insulate, to be situated between
The outer ring of matter layer, the wide groove conductive polycrystalline silicon of terminal by the side wall of the wide channel insulation gate oxide of terminal and the wide groove of terminal with
And bottom wall is dielectrically separated from；
The wide groove of terminal and terminal isolated groove, substrate cellular groove and cellular edge groove pass through same technique
Step obtains, and the wide groove of terminal and terminal isolated groove, substrate cellular groove and cellular edge groove are in semiconductor substrate
Depth having the same, the wide groove of terminal are located between terminal isolated groove and cellular edge groove.
In step 1, in the first photoresist layer of front surface coated substrate of the semiconductor substrate, the first mask of substrate is utilized
Photoetching is carried out to the first photoresist layer of substrate, to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate,
After etching using the first photoresist layer of substrate and substrate the first photoresist layer window to the front of semiconductor substrate, institute can be obtained
The substrate trenches needed.
In step 6, the injection of the first conductive type impurity ion is first carried out, reinjects the second conductive type impurity ion
Injection, or the injection of the second conductive type impurity ion is first carried out, the injection of the first conductive type impurity ion is reinjected, or
Person carries out injecting while the first conductive type impurity ion, the second conductive type impurity ion simultaneously.
The material of the semiconductor substrate includes silicon.
Wide groove the second conduction type doped region of terminal and cellular edge groove the second conduction type doped region are same
One processing step layer.
In " first conduction type " and " the second conduction type " the two, N-type power semiconductor, first is led
Electric type refers to N-type, and the second conduction type is p-type；For p-type power semiconductor, the first conduction type and the second conductive-type
The type and N-type power semiconductor of type meaning are exactly the opposite.
Advantages of the present invention: settable terminal isolated groove and whole tapering gutter in the terminal protection area of semiconductor substrate
Terminal isolated groove insulating oxide and terminal isolated groove conductive polycrystalline silicon is arranged, at end in slot in terminal isolated groove
The wide groove conductive polycrystalline silicon of tapering gutter slot setting terminal, the wide channel insulation gate oxide of terminal simultaneously fill substrate insulating medium layer；
When carrying out the second conductive type impurity ion implanting using the second photoresist layer of substrate, it can be obtained in the two sides of substrate cellular groove
The second conduction type base region of substrate, and the second conductive-type of substrate is obtained in the two sides and terminal protection area of cellular edge groove
Second conductivity type body region of substrate in the area Xing Ti, terminal protection area cooperates with terminal isolated groove and/or matches with the wide groove of terminal
Required terminal protection area can be formed by closing, and obtain not needing mask when the second conductivity type body region of substrate, with prior art
It compares, trench-type power semiconductor device is enabled, less with one piece of mask, to effectively reduce power in Facad structure preparation
The preparation cost of semiconductor devices.
The first conductive type impurity ion can be carried out to the active area of semiconductor substrate using the second photoresist layer of substrate to infuse
Enter, the second conductive type impurity ion, after removal the second photoresist layer of substrate and annealing activation, it is conductive that substrate first can be obtained
The second conduction type base region of type source region and substrate, the energy in the case where guaranteeing the second conduction type base region of substrate doping concentration
It reduces and uses mask, further reduce the cost.Using the second conduction type base region of substrate in active area, it is able to achieve to active
The doping concentration of the second conduction type is adjusted in area, ensure that the prepared breakdown for obtaining power semiconductor termination environment
The on state characteristic of characteristic and active area, entire technical process is compatible with prior art, securely and reliably.
It can be formed simultaneously between substrate cellular groove, cellular edge groove, terminal isolated groove and the wide groove 71 of terminal, member
Born of the same parents edge groove, the wide groove of terminal width be greater than substrate cellular groove, terminal isolated groove width, thus in technical process
In, groove injection location hole in edge can be obtained in cellular edge groove, and the wide groove injection of terminal is obtained in the wide groove of terminal
Location hole, when the second conductive type impurity ion of injection obtains the second conductive type layer of substrate, it is fixed to be injected using edge groove
Position hole can obtain cellular edge groove the second conduction type doped region immediately below the slot bottom of cellular edge groove, wide using terminal
Groove injection location hole can obtain wide the second conduction type of the groove doped region of terminal immediately below the wide groove slot bottom of terminal, utilize
Substrate insulating medium layer in cellular edge groove the second conduction type doped region and cellular edge groove cooperates, and member can be improved
The breakdown voltage of born of the same parents edge groove prevents from puncturing at cellular edge groove so that breakdown occurs in active area, improves half
The UIS ability of conductor power device.In addition, utilizing the lining in wide groove the second conduction type doped region of terminal and the wide groove of terminal
The cooperation of bottom insulating medium layer, can be improved the breakdown voltage at the wide groove of terminal, prevents electric field from expanding to the end of semiconductor substrate
The edge for holding protection zone, further increases the safety and reliability of power semiconductor.
Detailed description of the invention
Fig. 1~Figure 11 is the specific step of preparation process cross-sectional view of existing power semiconductor, wherein
Fig. 1 is to obtain the cross-sectional view after substrate the first photoresist layer window.
Fig. 2 is the cross-sectional view after obtaining end ring.
Fig. 3 is the schematic diagram after performing etching to the field oxide of active area.
Fig. 4 is to obtain the cross-sectional view after active area groove.
Fig. 5 is to obtain the cross-sectional view after groove conductive polycrystalline silicon.
Fig. 6 is to obtain the cross-sectional view behind substrate P type base area.
Fig. 7 is to obtain the cross-sectional view after substrate N+ active layer.
Fig. 8 is to obtain the cross-sectional view after the 4th photoresist layer window of substrate.
Fig. 9 is to obtain the cross-sectional view after substrate contact hole.
Figure 10 is to obtain substrate metal to separate the cross-sectional view behind hole.
Figure 11 is to obtain the cross-sectional view behind substrate source pad hole.
Figure 12~Figure 21 is specific implementation process step cross-sectional view of the invention, wherein
Figure 12 is that the present invention obtains the cross-sectional view after substrate trenches.
Figure 13 is that the present invention obtains the cross-sectional view after substrate polysilicon body.
Figure 14 is that the present invention obtains the cross-sectional view after edge groove injection location hole.
Figure 15 is that the present invention obtains the cross-sectional view after substrate P-type layer and cellular edge groove P-doped zone.
Figure 16 is that the present invention obtains the cross-sectional view after the second photoresist layer of substrate.
Figure 17 is that the present invention obtains the cross-sectional view behind substrate N+ source region, substrate p-type base area.
Figure 18 is that the present invention obtains the cross-sectional view after substrate third photoresist layer window.
Figure 19 is that the present invention obtains the cross-sectional view after substrate insulating medium layer contact hole.
Figure 20 is that the present invention obtains the cross-sectional view behind metal separation hole.
Figure 21 is that the present invention obtains the cross-sectional view after substrate source pad hole.
Figure 22 is cross-sectional view when the wide groove of terminal is arranged in the present invention in terminal protection area.
Description of symbols: 1- semiconductor substrate, the first photoresist layer of 2- substrate, the first mask of 3- substrate, 4- substrate
First photoresist layer window, 5- end ring, the second mask of 6- substrate, 7- field oxide, the second photoresist layer of 8- substrate, 9- base
Plate third photoresist layer, 10- substrate third mask, 11- active area groove, 12- substrate third photoresist layer window, 13- are exhausted
Edge gate oxide, 14- groove conductive polycrystalline silicon, 15- substrate P type base area, 16- substrate N+ active layer, 17- substrate medium layer, 18-
The 4th photoresist layer of substrate, the 4th mask of 19- substrate, the 4th photoresist layer window of 20- substrate, 21- substrate cellular front gold
Belong to, 22- substrate metal separates hole, 23- substrate N+ source region, 24- substrate contact hole, 25- substrate terminal front metal, 26- substrate
5th photoresist layer, the 5th mask of 27- substrate, the 5th photoresist layer window of 28- substrate, 29- substrate front side passivation layer, 30-
The 6th photoresist layer of substrate, the 6th mask of 31- substrate, 32- substrate source pad hole, the first mask of 33- substrate, 34- lining
The first photoresist layer of bottom, 35- substrate cellular groove, 36- cellular edge groove, 37- terminal isolated groove, 38- semiconductor substrate,
39- liner oxidation layer, 40- substrate polysilicon body, 41- substrate cellular insulated gate oxide layer, 42- substrate cellular conductive polycrystalline silicon,
The edge 43- channel insulation gate oxide, the edge 44- groove conductive polycrystalline silicon, 45- terminal isolated groove insulation gate oxide, 46-
Terminal isolated groove conductive polycrystalline silicon, 47- substrate P-type layer, 48- cellular edge groove P-doped zone, the injection of the edge 49- groove
Location hole, the second mask of 50- substrate, the second photoresist layer of 51- substrate, the area 52- substrate PXing Ti, 53- substrate p-type base area,
54- substrate N+ source region, 55- substrate third photoresist layer, 56- substrate third mask, 57- substrate third photoresist layer window,
58- substrate insulating medium layer, 59- substrate insulating medium layer contact hole, 60- substrate terminal metal layer, the 4th mask of 61- substrate
Version, the 4th photoresist layer of 62- substrate, the 4th photoresist layer window of 63- substrate, the 5th mask of 64- substrate, 65- substrate the 5th
Photoresist layer, the 5th photoresist layer window of 66- substrate, 67- substrate face passivation layer, 68- metal separation hole, 69- substrate source
Pad hole, 70- substrate source metal layer, the wide groove of 71- terminal, the wide trench P-type doped region of 72- terminal, the wide groove of 73- terminal are led
Electric polysilicon and the wide channel insulation gate oxide of 74- terminal.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
As shown in figure 21: the breakdown voltage in order to improve terminal area improves the UIS ability of power semiconductor,
By taking N-type power semiconductor as an example, the present invention includes having the semiconductor substrate 38 of N conduction type, is served as a contrast in the semiconductor
Active area is arranged in the center at bottom 38, terminal protection area is arranged in the outer ring of the active area, the cellular in the active area is adopted
Use groove structure；
It include substrate cellular groove 35 and cellular marginal ditch in active area on the section of the power semiconductor
Slot 36, the engaging portion of cellular edge groove 36 adjacent active regions and terminal protection area in semiconductor substrate, cellular edge
The width of groove 36 is greater than the width of substrate cellular groove 35；
At cellular edge, cellular edge groove P-doped zone 48, the cellular edge is arranged in the underface of 36 slot bottom of groove
Trench P-type doped region 48 is contacted with the slot bottom of cellular edge groove 36, and substrate p-type base is arranged in the two sides of substrate cellular groove 35
Area 53, substrate p-type base area 53 are contacted with the lateral wall of respective substrate cellular groove 35；The two sides setting of groove 36 at cellular edge
The area substrate PXing Ti 52, the area substrate PXing Ti 52 are contacted with the lateral wall of cellular edge groove 36, and substrate p-type base area 53 is mixed
Miscellaneous concentration is greater than the doping concentration in the area substrate PXing Ti 52；Substrate N+ source region 54, the substrate N are set in substrate p-type base area 53
+ source region 54 is contacted with the lateral wall of substrate cellular groove 35；
Substrate cellular conductive polycrystalline silicon 42, the substrate cellular conductive polycrystalline silicon 42 are filled in substrate cellular groove 35
Pass through the substrate cellular insulated gate oxide layer 41 and place substrate cellular being grown on 35 side wall of substrate cellular groove and bottom wall
The side wall and bottom wall of groove 35 are dielectrically separated from；In cellular edge groove 36 filled with edge groove conductive polycrystalline silicon 44 and
Substrate insulating medium layer 58, the substrate insulating medium layer 58 are also covered on the front of semiconductor substrate 38, and edge groove is conductive
Polysilicon 44 is located at the outer ring of the substrate insulating medium layer 58 in cellular edge groove 36, marginal ditch in cellular edge groove 36
Slot conductive polycrystalline silicon 44 by side wall and the bottom wall insulation of edge channel insulation gate oxide 43 and cellular edge groove 36 every
From；
Substrate source metal layer 70 is set in the positive top of semiconductor substrate 38, the substrate source metal layer 70 supports
On substrate insulating medium layer 58, substrate source metal layer 70 and substrate p-type base area 53, substrate N+ source region 54 and cellular edge
52 Ohmic contact of the area substrate PXing Ti of 36 two sides of groove.
Specifically, the material of semiconductor substrate 38 can be silicon or other common semiconductor materials, specifically can basis
It is selected, details are not described herein again.Generally, active area is located at the center of semiconductor substrate 38, terminal protection position
In the outer ring of active area, active area can be protected using terminal protection area, improve entire power semiconductor work
Reliability, active area, terminal protection section it is specific effect and it is known to those skilled in the art with being combined into, herein
No longer it is described in detail.
In the embodiment of the present invention, the cellular in active area uses groove structure, thus in the section of power semiconductor
On, it include substrate cellular groove 35 and cellular edge groove 36 in active area, wherein the width of cellular edge groove 36 is big
In the width of substrate cellular groove 35, generally, cellular edge groove 36, substrate cellular groove 35 are in semiconductor substrate 38
Depth is identical, substrate cellular groove 35, cellular edge groove 36 notch be located at the front of semiconductor substrate 38, substrate cellular ditch
Slot 35, the corresponding depth of cellular edge groove 36 are less than the thickness of semiconductor substrate 38.Cellular edge groove 36 is in active area
Adjacent terminals protection zone, substrate cellular groove 35 are located at the inside of cellular edge groove 36.
The width of cellular edge groove P-doped zone 48 is less than the width of cellular edge groove 36, cellular edge trench P-type
Doped region 48 and the area substrate PXing Ti 52 are same processing step floor, cellular edge groove P-doped zone 48 and cellular edge groove
36 slot bottom contact, the area substrate PXing Ti 52 is located at the two sides of cellular edge groove 36 and the lateral wall with cellular edge groove 36
Contact.The area substrate PXing Ti 52 is located at the top of 36 slot bottom of cellular edge groove.For each substrate cellular groove 35, in substrate
The two sides of cellular groove 35 are respectively provided with substrate p-type base area 53, and substrate N+ source region 54, substrate p-type are arranged in substrate p-type base area 53
Base area 53 also is located at the top of 35 slot bottom of substrate cellular groove, the lining in substrate p-type base area 53 and substrate p-type base area 53
Bottom N+ source region 54 is contacted with the lateral wall of neighbouring substrate cellular groove 35.The doping concentration of substrate p-type base area 53 is greater than lining
The doping concentration of the area DiPXing Ti 52 and cellular edge groove P-doped zone 48.
Substrate cellular conductive polycrystalline silicon 42 is filled in substrate cellular groove 35, and edge groove conductive polycrystalline silicon 44 is located at member
In born of the same parents edge groove 36, in side wall and bottom wall growth substrates cellular the insulation gate oxide 41 of substrate cellular groove 35, thus
Substrate cellular conductive polycrystalline silicon 42 can by the side wall of substrate cellular insulated gate oxide layer 41 and place substrate cellular groove 35 with
And bottom wall is dielectrically separated from；Similarly, edge trench polisilicon 41 passes through edge channel insulation gate oxide 43 and cellular edge groove
36 side wall and bottom wall is dielectrically separated from.In addition, substrate insulating medium layer 58 is also filled up in the center of cellular edge groove 36,
Substrate insulating medium layer 58, substrate cellular insulated gate oxide layer 41 and edge channel insulation gate oxide 43 are silica
Layer；In cellular edge groove 36, edge groove conductive polycrystalline silicon 44 is located at the outer ring of substrate insulating medium layer 58, cellular edge
Trench P-type doped region 48 is positive corresponding with the substrate insulating medium layer 58 in cellular edge groove 36, generally, cellular edge groove
The width of P-doped zone 48 is consistent with width of the substrate insulating medium layer 58 in cellular edge groove 36.At cellular edge
In groove 36 after filling substrate insulating medium layer 58, due to substrate insulating medium layer 58 and edge channel insulation gate oxide 43
It is all silicon dioxide layer, substrate insulating medium layer 58, edge channel insulation gate oxide 43 can ensure that porch groove is conductive
Side wall between polysilicon 44 and cellular edge groove 36, bottom wall are dielectrically separated from.Certainly, substrate insulating medium layer 58 is filled in cellular
When in edge groove 36, it is also covered on the front of semiconductor substrate 38.
In the embodiment of the present invention, the width of cellular edge groove 36 is greater than the width of substrate cellular groove 35, so as to side
Just in the slot bottom shape cellular edge groove P-doped zone 48 of cellular edge groove 36, and lining is filled in cellular edge groove 36
Bottom insulating medium layer 58 utilizes the substrate insulating medium layer in cellular edge groove P-doped zone 48 and cellular edge groove 36
58 cooperations, can be improved the breakdown voltage of cellular edge groove 36, so that breakdown occurs in active area, prevent cellular marginal ditch
Puncture at slot 36, improves UIS (Unclamped Inductive Switching) ability of semiconductor power device.
Substrate source metal layer 70 is supported on substrate insulating medium layer 58, substrate source metal layer 70 with substrate p-type
52 Ohmic contact of the area substrate PXing Ti of 36 two sides of base area 53, substrate N+ source region 54 and cellular edge groove, to pass through substrate
Source metal 70 can form the source electrode of power semiconductor.By by substrate cellular conductive polycrystalline silicon 42 and edge groove
Conductive polycrystalline silicon 44 can form the gate electrode of power semiconductor after drawing, in addition it is also necessary in the back of semiconductor substrate 38
Wheat flour makees backside structure, and the collector or emitter of power semiconductor can be formed by backside structure, specific to form grid electricity
Pole, backside structure concrete form can according to need and need carrying out selection determination, the specially skill of the art
Known to art personnel, details are not described herein again.
Further, on the section of the power semiconductor, terminal protection area uses groove structure, terminal protection
Area includes terminal isolated groove 37, and the area substrate PXing Ti 52, the substrate p-type body is arranged in the two sides of the terminal isolated groove 37
Area 52 is located above the slot bottom of terminal isolated groove 37, and the area substrate PXing Ti 52 is contacted with the lateral wall of terminal isolated groove 37,
Terminal isolated groove conductive polycrystalline silicon 46, the terminal isolated groove conductive polycrystalline silicon 46 are filled in terminal isolated groove 37
Pass through the terminal isolated groove insulation gate oxide 45 and place terminal isolated groove 37 being grown in terminal isolated groove 37
Side wall and bottom wall are dielectrically separated from, and substrate insulating medium layer 58 is covered on the notch of terminal isolated groove 37.
In the embodiment of the present invention, terminal protection area also uses groove structure, i.e., includes that terminal is isolated in terminal protection area
Groove 37, terminal isolated groove 37 are that same technique is prepared with substrate cellular groove 35 and cellular edge groove 36, eventually
Hold isolated groove 37 and the depth having the same of substrate cellular groove 35.It is raw on the side wall and bottom wall of terminal isolated groove 37
With terminal isolated groove insulation gate oxide 45, the terminal isolated groove conductive polycrystalline silicon being filled in terminal isolated groove 37
46 can be dielectrically separated from by terminal isolated groove insulation gate oxide 45 with the side wall and bottom wall of terminal isolated groove 37.Due to
Substrate insulating medium layer 58 is covered on the front of semiconductor substrate 38, so that substrate insulating medium layer 58 can cover terminal isolating trenches
The notch of slot 37.In addition, also setting up substrate terminal metal layer 60, the substrate terminal metal layer in the top in terminal protection area
60 with substrate source metal layer 70 be same processing step layer.When it is implemented, substrate terminal metal layer 60 can be removed or protected
Substrate terminal metal layer 60 is stayed, the substrate terminal metal layer 60 and 52 Ohmic contact of the area substrate PXing Ti of reservation specifically can bases
It is selected, details are not described herein again.
It as shown in figure 22, further include the wide groove 71 of terminal in terminal protection area, the width of the wide groove 71 of terminal is big
In terminal isolated groove 37 and the width of substrate cellular groove 35；In the underface of wide 71 slot bottom of groove of terminal, setting terminal is wide
Trench P-type doped region 72, the wide trench P-type doped region 72 of terminal are contacted with the slot bottom of the wide groove 71 of terminal, the wide groove of terminal
Two sides above 71 slot bottoms have the area substrate PXing Ti 52；The wide groove conductive polycrystalline silicon 73 of terminal is filled in the wide groove 71 of terminal
And substrate insulating medium layer 58, the wide groove conductive polycrystalline silicon 73 of terminal are located at the wide groove of the terminal in the wide groove 71 of terminal
The outer ring of substrate insulating medium layer 58 in 71, the wide groove conductive polycrystalline silicon 73 of terminal pass through the wide channel insulation gate oxide of terminal
74 are dielectrically separated from the side wall and bottom wall of the wide groove 71 of terminal；
The wide groove 71 of terminal passes through with terminal isolated groove 37, substrate cellular groove 35 and cellular edge groove 36
Same processing step obtains, the wide groove 71 of terminal and terminal isolated groove 37, substrate cellular groove 35 and cellular edge groove
36 in semiconductor substrate 58 depth having the same, the wide groove 71 of terminal be located at terminal isolated groove 37 and cellular edge groove
Between 36.
In the embodiment of the present invention, the wide groove 71 of one or more terminals, whole tapering gutter can be set in terminal protection area
Slot 71 is located between terminal isolated groove 37 and cellular edge groove 36, and the width of the wide groove 71 of terminal is greater than terminal isolated groove
37 width, generally, the width of the wide groove 71 of terminal can be identical with the width of cellular edge groove 36.In the wide groove of terminal
The wide trench P-type doped region 72 of terminal, the wide trench P-type doped region 72 of terminal and cellular edge trench P-type is arranged in the lower section of 71 slot bottoms
Doped region 48, the area substrate PXing Ti 52 are same processing step floor.Terminal is grown on the side wall and bottom wall of the wide groove 71 of terminal
Wide channel insulation gate oxide 74, the wide groove conductive polycrystalline silicon 73 of terminal being filled in the wide groove 71 of terminal pass through whole tapering gutter
Slot insulation gate oxide 74 and the side wall and bottom wall of the wide groove 71 of terminal are dielectrically separated from.
Similar with cellular edge groove 36, substrate insulating medium layer 58 is also filled in the wide groove 71 of terminal, wide in terminal
In groove 71, the wide groove conductive polycrystalline silicon 73 of terminal is located at the outer ring of substrate insulating medium layer 58, the wide trench P-type doped region of terminal
72 contact with the slot bottom of the wide groove 71 of terminal, the width of the wide trench P-type doped region 72 of terminal and are filled in the wide groove 71 of terminal
The width of substrate insulating medium layer 58 is consistent.Specifically, the wide groove 71 of the terminal and terminal isolated groove 37, substrate cellular
Groove 35 and cellular edge groove 36 are obtained by same processing step, the wide groove 71 of terminal and terminal isolated groove 37, lining
Bottom cellular groove 35 and cellular edge groove 36 depth having the same in semiconductor substrate 58.
Further, substrate face passivation layer 67 is set on the substrate source metal layer 70, in the substrate face
Substrate source pad hole 69 is set in passivation layer 67, and the 69 Through-substrate front passivation layer 67 of substrate source pad hole passes through
Substrate source metal layer 70 can be isolated with substrate terminal metal layer 60 for substrate face passivation layer 67.
In the embodiment of the present invention, substrate face passivation layer 67 can be silicon nitride, and substrate face passivation layer 67 is supported on lining
In bottom source metal 70 and substrate terminal metal layer 60, and substrate source metal is able to achieve by substrate face passivation layer 67
Layer 70, substrate terminal metal layer 60 are isolated, and can make the corresponding area of substrate source metal layer 70 by substrate source pad hole 69
Domain is exposed, to draw substrate source metal layer 70.
As shown in Figure 12~Figure 22, the power semiconductor of above structure can be prepared by following processing steps
It arrives, specifically, the preparation method includes the following steps:
Step 1 provides the semiconductor substrate 38 with N conduction type, and carries out groove quarter to the semiconductor substrate 38
Erosion, to obtain required substrate trenches, the substrate trenches include substrate cellular groove 35, the cellular marginal ditch positioned at active area
The width of slot 36 and terminal isolated groove 37 positioned at termination environment, cellular edge groove 36 is greater than substrate cellular groove
35, the adjacent terminals protection zone in active area of cellular edge groove 36；
Specifically, the material of semiconductor substrate 38 can be with silicon, in the front surface coated substrate first of the semiconductor substrate 58
Photoresist layer 34 carries out photoetching to the first photoresist layer of substrate 34 using the first mask of substrate 33, to obtain Through-substrate the
Substrate the first photoresist layer window of one photoresist layer 34, utilizes the first photoresist layer of the first photoresist layer of substrate 34 and substrate
After window is to the front etching of semiconductor substrate 38, required substrate trenches can be obtained, as shown in figure 12.In addition, in semiconductor
The terminal protection area of substrate 38 can also include the wide groove 71 of terminal, that is, utilize the first photoresist layer of substrate 34 and substrate first
Photoresist layer window can etch simultaneously to obtain substrate cellular groove 35, cellular edge groove 36, end in semiconductor substrate 38
Isolated groove 37 and the wide groove 71 of terminal are held, the process for specifically performing etching to obtain substrate trenches to semiconductor substrate 38 is this
Known to technical field personnel, details are not described herein again.
Step 2 carries out oxide layer growth and polysilicon filling in the front of above-mentioned semiconductor substrate 38, to obtain substrate
Oxide layer 39 and substrate polysilicon body 40, the liner oxidation layer 39 are grown in front and the substrate ditch of semiconductor substrate 38
The side wall and bottom wall of slot, substrate polysilicon body 40 are filled in substrate trenches, and substrate polysilicon body 40 also covers semiconductor lining
On the positive liner oxidation layer 39 in bottom 38；
Specifically, liner oxidation layer 39 can be obtained by thermal oxidation technology, certainly, before carrying out thermal oxidation technology,
It needs to remove the first photoresist layer of substrate 34 on 38 front of semiconductor substrate using common technological means.Work as terminal protection
In area when groove wide with terminal, substrate cellular groove 35, cellular edge groove 36, end are gone back while being grown in liner oxidation layer 39
Isolated groove 37 and the terminal corresponding side wall of wide groove 71 and bottom wall are held, meanwhile, substrate polysilicon body 40 is filled simultaneously
There are substrate cellular groove 35, cellular edge groove 36, terminal isolated groove 37 and the terminal of liner oxidation layer 39 wide in growth
In groove 71, as shown in figure 13.Substrate conduction polysilicon can be with substrate cellular groove 35, cellular edge by liner oxidation layer 39
Groove 36, terminal isolated groove 37 and the terminal corresponding side wall of wide groove 71 and bottom wall are dielectrically separated from.Liner oxidation layer
39 be silicon dioxide layer.
Step 3 carries out anisotropy time quarter to above-mentioned substrate polysilicon body 40, and carves to liner oxidation layer 39
Erosion, to obtain the substrate cellular insulated gate oxide layer 41 being located in substrate cellular groove 35 and substrate cellular conductive polycrystalline silicon
42, edge channel insulation gate oxide 43, edge groove conductive polycrystalline silicon 44 are obtained in cellular edge groove 36 and are located at
The edge groove of 36 center of cellular edge groove injects location hole 49, and terminal isolated groove is obtained in terminal isolated groove 37
Insulate gate oxide 45 and terminal isolated groove conductive polycrystalline silicon 46, and cellular can be made by injecting location hole 49 by edge groove
The slot bottom of edge groove 36 is exposed；
Specifically, substrate polysilicon body 40 carve using the art common technological means, and to substrate
Oxide layer 39 performs etching, so as to remove the liner oxidation layer 39 and substrate polysilicon body on 38 front of semiconductor substrate
40, so as to obtain the substrate cellular insulated gate oxide layer 41 being located in substrate cellular groove 35 and substrate cellular conductive polycrystalline
Silicon 42 obtains edge channel insulation gate oxide 43, edge groove conductive polycrystalline silicon 44 and position in cellular edge groove 36
Edge groove in 36 center of cellular edge groove injects location hole 49, and terminal isolating trenches are obtained in terminal isolated groove 37
Slot insulation gate oxide 45 and terminal isolated groove conductive polycrystalline silicon 46, member can be made by injecting location hole 49 by edge groove
The slot bottom of 36 center of born of the same parents edge groove is exposed, as shown in figure 14.
When groove 71 wide with terminal in terminal protection area, moreover it is possible to it is wide to obtain the terminal being located in the wide groove 71 of terminal
Channel insulation gate oxide 74 and the wide groove conductive polycrystalline silicon 73 of terminal, the wide groove conductive polycrystalline silicon 73 of terminal pass through terminal ditch
Slot insulation gate oxide 74 can side wall corresponding with the wide groove 71 of terminal and bottom wall be dielectrically separated from, meanwhile, in the wide groove of terminal
71 center obtains the wide groove injection location hole of terminal, and the wide groove 71 of terminal can be made by injecting location hole by the wide groove of terminal
The slot bottom of center is exposed.
Step 4, above-mentioned semiconductor substrate 38 front p type impurity ion injection and annealing, partly led with obtaining traversing
The substrate P-type layer 47 on 38 top of body substrate, the substrate P-type layer 47 are located at the top of substrate trenches slot bottom, and at cellular edge
The underface of groove 36 obtains cellular edge groove P-doped zone 48, the cellular edge groove P-doped zone 48 and cellular side
The slot bottom of edge groove 36 contacts；
Specifically, the injection and annealing that p type impurity ion is carried out using the common process conditions of the art, can obtain
Substrate P-type layer 47, substrate P-type layer 47 are located at 37 slot of substrate cellular groove 35, cellular edge groove 36 and terminal isolated groove
The top at bottom, and substrate P-type layer 47 is corresponding with substrate cellular groove 35, cellular edge groove 36 and terminal isolated groove 37
Lateral wall contact.When carrying out p type impurity ion implanting, cellular edge groove just corresponding with edge groove injection location hole 49
36 slot bottom is exposed, so as to obtain cellular edge groove P-doped zone 48 below 36 slot bottom of cellular edge groove, i.e., first
The doping concentration of born of the same parents edge groove P-doped zone 48 is identical as the doping concentration of substrate P-type layer 47, as shown in figure 15.
It, can be wide in terminal using the wide groove injection location hole of terminal when groove 71 wide with terminal in terminal protection area
The wide trench P-type doped region 72 of terminal, the wide trench P-type doped region 72 of terminal and the wide groove of terminal are obtained immediately below 71 slot bottom of groove
71 slot bottom contact.
Step 5, in the front surface coated photoresist layer of above-mentioned semiconductor substrate 38, and utilize 50 pairs of light of the second mask plate of substrate
Photoresist layer carries out photoetching, and to obtain the second photoresist layer of substrate 51, second photoresist layer of substrate 51 covers semiconductor substrate
38 terminal protection area, the second photoresist layer of substrate 51 also fill up in edge groove injection location hole 49 and cover cellular edge
The notch of groove 36；
Specifically, the process of required the second photoresist layer of substrate 51 is prepared by the second mask of substrate 50 as this technology neck
Known to the personnel of domain, details are not described herein again.Obtained the second photoresist layer of substrate 51 covers the terminal protection of semiconductor substrate 38
Area, and the notch of cellular edge groove 36 is also filled up in edge groove injection location hole 49 and covers, as shown in figure 16.
When groove 71 wide with terminal in terminal protection area, the second photoresist layer of substrate 51 is also filled up in whole tapering gutter
The wide groove of the terminal of slot 71 injects positioning hole, and covers the notch of the wide groove 71 of terminal.Pass through the second photoresist layer of substrate
51 can the region on the outside of 36 notch of terminal protection area and cellular edge groove to semiconductor substrate 38 block, semiconductor
The corresponding region of 38 active area of substrate is in unobstructed state, prepares for subsequent progress ion implanting.
Step 6, using 51 blocking to semiconductor substrate 38 of the second photoresist layer of substrate, to above-mentioned semiconductor substrate 38 into
Required annealing process is carried out after row N-type impurity ion, the injection of p type impurity ion and removal the second photoresist layer of substrate 51,
To obtain substrate p-type base area 53 and the substrate N in substrate p-type base area 53 in the active area of semiconductor substrate 58
+ source region 54, and the substrate P-type layer 47 of 51 lower section of the second photoresist layer of substrate forms the area substrate PXing Ti 52, substrate p-type base area 53
Doping concentration be greater than the area substrate PXing Ti 52 doping concentration, substrate p-type base area 53, substrate N+ source region 54 and respective substrate member
The lateral wall of born of the same parents' groove 35 contacts；
Specifically, using 51 blocking to semiconductor substrate 38 of the second photoresist layer of substrate, N-type impurity ion, P are being carried out
After type foreign ion injection, need to remove after the second photoresist layer of substrate 51 carries out annealing process again, so as to be served as a contrast in semiconductor
It obtains substrate p-type base area 53, that is, passing through the substrate P-type layer in the p type impurity ion and active area of injection in the active area at bottom 38
Substrate p-type base area 53 is collectively formed in 47 cooperations, and can be formed by the substrate P-type layer 47 that the second photoresist layer of substrate 51 blocks lower section
The area substrate PXing Ti 52, so that the doping concentration of substrate p-type base area 53 is greater than the doping concentration in the area substrate PXing Ti 52, specific implementation
When, the second photoresist layer of substrate 51, the specific technique for carrying out annealing process are removed using the common technological means of the art
Condition etc. with it is existing consistent, if annealing temperature is at 800 DEG C or more, specially known to those skilled in the art, herein not
It repeats again.
When it is implemented, can first carry out N-type impurity in order to prepare substrate p-type base area 53 and substrate N+ source region 54
The injection of ion reinjects the injection of p type impurity ion, or first carries out the injection of p type impurity ion, reinjects N-type impurity
The injection of ion, or injection while N-type impurity ion, p type impurity ion is carried out simultaneously, specific order can according to need
It is selected, details are not described herein again.It is specific to carry out N-type impurity ion implanting, the process conditions of p type impurity ion implanting and annealing
It is known to those skilled in the art, compared with the prior art, substrate p-type base area 53 and substrate is being prepared in the present invention
When N+ source region 54, do not increase mask plate additionally, not will increase the cost of processing, as shown in figure 17.
Step 7 carries out dielectric layer deposition on the front of above-mentioned semiconductor substrate 38, to obtain covering semiconductor substrate 38
Positive substrate insulating medium layer 58, the substrate insulating medium layer 58 also fill up in edge groove injection location hole 49；
Specifically, the material of substrate insulating medium layer 58 is silica, when deposit obtains substrate insulating medium layer 58,
Substrate insulating medium layer 58 can be filled in the injection location hole 49 of the edge groove in cellular edge groove 36.Certainly, in terminal
In protection zone when groove 71 wide with terminal, substrate insulating medium layer 58 also fills up the wide groove note of terminal in the wide groove 71 of terminal
Enter positioning hole.
Step 8, the coated substrate third photoresist layer 55 on above-mentioned substrate insulating medium layer 58, and covered using substrate third
Template 56 carries out photoetching to substrate third photoresist layer 55, to obtain the substrate third photoetching of Through-substrate third photoresist layer 55
Glue-line window 57；
Specifically, it coats to obtain substrate third photoresist layer 55 using the common technological means of the art, and utilizes
Substrate third mask 56 carries out photoetching to substrate third photoresist layer 55, to obtain substrate third photoresist layer window 57, such as
Shown in Figure 18.
Step 9, using substrate third photoresist layer 55 and substrate third photoresist layer window 57 to substrate dielectric
Layer 58 performs etching, to obtain the substrate insulating medium layer contact hole 59 of Through-substrate insulating medium layer 58, substrate cellular groove
The substrate insulating medium layer contact hole 59 in 35 outsides goes back Through-substrate N+ source region 54；
Specifically, using substrate third photoresist layer 55 and substrate third photoresist layer window 57 to substrate dielectric
Layer 58 performs etching, and can obtain substrate insulating medium layer contact hole 59, the insulation of 58 Through-substrate of substrate insulating medium layer contact hole
The substrate insulating medium layer contact hole 59 of dielectric layer 58,35 outside of substrate cellular groove goes back Through-substrate N+ source region 54, cellular side
The substrate insulating medium layer contact hole 59 of 36 two sides of edge groove can enter the area substrate PXing Ti 52 of 36 two sides of cellular edge groove
It is interior, as shown in figure 19.
Step 10, the above-mentioned substrate third photoresist layer 55 of removal, and carried out in the upper front of above-mentioned semiconductor substrate 38
Metal layer deposit, with the substrate metal layer being supported on substrate insulating medium layer 58, the substrate metal layer is also filled up
In substrate insulating medium layer contact hole 59；The 4th photoresist layer 62 of coated substrate on substrate metal layer, and utilize substrate the 4th
Mask 61 carries out photoetching to the 4th photoresist layer 62 of substrate, to obtain the 4th light of substrate of the 4th photoresist layer 62 of Through-substrate
Photoresist layer window 63；
Specifically, removal and the gold of substrate third photoresist layer 55 are realized using the common technological means of the art
Belonging to the deposit of layer, substrate metal layer is supported on substrate insulating medium layer 58, after being filled in substrate insulating medium layer contact hole 59,
Substrate metal layer can be with the area substrate PXing Ti 52 of 36 two sides of substrate p-type base area 53, substrate N+ source region 54 and cellular edge groove
Ohmic contact.
In order to perform etching to substrate metal layer, coating obtains the 4th photoresist layer 62 of substrate on substrate metal layer,
And photoetching is carried out to the 4th photoresist layer 62 of substrate using the 4th mask 61 of substrate, to obtain the 4th photoresist layer window of substrate
63, the 4th photoresist layer 62 of 63 Through-substrate of the 4th photoresist layer window of substrate.
Step 11, using the 4th photoresist layer 62 of substrate and the 4th photoresist layer window 63 of substrate to substrate metal layer into
Row etching separates hole 68 to obtain the substrate metal of Through-substrate metal layer, and substrate metal layer separates hole 68 by substrate metal
The substrate source metal layer 70 of active region and the substrate terminal metal layer 60 above terminal protection area are obtained, it is described
The substrate p-type body of substrate source metal layer 70 and 36 two sides of substrate N+ source region 54, substrate p-type base area 53 and cellular edge groove
52 Ohmic contact of area；
Specifically, the substrate metal separates hole 68 and the 4th photoresist layer window 63 of substrate is positive corresponding, passes through substrate gold
Substrate metal layer can be separated to obtain substrate source metal layer 70 and substrate terminal metal layer 60 by belonging to separation hole 68, such as Figure 20 institute
Show.Generally, substrate source metal layer 70 is located at the active area of semiconductor substrate 38, and substrate terminal metal layer 60 is located at semiconductor
The termination environment of substrate 38 obtains substrate source metal layer 70 and substrate N+ source region 54, substrate p-type base area 53 and cellular marginal ditch
52 Ohmic contact of the area substrate PXing Ti of 36 two sides of slot.
Step 12, above-mentioned the 4th photoresist layer 62 of substrate of removal, and be passivated in the front of above-mentioned semiconductor substrate 38
Layer deposit, to obtain substrate face passivation layer 67, the substrate face passivation layer 67 is filled in substrate metal and separates in hole 68, and
Substrate face passivation layer 67 is also covered on substrate source metal layer 70, on substrate terminal metal layer 60；
Specifically, the removal of the 4th photoresist layer 62 of substrate and blunt is realized using the common technological means of the art
Change the deposit of layer, so as to obtain substrate face passivation layer 67, substrate face passivation layer 67 is filled in substrate metal and separates hole 68
After interior, being isolated between substrate source metal layer 70 and substrate terminal metal layer 60 is able to achieve by substrate face passivation layer 67,
The material of substrate face passivation layer 67 is generally silicon nitride.
Step 13, the 5th photoresist layer 65 of coated substrate on above-mentioned substrate face passivation layer 67, and utilize substrate the 5th
Mask 64 carries out photoetching to the 5th photoresist layer 65 of substrate, to obtain the 5th light of substrate of the 5th photoresist layer 65 of Through-substrate
Photoresist layer window 66, using the 5th photoresist layer 65 of substrate and the 5th photoresist layer window 66 of substrate to substrate face passivation layer
67 perform etching, to obtain the substrate source pad hole 69 of Through-substrate front passivation layer 67, the substrate source pad hole 69
It is corresponding with substrate source metal layer 70；
Specifically, the 5th photoresist layer window 66 of substrate is located at the top of substrate source metal layer 70, utilizes substrate the 5th
Photoresist layer 65 and the 5th photoresist layer window 66 of substrate perform etching substrate face passivation layer 67, to obtain Through-substrate
The substrate source pad hole 69 of front passivation layer 67, the substrate source pad hole 69 is corresponding with substrate source metal layer 70, i.e.,
Substrate source metal layer 70 can be drawn using substrate source pad hole 69 and obtain the source electrode of power semiconductor, such as Figure 21
It is shown.When groove wide with terminal in terminal protection area, the structure type specifically formed is as shown in figure 22.
Step 14 carries out required back process at the back side of above-mentioned semiconductor substrate 58, to obtain required substrate back
Face structure.
Specifically, it before the back side of semiconductor substrate 58 carries out back process, needs to above-mentioned the 5th photoresist of substrate
Layer 65 is removed.According to the type of power semiconductor, corresponding back process is carried out, according to the class of substrate back structure
The getable power semiconductor of type is MOSFET element or IGBT device, specially known to those skilled in the art.Tool
The process of body back process, which can according to need, to be selected, and specially known to those skilled in the art, details are not described herein again.
As shown in the above description, settable terminal isolated groove 37 and end in the terminal protection area of semiconductor substrate 38
Tapering gutter slot 71, is arranged terminal isolated groove insulating oxide 45 in terminal isolated groove 37 and terminal isolated groove is conductive
The wide groove conductive polycrystalline silicon 73 of terminal, the wide channel insulation gate oxide 74 of terminal is arranged simultaneously in the wide groove 71 of terminal in polysilicon 46
Fill substrate insulating medium layer 58；It, can be in substrate cellular when carrying out p type impurity ion implanting using the second photoresist layer of substrate 51
The two sides of groove 35 obtain substrate p-type base area 54, and are served as a contrast in the two sides and terminal protection area of cellular edge groove 36
The area DiPXing Ti 52, the area substrate PXing Ti 52 in terminal protection area and terminal isolated groove 37 cooperate and/or with the wide groove 37 of terminal
Cooperation can form required terminal protection area, and obtain not needing mask when the substrate area 52 PXing Ti, compared with the prior art,
Trench-type power semiconductor device is enabled, less with one piece of mask, to effectively reduce power semiconductor in Facad structure preparation
The preparation cost of device.
Using the second photoresist layer of substrate 51 N-type impurity ion implanting, p-type can be carried out to the active area of semiconductor substrate 38
Foreign ion can obtain substrate N+ source region 54 and substrate p-type base after removal the second photoresist layer of substrate 51 and annealing activation
Area 53 can be reduced using mask in the case where guaranteeing substrate p-type 53 doping concentration of base area, further reduce the cost.It utilizes
Substrate p-type base area 53 in active area, is able to achieve and the doping concentration of p-type in active area is adjusted, and ensure that prepared obtain
To the breakdown characteristics of power semiconductor termination environment and the on state characteristic of active area, entire technical process and prior art are simultaneous
Hold, securely and reliably.
It can be simultaneously between substrate cellular groove 35, cellular edge groove 36, terminal isolated groove 37 and the wide groove 71 of terminal
It is formed, the width of the wide groove 71 of cellular edge groove 36, terminal is greater than the width of substrate cellular groove 35, terminal isolated groove 37
Degree, so that in technical process groove injection location hole 49 in edge can be obtained in cellular edge groove 36, in the wide groove of terminal
The wide groove injection location hole of terminal is obtained in 71 utilizes edge groove when injecting p-type foreign ion obtains substrate P-type layer 47
Injection location hole 49 can obtain cellular edge groove P-doped zone 48 immediately below the slot bottom of cellular edge groove 36, utilize end
Tapering gutter slot injection location hole can obtain the wide trench P-type doped region 72 of terminal immediately below wide 71 slot bottom of groove of terminal, utilize
Substrate insulating medium layer 58 in cellular edge groove P-doped zone 48 and cellular edge groove 36 cooperates, and cellular can be improved
The breakdown voltage of edge groove 36 prevents from puncturing at cellular edge groove 36 so that breakdown occurs in active area, improves
The UIS ability of semiconductor power device.In addition, utilizing the wide trench P-type doped region 72 of terminal and the substrate in the wide groove 71 of terminal
Insulating medium layer 58 cooperates, and the breakdown voltage at the wide groove 71 of terminal can be improved, prevent electric field from expanding to semiconductor substrate 58
Terminal protection area edge, further increase the safety and reliability of power semiconductor.
Claims (10)
1. a kind of power semiconductor of low cost and high reliability, including the semiconductor substrate with the first conduction type, In
Active area is arranged in the center of the semiconductor substrate, and terminal protection area, the active area is arranged in the outer ring of the active area
Interior cellular uses groove structure；It is characterized in that:
It include substrate cellular groove and cellular edge groove, institute in active area on the section of the power semiconductor
State the engaging portion of cellular edge groove adjacent active regions and terminal protection area in semiconductor substrate, the width of cellular edge groove
Greater than the width of substrate cellular groove；
At cellular edge, cellular edge groove the second conduction type doped region, the cellular edge is arranged in the underface of groove slot bottom
Groove the second conduction type doped region is contacted with the slot bottom of cellular edge groove, in the two sides of substrate cellular groove setting substrate the
Two conduction type base regions, the second conduction type base region of substrate are contacted with the lateral wall of respective substrate cellular groove；At cellular edge
The second conductivity type body region of substrate, the lateral wall of the second conductivity type body region of substrate and cellular edge groove is arranged in the two sides of groove
Contact, the doping concentration of second conduction type base region of substrate are greater than the doping concentration of the second conductivity type body region of substrate；In
The first conduction type of substrate source region, the first conduction type source region and substrate cellular are set in the second conduction type base region of substrate
The lateral wall of groove contacts；
Substrate cellular conductive polycrystalline silicon is filled in substrate cellular groove, the substrate cellular conductive polycrystalline silicon is by being grown on
The side wall of substrate cellular insulated gate oxide layer on substrate cellular trenched side-wall and bottom wall and place substrate cellular groove and
Bottom wall is dielectrically separated from；Edge groove conductive polycrystalline silicon and substrate insulating medium layer are filled in cellular edge groove, it is described
Substrate insulating medium layer is also covered on the front of semiconductor substrate, and edge groove conductive polycrystalline silicon is located in cellular edge groove
The outer ring of substrate insulating medium layer in cellular edge groove, edge groove conductive polycrystalline silicon pass through edge channel insulation gate oxidation
The side wall and bottom wall of layer and cellular edge groove are dielectrically separated from；
Substrate source metal layer is set in semiconductor substrate positive top, the substrate source metal layer is supported on substrate insulation
On dielectric layer, substrate source metal layer and the second conduction type base region of substrate, substrate the first conduction type source region and cellular side
The second conductivity type body region of substrate Ohmic contact of edge groove two sides.
2. the power semiconductor of low cost and high reliability according to claim 1, it is characterized in that: in the power half
On the section of conductor device, terminal protection area uses groove structure, and terminal protection area includes terminal isolated groove, the terminal every
The second conductivity type body region of substrate is arranged in two sides from groove, and second conductivity type body region of substrate is located at terminal isolated groove
Slot bottom above, and the second conductivity type body region of substrate is contacted with the lateral wall of terminal isolated groove, in terminal isolated groove
Filled with terminal isolated groove conductive polycrystalline silicon, the terminal isolated groove conductive polycrystalline silicon is by being grown on terminal isolated groove
The side wall and bottom wall of the terminal isolated groove of interior terminal isolated groove insulation gate oxide and place are dielectrically separated from, and substrate is exhausted
Edge dielectric layer is covered on the notch of terminal isolated groove.
3. the power semiconductor of low cost and high reliability according to claim 2, it is characterized in that: in terminal protection area
It inside further include the wide groove of terminal, the width of the wide groove of terminal is greater than the width of terminal isolated groove and substrate cellular groove
Degree；In the underface of the wide groove slot bottom of terminal, wide the second conduction type of the groove doped region of terminal, the wide groove of terminal the are set
Two conduction type doped regions are contacted with the slot bottom of the wide groove of terminal, and there is the two sides above the wide groove slot bottom of terminal substrate second to lead
Electric type body region；The wide groove conductive polycrystalline silicon of terminal and substrate insulating medium layer, whole tapering gutter are filled in the wide groove of terminal
Slot conductive polycrystalline silicon is located at the outer ring of the substrate insulating medium layer in the wide groove of the terminal, whole tapering gutter in the wide groove of terminal
Slot conductive polycrystalline silicon is dielectrically separated from by the wide channel insulation gate oxide of terminal and the side wall and bottom wall of the wide groove of terminal；
The wide groove of terminal and terminal isolated groove, substrate cellular groove and cellular edge groove pass through same processing step
It obtains, the wide groove of terminal has in semiconductor substrate with terminal isolated groove, substrate cellular groove and cellular edge groove
Identical depth, the wide groove of terminal are located between terminal isolated groove and cellular edge groove.
4. the power semiconductor of low cost and high reliability according to claim 1 or 2 or 3, it is characterized in that: described
Substrate face passivation layer is set on substrate source metal layer, substrate source pad hole is set in the substrate face passivation layer,
Substrate source pad hole Through-substrate front passivation layer, can be by substrate source metal layer and lining by substrate face passivation layer
The isolation of bottom terminal metal.
5. a kind of preparation method of the power semiconductor of low cost and high reliability, characterized in that the preparation method includes
Following steps:
Step 1 provides the semiconductor substrate with the first conduction type, and carries out etching groove to the semiconductor substrate, with
Obtain required substrate trenches, the substrate trenches include the substrate cellular groove positioned at active area, cellular edge groove and
The width of terminal isolated groove positioned at termination environment, cellular edge groove is greater than substrate cellular groove, cellular edge groove
The adjacent terminals protection zone in active area；
Step 2 carries out oxide layer growth and polysilicon filling in the front of above-mentioned semiconductor substrate, to obtain liner oxidation layer
And substrate polysilicon body, the liner oxidation layer are grown in the front of semiconductor substrate and the side wall of substrate trenches and bottom
Wall, substrate polysilicon body are filled in substrate trenches, and substrate polysilicon body also covers the positive liner oxidation of semiconductor substrate
On layer；
Step 3 carries out anisotropy time quarter to above-mentioned substrate polysilicon body, and performs etching to liner oxidation layer, to obtain
Substrate cellular insulated gate oxide layer and substrate cellular conductive polycrystalline silicon in substrate cellular groove, in cellular edge groove
Inside obtain edge channel insulation gate oxide, edge groove conductive polycrystalline silicon and the edge positioned at cellular marginal ditch groove center area
Groove injects location hole, and terminal isolated groove insulation gate oxide is obtained in terminal isolated groove and terminal isolated groove is led
Electric polysilicon, injecting location hole by edge groove can make the slot bottom of cellular edge groove exposed；
Step 4, above-mentioned semiconductor substrate front the second conductive type impurity ion injection and annealing, to obtain traversing half
Second conductive type layer of substrate on conductor substrate top, second conductive type layer of substrate are located at the upper of substrate trenches slot bottom
Side, and cellular edge groove the second conduction type doped region, the cellular marginal ditch are obtained immediately below cellular edge groove
Slot the second conduction type doped region is contacted with the slot bottom of cellular edge groove；
Step 5, the front surface coated photoresist layer in above-mentioned semiconductor substrate, and using the second mask plate of substrate to photoresist layer into
Row photoetching, to obtain the second photoresist layer of substrate, second photoresist layer of substrate covers the terminal protection area of semiconductor substrate,
The second photoresist layer of substrate, which is also filled up, to be injected positioning hole in edge groove and covers the notch of cellular edge groove；
Step 6 blocks semiconductor substrate using the second photoresist layer of substrate, and it is conductive to carry out first to above-mentioned semiconductor substrate
Required annealing is carried out after type dopant ion, the injection of the second conductive type impurity ion and removal the second photoresist layer of substrate
Technique, to obtain the second conduction type base region of substrate in the active area of semiconductor substrate and be located at second conduction of substrate
Substrate the first conduction type source region in type base area, and substrate the second conductive type layer shape below the second photoresist layer of substrate
At the second conductivity type body region of substrate, the doping concentration of the second conduction type base region of substrate is greater than the second conductivity type body region of substrate
Doping concentration, the outside of the second conduction type base region of substrate, substrate the first conduction type source region and respective substrate cellular groove
Wall contact；
Step 7 carries out dielectric layer deposition on the front of above-mentioned semiconductor substrate, to obtain the covering positive lining of semiconductor substrate
Bottom insulating medium layer, the substrate insulating medium layer, which is also filled up, injects positioning hole in edge groove；
Step 8, the coated substrate third photoresist layer on above-mentioned substrate insulating medium layer, and using substrate third mask to lining
Bottom third photoresist layer carries out photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer；
Step 9 carves substrate insulating medium layer using substrate third photoresist layer and substrate third photoresist layer window
Erosion, the substrate insulation to obtain the substrate insulating medium layer contact hole of Through-substrate insulating medium layer, on the outside of substrate cellular groove
Dielectric layer contact hole also the first conduction type of Through-substrate source region；
Step 10, the above-mentioned substrate third photoresist layer of removal, and metal layer shallow lake is carried out in the upper front of above-mentioned semiconductor substrate
Product, with the substrate metal layer being supported on substrate insulating medium layer, the substrate metal layer, which also fills up to insulate in substrate, to be situated between
In matter layer contact hole；The 4th photoresist layer of coated substrate on substrate metal layer, and using the 4th mask of substrate to substrate the
Four photoresist layers carry out photoetching, to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate；
Step 11 performs etching substrate metal layer using the 4th photoresist layer of substrate and the 4th photoresist layer window of substrate,
Separate hole to obtain the substrate metal of Through-substrate metal layer, substrate metal layer separates hole by substrate metal and obtains on active area
The substrate source metal layer and the substrate terminal metal layer above terminal protection area of side, the substrate source metal layer
It is conductive with the first conduction type of substrate source region, the second conduction type base region of substrate and the substrate of cellular edge groove two sides second
Type body region Ohmic contact；
Step 12, above-mentioned the 4th photoresist layer of substrate of removal, and it is passivated layer deposit in the front of above-mentioned semiconductor substrate, with
Substrate face passivation layer is obtained, the substrate face passivation layer is filled in substrate metal and separates in hole, and substrate face passivation layer
Also it is covered on substrate source metal layer, on substrate terminal metal layer；
Step 13, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, and utilize the 5th mask pair of substrate
The 5th photoresist layer of substrate carries out photoetching, to obtain the 5th photoresist layer window of substrate of the 5th photoresist layer of Through-substrate, benefit
Substrate face passivation layer is performed etching with the 5th photoresist layer of substrate and the 5th photoresist layer window of substrate, to be penetrated through
The substrate source pad hole of substrate face passivation layer, the substrate source pad hole are corresponding with substrate source metal layer；
Step 14 carries out required back process at the back side of above-mentioned semiconductor substrate, to obtain required substrate back structure.
6. the preparation method of the power semiconductor of the low cost and high reliability according to shown in claim 5, characterized in that In
It further include the wide groove of terminal in terminal protection area, the width of the wide groove of terminal is greater than terminal isolated groove and substrate cellular
The width of groove；In the underface of the wide groove slot bottom of terminal, wide the second conduction type of the groove doped region of terminal, the terminal are set
Wide groove the second conduction type doped region is contacted with the slot bottom of the wide groove of terminal, and the two sides above the wide groove slot bottom of terminal have lining
The second conductivity type body region of bottom；The wide groove conductive polycrystalline silicon of terminal and substrate insulating medium layer are filled in the wide groove of terminal,
The wide groove conductive polycrystalline silicon of terminal is located at the outer ring of the substrate insulating medium layer in the wide groove of the terminal in the wide groove of terminal,
The wide groove conductive polycrystalline silicon of terminal is insulated by the side wall and bottom wall of the wide channel insulation gate oxide of terminal and the wide groove of terminal
Isolation；
The wide groove of terminal and terminal isolated groove, substrate cellular groove and cellular edge groove pass through same processing step
It obtains, the wide groove of terminal has in semiconductor substrate with terminal isolated groove, substrate cellular groove and cellular edge groove
Identical depth, the wide groove of terminal are located between terminal isolated groove and cellular edge groove.
7. the preparation method of the power semiconductor of the low cost and high reliability according to shown in claim 5, characterized in that step
In rapid 1, in the first photoresist layer of front surface coated substrate of the semiconductor substrate, using the first mask of substrate to substrate first
Photoresist layer carries out photoetching, to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate, utilizes substrate the
After one photoresist layer and substrate the first photoresist layer window etch the front of semiconductor substrate, required substrate ditch can be obtained
Slot.
8. the preparation method of the power semiconductor of the low cost and high reliability according to shown in claim 5, characterized in that step
In rapid 6, the injection of the first conductive type impurity ion is first carried out, reinjects the injection of the second conductive type impurity ion, or
The injection for first carrying out the second conductive type impurity ion reinjects the injection of the first conductive type impurity ion, or simultaneously into
It is injected while the first conductive type impurity of row ion, the second conductive type impurity ion.
9. the preparation method of the power semiconductor of the low cost and high reliability according to shown in claim 5, characterized in that institute
The material for stating semiconductor substrate includes silicon.
10. the preparation method of the power semiconductor of the low cost and high reliability according to shown in claim 6, characterized in that
Wide groove the second conduction type doped region of terminal and cellular edge groove the second conduction type doped region are same technique step
Rapid layer.
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| US20040222458A1 (en) * | 2003-05-06 | 2004-11-11 | Mosel Vitelic, Inc. | Termination structure for trench DMOS device and method of making the same |
| CN103180958A (en) * | 2010-10-21 | 2013-06-26 | 威世通用半导体公司 | Trench dmos device with improved termination structure for high voltage applications |
| CN104637994A (en) * | 2013-11-13 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and manufacturing method |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
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Effective date of registration: 20220913 Address after: Room 1106-3, No. 62, Suyuan Avenue, Jiangning Development Zone, Nanjing City, Jiangsu Province, 211100 (Jiangning Development Zone) Applicant after: Jiangsu Chip Long March Microelectronics Group Co.,Ltd. Applicant after: Nanjing Xinchangzheng Technology Co.,Ltd. Address before: 211100 block A2, Jiulonghu international enterprise headquarters park, 19 Suyuan Avenue, Nanjing City, Jiangsu Province (Jiangning Development Zone) Applicant before: Nanjing Xinchangzheng Technology Co.,Ltd. |
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