CN114582717A - Preparation method of semiconductor device and shielded gate trench device - Google Patents

Preparation method of semiconductor device and shielded gate trench device Download PDF

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Publication number
CN114582717A
CN114582717A CN202011377002.4A CN202011377002A CN114582717A CN 114582717 A CN114582717 A CN 114582717A CN 202011377002 A CN202011377002 A CN 202011377002A CN 114582717 A CN114582717 A CN 114582717A
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groove
layer
dielectric layer
polycrystalline silicon
polysilicon
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冯冰
张建栋
贺腾飞
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202011377002.4A priority Critical patent/CN114582717A/en
Priority to PCT/CN2021/110551 priority patent/WO2022110889A1/en
Publication of CN114582717A publication Critical patent/CN114582717A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Abstract

The invention relates to a preparation method of a semiconductor device and a shielding grid groove device, wherein the method comprises the following steps: obtaining a substrate with a groove, wherein a first dielectric layer is formed on the inner wall of the groove, a polycrystalline silicon structure is formed in a space where the first dielectric layer is not formed in the groove, and the top of the polycrystalline silicon structure is lower than the surface of the substrate; removing the part of the first dielectric layer higher than the polycrystalline silicon structure by wet etching; the top of the polysilicon structure is bombarded by plasma, so that the top of the polysilicon structure is partially removed; thermally growing a first oxide layer on the inner wall of the groove and the surface of the polycrystalline silicon structure; and filling a second dielectric layer into the groove, wherein the second dielectric layer fills the groove. According to the method, the edges of the polycrystalline silicon structure are bombarded by the plasmas, so that the width of the top of the polycrystalline silicon structure is reduced, the purpose of avoiding small holes from being formed in two sides of the top of the polycrystalline silicon structure is achieved, and the purpose of eliminating gate-source short circuit caused by filling abnormity is achieved.

Description

Preparation method of semiconductor device and shielding gate groove device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a device with a shielded gate trench.
Background
The Shield Gate Trench (SGT) product is susceptible to forming small holes on both sides of the top of the Shield Gate polysilicon. When a polysilicon gate is formed in the deep trench subsequently, the polysilicon gate easily enters the small hole, so that a gate source short circuit is caused. And because the protruding structure at the top of the shielding grid is easy to form sharp charge concentration, breakdown and electric leakage can occur when the shielding grid and the grid work.
Disclosure of Invention
In view of the above, there is a need for a method of fabricating a semiconductor device and a shielded gate trench device.
In order to achieve the above object, in one aspect, the present invention provides a method for manufacturing a semiconductor device, including:
obtaining a substrate with a groove, wherein a first medium layer is formed on the inner wall of the groove, a polycrystalline silicon structure is formed in a space where the first medium layer is not formed in the groove, and the top of the polycrystalline silicon structure is lower than the surface of the substrate;
removing the part of the first dielectric layer higher than the polycrystalline silicon structure by wet etching;
the top of the polysilicon structure is bombarded by plasma, so that the top of the polysilicon structure is partially removed;
thermally growing a first oxide layer on the inner wall of the groove and the surface of the polycrystalline silicon structure;
and filling a second dielectric layer into the groove, wherein the second dielectric layer fills the groove.
In one embodiment, the first dielectric layer is an insulating oxide layer, the substrate with the trench is obtained, the first dielectric layer is formed on the inner wall of the trench, a polysilicon structure is formed in a space in the trench where the first dielectric layer is not formed, and the step of making the top of the polysilicon structure lower than the surface of the substrate includes:
etching the substrate with the mask layer, and forming a groove at the position of the substrate not covered by the mask layer;
thermally growing the insulating oxide layer on the inner wall of the groove to form the insulating oxide layer;
the step of bombarding the edge of the polysilicon structure by the plasma comprises:
and bombarding the edge of the mask layer positioned at the top of the groove to partially remove the edge of the mask layer.
In one embodiment, the mask layer is a silicon nitride layer.
In one embodiment, the step of filling the second dielectric layer into the trench includes: and forming the second dielectric layer by a high-density plasma chemical vapor deposition process.
In one embodiment, the step of plasma bombarding the edge of the polysilicon structure comprises: and forming plasma by adopting a high-density plasma chemical vapor deposition machine.
In one embodiment, the process gas of the high-density plasma chemical vapor deposition machine comprises helium and oxygen.
In one embodiment, the volume flow ratio of helium to oxygen in the process gas is not less than 1.
In one embodiment, the plasma bombards the edge of the polysilicon structure, so that the edge of the polysilicon structure is partially removed, after the two sides of the top of the polysilicon structure are removed, a polysilicon descending slope structure extending to the top of the first dielectric layer is formed, and an included angle between the slope structure and the top of the first dielectric layer is an obtuse angle.
In one embodiment, bombarding the edge of the mask layer at the top of the trench, so that the edge of the mask layer is partially removed, includes: and removing the part of the mask layer protruding out of the top of the inner wall of the groove, so that the mask layer does not protrude out of the top of the inner wall of the groove any more after removal.
In one embodiment, the semiconductor device is a shielded gate trench device and the polysilicon structure is used to form a shielded gate structure.
The present invention also provides a shielded gate trench device, comprising:
a substrate provided with a groove;
the shielding gate dielectric layer is positioned at the bottom and the inner wall of the groove;
and the shielding grid polycrystalline silicon layer is arranged in the groove, and the two sides of the top of the shielding polycrystalline silicon layer are slope structures extending downwards.
In one embodiment, an included angle between the slope structure and the top of the shielding gate dielectric layer is an obtuse angle.
According to the preparation method of the semiconductor device, the sharp angle exposed at the top edge of the polycrystalline silicon structure due to wet etching isotropy can be improved by bombarding the edge of the polycrystalline silicon structure by the plasma. Specifically, in the wet etching step of the method, in order to completely remove the first dielectric layer on the inner wall of the trench, which is higher than the top of the polysilicon structure, the first dielectric layers on the two sides of the top of the polysilicon structure are removed, so that the edge of the top of the polysilicon structure is exposed; when the exposed polycrystalline silicon structure grows the first oxidation layer thermally, because the crystal orientation of the top of the polycrystalline silicon structure is different from the crystal orientations of the polycrystalline silicon structures at other positions, the growth speed of the first oxidation layer at the edge of the top of the polycrystalline silicon structure is higher, the first oxidation layers at the top of the polycrystalline silicon structure and the edge of the top of the polycrystalline silicon structure are thicker, a structure with convex sides at two sides of the top is formed, and the convex structure ensures that a space below a second medium layer is difficult to fill when the second medium layer is filled in a groove, so that a small hole is formed; and the plasma bombardment can remove part of the polycrystalline silicon at the edge, so that the width of the top of the polycrystalline silicon structure is reduced, and the first oxide layer grown thermally cannot form the convex structure, thereby avoiding influencing the filling capability of the second dielectric layer during filling, achieving the purpose of avoiding forming small holes at two sides of the top of the polycrystalline silicon structure, and further achieving the purpose of eliminating gate-source short circuit caused by abnormal filling.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a Scanning Electron Microscope (SEM) photograph of cracks under a silicon nitride mask layer and small holes on two sides of the top of a shielded gate polysilicon in an exemplary shielded gate trench device after silicon dioxide is filled in the trench;
FIG. 2 is a schematic flow chart illustrating a method of fabricating a semiconductor device according to one embodiment;
FIG. 3 is a flowchart illustrating step S102 according to an embodiment;
fig. 4 is a schematic cross-sectional structure view of a substrate formed with a mask layer in a manufacturing method of a semiconductor device provided in an embodiment;
fig. 5 is a schematic cross-sectional view of the semiconductor device after forming trenches corresponding to fig. 4;
FIG. 6 is a schematic cross-sectional view of a semiconductor device after forming a polysilicon structure in accordance with one embodiment of the present invention shown in FIG. 5;
FIG. 7 is a schematic cross-sectional view of the semiconductor device of FIG. 6 after removing portions of the first dielectric layer above the polysilicon structure;
FIG. 8 is a schematic cross-sectional view of the semiconductor device of FIG. 7 after plasma bombardment;
FIG. 9 is a schematic cross-sectional view of a semiconductor device after forming a second dielectric layer and a schematic cross-sectional view of a shielded gate trench device in one embodiment;
FIG. 10 is a schematic partial flow chart of an exemplary shielded gate trench device;
fig. 11 is a comparison graph of the shapes of the sem photographs of the cross-sectional structures of the semiconductor devices respectively manufactured by the manufacturing method of the present application and the conventional manufacturing method, and is also a comparison graph of the shapes of the sem photographs of the cross-sectional structures of the shielded gate trench devices.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Referring to fig. 10, in a process of manufacturing an exemplary Shielded Gate Trench (SGT) product, a shielded Gate oxide layer is formed on an inner wall of a deep trench, a shielded Gate polysilicon structure is formed in the deep trench, a top of the shielded Gate polysilicon structure is lower than a surface of a substrate, i.e., a top of the shielded Gate oxide layer, and then a portion of the shielded Gate oxide layer higher than the shielded Gate polysilicon structure is removed by a wet etching process. Because the wet etching has the characteristic of isotropy, in the process of completely removing the part of the shielding gate oxide layer formed on the inner wall of the deep groove, which is higher than the shielding gate polysilicon structure, through the etching process, the shielding gate oxide layers on the two sides of the top of the shielding gate polysilicon structure are etched, so that the edge of the top of the shielding gate polysilicon structure is exposed, two small grooves between the side wall of the shielding gate polysilicon structure and the side wall of the deep groove are formed inside the deep groove, and the depth of each small groove is deepened along with the increase of the thickness of the shielding gate oxide layer.
When a thin Sacrificial Oxide layer (Sacrificial Oxide) is grown in the deep trench by a thermal oxidation process, because the top of the polysilicon structure of the shielding gate has different crystal orientations from the polysilicon structures at other positions, the rates of oxidizing the polysilicon to form the Sacrificial Oxide layer are different, after the growth of the Sacrificial Oxide is completed, the small trenches at two sides of the top of the polysilicon structure of the shielding gate can be changed into concave structures with narrow top and wide bottom (namely, two sides of the top of the polysilicon structure of the shielding gate form convex structures), when the polysilicon gate Oxide layer is filled in the deep trench by a high-density plasma chemical vapor deposition process, the positions of the concave structures in the small trenches at two sides of the top of the polysilicon structure of the shielding gate are difficult to fill, so that small holes (as shown in figure 1) are formed in the small trenches, the quality of the polysilicon gate Oxide layer filled in the small trenches is poor, gate source leakage is easy to cause, and when the polysilicon gate is formed in the deep trench subsequently, the polysilicon gate easily enters the small hole, causing a gate-source short circuit.
Secondly, after the groove is formed, a silicon nitride mask layer used for forming the groove covers the surface of the substrate, when a shielding gate oxide layer grows in the groove in a dry oxygen mode, silicon below the silicon nitride mask layer and located on the side wall of the groove can be consumed, and after the part, higher than the shielding gate polycrystalline silicon structure, of the shielding gate oxide layer is removed through a wet etching process, the silicon nitride mask layer protrudes relative to the groove, namely the part, close to the groove, of the silicon nitride mask layer is suspended above the groove. When the polysilicon gate oxide layer for filling the trench is formed by plasma chemical vapor deposition in the subsequent process, because the plasma at the edge of the wafer has an inclined direction, a small crack (as shown in fig. 1) can be formed below the protruding position of the silicon nitride mask layer, so that the etching rates in the trench are different when the polysilicon gate oxide layer is etched by a wet process in the subsequent process, the thickness of the polysilicon gate oxide layer between the gate and the source has high-low difference, and the problem of breakdown and electric leakage easily occurs.
In view of the above problems, the present application provides a method for manufacturing a novel semiconductor device and a novel shielded gate trench device.
Referring to fig. 2, a flow chart of a method for manufacturing a semiconductor device according to an embodiment is shown.
In one embodiment, as shown in fig. 2, there is provided a method of manufacturing a semiconductor device, the method comprising the steps of:
and S102, obtaining the substrate with the groove.
The method comprises the steps of obtaining a substrate with a groove, forming a first medium layer on the inner wall of the groove, forming a polycrystalline silicon structure in a space where the first medium layer is not formed in the groove, and enabling the top of the polycrystalline silicon structure to be lower than the surface of the substrate.
The substrate may be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, or the like, and the trench may be opened in a single crystal silicon epitaxial layer on the surface of the substrate, which will be described below with the substrate as the silicon substrate.
And S104, removing the part of the first dielectric layer higher than the polycrystalline silicon structure by wet etching.
And removing the part of the first dielectric layer higher than the polysilicon structure in the groove by a wet etching process to obtain the shielding gate dielectric layer formed by the residual first dielectric layer.
And S106, bombarding the top of the polycrystalline silicon structure by using plasma, so that the top of the polycrystalline silicon structure is partially removed.
And removing the two sides of the top of the polycrystalline silicon structure formed in the groove through plasma bombardment, so that the top of the polycrystalline silicon structure is partially removed, the width of the top of the polycrystalline silicon structure is narrowed, and the appearance of a sharp corner at the top of the polycrystalline silicon structure becomes gentle. When the first oxide layer (i.e., the sacrificial oxide layer) is thermally grown in the trench in step S108, the growth speed of the first oxide layer at the top edge of the polysilicon structure is faster due to the different crystal orientations of the polysilicon at the top of the polysilicon structure and other positions, and the first oxide layer at the top of the polysilicon structure and the top edge thereof is thicker, thereby forming a structure in which both sides of the top protrude outward.
And S108, thermally growing a first oxidation layer on the inner wall of the groove and the surface of the polycrystalline silicon structure.
In one embodiment, a furnace tube is used to grow a thin sacrificial oxide layer.
And S110, filling a second dielectric layer into the groove, wherein the groove is filled with the second dielectric layer.
In one embodiment, the first dielectric layer is an insulating oxide layer, and step S102 includes:
the first step is to etch the substrate with the mask layer, and form a groove at the position where the mask layer is not covered by the substrate. And secondly, forming a first dielectric layer on the inner wall of the groove by a chemical vapor deposition process. And thirdly, forming a polycrystalline silicon structure in the space where the first dielectric layer is not formed in the groove, wherein the top of the polycrystalline silicon structure is lower than the surface of the substrate. The third step may be performed by a conventional process for forming a structure with a top lower than the surface of the substrate, which is not described herein. Fig. 3 is a flowchart illustrating step S102 according to an embodiment. In this embodiment, the first dielectric layer is an insulating oxide layer, and step S102 includes:
s202, etching the substrate with the mask layer, and forming a groove at a position where the mask layer is not covered by the substrate.
Fig. 4 to 9 illustrate a method for manufacturing a semiconductor device according to the present application, by way of example, in the case of manufacturing a shielded gate trench device. Referring to fig. 4, in one embodiment, a silicon oxide film 103 is formed on a substrate 102, and a mask layer is located on the silicon oxide film 103.
Referring to fig. 5, step S202 may specifically include: in a first step, a mask layer 104 is formed on the substrate 102, and the mask layer 104 exposes a portion of the silicon oxide film 103 (and a portion of the substrate 102). And secondly, performing an etching process to remove the silicon oxide film 103 which is not covered by the mask layer 104 on the substrate 102 and a part of the substrate 102 below the silicon oxide film 103, forming a groove 106 in the substrate 102, and obtaining an oxide layer 202 formed by the residual silicon oxide film 103.
In one embodiment, the mask layer 104 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbide layer, a silicon carbonitride layer, and a silicon oxycarbonitride layer. The mask layer 104 is illustratively a silicon nitride layer.
And S204, thermally growing the insulating oxide layer on the inner wall of the groove.
As shown in fig. 6, the silicon on the inner wall of the trench 106 is oxidized by a thermal oxidation process to form an insulating oxide layer 108 on the inner wall of the trench 106. For example, the substrate 102 is placed in a furnace tube and oxygen is introduced into the furnace tube for dry oxidation to form the insulating oxide layer 108; or putting the substrate 102 into a furnace tube, introducing oxygen and water vapor, and performing wet oxygen oxidation to form an insulating oxide layer 108; or putting the substrate 102 into a furnace tube, and introducing oxygen and hydrogen to perform oxyhydrogen synthesis oxidation to form an insulating oxide layer 108; or the substrate 102 is placed in a furnace tube and oxygen and chlorine-containing gas are introduced into the furnace tube for chlorine doping and oxidation to form the insulating oxide layer 108.
After forming the insulating oxide layer 108 on the inner wall of the trench 106, a polysilicon structure 110 is formed in the trench 106, and the top of the polysilicon structure 110 is lower than the surface of the substrate 102. In practical applications, the polysilicon structure 110 may be formed by a conventional process for forming a structure with a top lower than the surface of the substrate, for example, etching back after depositing polysilicon, which is not described herein.
As shown in fig. 7, after the polysilicon structure 110 is formed, a portion of the insulating oxide layer 108 higher than the polysilicon structure 110 is removed by wet etching, so as to obtain a shield gate dielectric layer 204 formed by the remaining insulating oxide layer 108. Specifically, a wet etching process is performed to remove the insulating oxide layer 108 located between the top of the opening of the trench 106 and the top of the polysilicon structure 110, and simultaneously, the portion of the oxide layer 202 located above the insulating oxide layer 108 is removed, so as to obtain the shield gate dielectric layer 204 formed by the remaining insulating oxide layer 108. Because the wet etching process has an isotropic characteristic, and the ratio of the depth to the width of the insulating oxide layer 108 to be removed on the sidewall of the trench 106 is greater than 1, after the wet etching process, the insulating oxide layers 108 on both sides of the top of the polysilicon structure 110 are removed, so that the top of the polysilicon structure 110 is higher than the top of the shield gate dielectric layer 204.
After the shielding gate dielectric layer 204 is obtained, plasma bombardment is performed to partially remove the top of the polysilicon structure 110, so that the sharp corner appearance of the top of the polysilicon structure 110 becomes smooth even if the top of the polysilicon structure 110 becomes narrow. The formation of a structure with two convex sides at the top due to the faster growth speed of the first oxide layer at the top edge of the polysilicon structure 110 and the thicker first oxide layer at the top of the polysilicon structure 110 and the top edge thereof can be avoided when the first oxide layer (i.e., the sacrificial oxide layer) is thermally grown in the trench, because the polysilicon crystal orientations at the top of the polysilicon structure 110 and other positions are different.
As shown in fig. 8, the plasma bombards the edge of the polysilicon structure 110, so that both sides of the top of the polysilicon structure 110 are removed, a descending slope 208 extending toward the top 206 of the shield gate dielectric layer 204 is formed, and an included angle between the slope structure 208 and the top of the shield gate dielectric layer 204 is an obtuse angle, so as to obtain a shield gate polysilicon layer 210 formed by the remaining polysilicon structure 110. Therefore, when the second dielectric layer is filled subsequently (step S110), the two sides of the polysilicon structure 110 can be filled to avoid the occurrence of the small hole, so that the problem of gate-source short circuit caused by the fact that the polysilicon gate enters the small hole when the polysilicon gate is formed in the trench 106 is avoided.
Referring to fig. 6 and 7, dry oxygen growing the insulating oxide layer 108 within the trench 106 consumes silicon below the mask layer 104 located at the sidewalls of the trench 106. Thus, after removing the portion of the insulating oxide layer 108 above the polysilicon structure 110, the mask layer 104 protrudes relative to the polysilicon structure 106. In one embodiment, the plasma of step S106 may also bombard the edge of the mask layer 104 on the top of the trench 106, such that the edge of the mask layer 104 is partially removed. At this time, the width of the top of the mask layer 104 is narrowed, so that when a polysilicon gate oxide layer filling the trench 106 is formed by plasma chemical vapor deposition, a crack is not formed below the protruding position of the mask layer 104 due to directionality of plasma at the edge of the wafer. The cracks can cause different corrosion rates in the groove 106 when the polysilicon gate oxide layer is corroded by a subsequent wet method, so that the thickness of the polysilicon gate oxide layer between the gate source electrodes has different heights, and the problem of breakdown and electric leakage is easy to occur. The oxide layer 202 under the mask layer 104 may not be damaged when the edges of the mask layer 104 are removed by plasma bombardment in an actual manufacturing process.
In one embodiment, bombarding the edge of the mask layer 104 at the top of the trench 106, such that the edge of the mask layer 104 is partially removed, comprises: the portions of masking layer 104 that protrude above the tops of the inner walls of trench 106 are removed so that the bottom edge of masking layer 104 is aligned with the top of trench 102. I.e., the portion of the mask layer 104 that overhangs the trench 106 is removed.
In one embodiment, the step of plasma bombarding the edge of the polysilicon structure 110 comprises: a High Density Plasma Chemical Vapor Deposition (HDPCVD) tool is used to form a plasma and bombard the edges of the polysilicon structure 110.
In one embodiment, the process gas for HDPCVD comprises helium and oxygen.
In one embodiment, the volume flow ratio of helium to oxygen in the HDPCVD process gas is not less than 1. Furthermore, the flow rate of the helium gas is more than or equal to 90sccm and less than or equal to 110sccm, and the flow rate of the oxygen gas is more than or equal to 90sccm and less than or equal to 110 sccm. The TOP radio frequency power (RF-TOP) is between 4700W and 5000W, such as 4850W; the bottom radio frequency power (RF-BIAS) is between 2600W and 3100W, such as 2850W; the SIDE radio frequency power (RF-SIDE) is between 800W and 1000W, such as 900W, and the reaction pressure is between 3mTorr and 5mTorr, such as 3mTorr, both inclusive. In practical application, parameters of the high-density plasma etching process are adjusted according to the thickness of the first dielectric layer and the characteristic size of the deep groove, and within a certain range, the larger the thickness of the first dielectric layer is, the larger the characteristic size of the deep groove is, the higher the speed of the high-density plasma etching process is, and the longer the time is.
Referring to fig. 9, in one embodiment, step S110 includes: and forming a second dielectric layer by a high-density plasma chemical vapor deposition process.
Specifically, the second dielectric layer 112 filling the trench 106 is formed by a high density plasma chemical vapor deposition process. Typically, the high density plasma chemical vapor deposition process is followed by a chemical mechanical polishing step.
In one embodiment, second dielectric layer 112 comprises a silicon oxide layer.
In one embodiment, the method for manufacturing a semiconductor device further includes: and etching the second dielectric layer 112 to obtain a gate oxide layer located above the shield gate polysilicon layer 210.
According to the preparation method of the semiconductor device, the sharp angle exposed at the top edge of the polycrystalline silicon structure due to wet etching isotropy can be improved by bombarding the edge of the polycrystalline silicon structure by the plasma. Specifically, in the wet etching step of the method, in order to completely remove the first dielectric layer on the inner wall of the trench, which is higher than the top of the polysilicon structure, the first dielectric layers on the two sides of the top of the polysilicon structure are removed, so that the edge of the top of the polysilicon structure is exposed; when the exposed polycrystalline silicon structure grows the first oxidation layer thermally, because the crystal orientation of the top of the polycrystalline silicon structure is different from the crystal orientations of the polycrystalline silicon structures at other positions, the growth speed of the first oxidation layer at the edge of the top of the polycrystalline silicon structure is higher, the first oxidation layers at the top of the polycrystalline silicon structure and at the edge of the top of the polycrystalline silicon structure are thicker, a structure with convex sides at two sides of the top is formed, and the convex structure enables the space below the second medium layer to be difficult to fill when the second medium layer is filled in the groove, so that a small hole is formed; and the plasma bombardment can remove part of the polycrystalline silicon at the edge, so that the width of the top of the polycrystalline silicon structure is reduced, and the first oxide layer grown thermally cannot form the convex structure, thereby avoiding influencing the filling capability of the second dielectric layer during filling, achieving the purpose of avoiding forming small holes at two sides of the top of the polycrystalline silicon structure, and further achieving the purpose of eliminating gate-source short circuit caused by abnormal filling.
It should be understood that, although the steps in the flowcharts of fig. 1 and 3 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in fig. 1 and 3 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
As shown in fig. 9, the present invention also provides a shielded gate trench device, comprising:
a substrate 102 provided with a trench 106;
a shield gate dielectric layer 204 located at the bottom and inner wall of the trench 106;
and the shielding gate polysilicon layer 210 is arranged in the trench 106, two sides of the top of the shielding gate polysilicon layer 210 are slope structures 208 extending downwards, and an included angle between the slope structures 208 and the top 206 of the shielding gate dielectric layer 204 is an obtuse angle.
In one embodiment, the shielded gate trench device further includes a gate oxide layer over the shielded gate polysilicon layer 210.
As shown in fig. 11, which is a comparison graph of the shapes of the scanning electron micrographs of the cross-sectional structures of the semiconductor device manufactured by the manufacturing method of the present application and the semiconductor device manufactured by the conventional manufacturing method, it can be seen from fig. 11 that the semiconductor device manufactured by the manufacturing method of the semiconductor device in the present application has a gentle shape of the sharp corner at the top of the shield gate polysilicon layer (the portion circled by the dotted line in the trench in the figure), no voids at both sides, no anomaly in filling, and no cracks at the trench opening (the portion circled by the dotted line at the trench opening position in the figure).
According to the shielding gate trench device, the shielding gate polycrystalline silicon layer is arranged in the trench and is made of polycrystalline silicon, the two sides of the top of the shielding gate polycrystalline silicon layer are slope structures extending downwards, and included angles between the slope structures and the top of the shielding gate dielectric layer are obtuse angles. The width of the top of the polycrystalline silicon structure can be reduced, so that the first oxide layer grown thermally cannot form the convex structure, the filling capacity of the second dielectric layer during filling can be prevented from being influenced, and the purpose of preventing small holes from being formed in two sides of the top of the polycrystalline silicon structure is achieved. The width of the top of the polycrystalline silicon structure is small, the convex structure with thermal growth can not be formed at the top of the polycrystalline silicon structure, the filling capacity when the polycrystalline silicon gate is filled can be avoided from being influenced, the purpose of avoiding forming small holes at two sides of the top of the polycrystalline silicon structure is achieved, and the purpose of eliminating gate source short circuit caused by filling abnormity is achieved.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (12)

1. A method of manufacturing a semiconductor device, comprising:
obtaining a substrate with a groove, wherein a first medium layer is formed on the inner wall of the groove, a polycrystalline silicon structure is formed in a space where the first medium layer is not formed in the groove, and the top of the polycrystalline silicon structure is lower than the surface of the substrate;
removing the part of the first dielectric layer higher than the polycrystalline silicon structure by wet etching;
the plasma bombards the edge of the polysilicon structure, so that the edge of the polysilicon structure is partially removed;
thermally growing a first oxide layer on the inner wall of the groove and the surface of the polycrystalline silicon structure;
and filling a second dielectric layer into the groove, wherein the second dielectric layer fills the groove.
2. The method according to claim 1, wherein the first dielectric layer is an insulating oxide layer, the step of obtaining the substrate with the trench, the first dielectric layer formed on the inner wall of the trench, the polysilicon structure formed in the space in the trench where the first dielectric layer is not formed, the top of the polysilicon structure being lower than the surface of the substrate comprises:
etching the substrate with the mask layer, and forming a groove at the position of the substrate not covered by the mask layer;
thermally growing the insulating oxide layer on the inner wall of the groove to form the insulating oxide layer;
the step of bombarding the edge of the polysilicon structure by the plasma comprises: and bombarding the edge of the mask layer positioned at the top of the groove to partially remove the edge of the mask layer.
3. The method of claim 2, wherein the mask layer is a silicon nitride layer.
4. The method according to claim 1, wherein the step of filling the second dielectric layer into the trench comprises: and forming the second dielectric layer by a high-density plasma chemical vapor deposition process.
5. The method of claim 1, wherein the step of plasma bombarding the edge of the polysilicon structure forms a plasma using a high density plasma chemical vapor deposition tool.
6. The method as claimed in claim 5, wherein the process gas for forming the plasma in the HDP CVD apparatus includes helium and oxygen.
7. The method according to claim 6, wherein a volume flow ratio of helium gas and oxygen gas in the process gas is not less than 1.
8. The method according to claim 1, wherein the step of bombarding the edge of the polysilicon structure with the plasma to partially remove the edge of the polysilicon structure causes both sides of the top of the polysilicon structure to form a polysilicon descending slope structure extending to the top of the first dielectric layer after removal, and an included angle between the slope structure and the top of the first dielectric layer is an obtuse angle.
9. The method of claim 2, wherein bombarding the edge of the mask layer at the top of the trench such that the edge of the mask layer is partially removed comprises: and removing the part of the mask layer, which protrudes out of the top of the inner wall of the groove, so that the mask layer does not protrude out of the top of the inner wall of the groove any more after removal.
10. The method of claim 1, wherein the semiconductor device is a shielded gate trench device and the polysilicon structure is used to form a shielded gate structure.
11. A shielded gate trench device, comprising:
a substrate provided with a groove;
the shielding gate dielectric layer is positioned at the bottom and the inner wall of the groove;
and the shielding grid polycrystalline silicon layer is arranged in the groove, and two sides of the top of the shielding grid polycrystalline silicon layer are slope structures extending downwards.
12. The shielded gate trench device of claim 11 wherein the angle between the ramp structure and the top of the shielded gate dielectric layer is obtuse.
CN202011377002.4A 2020-11-30 2020-11-30 Preparation method of semiconductor device and shielded gate trench device Pending CN114582717A (en)

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