CN110993502A - Manufacturing method of shielded gate trench power device - Google Patents
Manufacturing method of shielded gate trench power device Download PDFInfo
- Publication number
- CN110993502A CN110993502A CN201911404392.7A CN201911404392A CN110993502A CN 110993502 A CN110993502 A CN 110993502A CN 201911404392 A CN201911404392 A CN 201911404392A CN 110993502 A CN110993502 A CN 110993502A
- Authority
- CN
- China
- Prior art keywords
- groove
- layer
- trench
- sacrificial layer
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000005429 filling process Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 210000004027 cell Anatomy 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a shielded gate trench power device, which comprises the following steps: providing a substrate with a groove, wherein a dielectric layer is formed at the bottom and the side wall of the groove and extends to the surface of the substrate; filling a sacrificial layer in the groove, wherein the sacrificial layer extends to cover the dielectric layer on the surface of the substrate; removing the sacrificial layer; and filling a shielding grid material layer in the groove. According to the invention, before the shielding gate material layer is filled, the sacrificial layer is filled in the groove, and the closing-in of the top end of the groove is weakened or eliminated by etching the sacrificial layer, so that a cavity is prevented from occurring in the filling process of the shielding gate material layer, and the electrical property of a device is improved. Furthermore, the sacrificial layer is removed in two steps, after the sacrificial layer is etched to the first preset height position of the groove in the first step, the exposed dielectric layer is cleaned in a wet method, under the condition that the appearance of the lower part of the groove is not influenced, the inclination angle of the opening at the top end of the groove is increased, the appearance of the upper part of the groove is improved, the filling capacity of the shielding grid material layer is improved, the cell density is improved, and the device performance is improved.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method of a shielded gate trench power device.
Background
Since the invention of power MOS technology, the technology has made many important developments and great advances. In recent years, new device structures and new manufacturing processes for power MOS technology have continually emerged to achieve two of the most basic goals: maximum power handling capability, minimum power consumption. Trench mosfet (trench mos) technology is one of the most important technological drivers to achieve this goal. Originally, the Trench MOS technology was invented to increase the channel density of planar devices to improve the current handling capability of the devices, but the channel density and drift resistance are not ideal enough.
Therefore, the industry further provides a new Trench MOS structure, which can not only reduce the channel density, but also further reduce the resistance of the drift region. Among the new Trench MOS structures, the most representative is the shielded Gate/discrete Gate (Shield Gate/Split Gate) Trench technology, the shielded Gate Trench power device is also commonly referred to as SGT device, and the first polysilicon layer, i.e. the shielded polysilicon (Shield), can be used as the "in-vivo field plate" to reduce the electric field in the drift region, so as to reduce the resistance of the drift region, so the Shield-Gate/Split Gate technology generally has lower on-resistance and higher breakdown voltage, and can be used for higher voltage (20V-250V) Trench MOS products. The power device has the advantages of low conduction loss, low grid charge, high switching speed, low device heating and high energy efficiency, so that the product can be widely applied to power supplies or adapters of high-end consumer electronics products such as personal computers, notebook computers, netbooks or mobile phones, lighting (high-pressure gas discharge lamps) products, televisions (liquid crystal or plasma televisions) and game machines.
In the conventional process for manufacturing a high-voltage shielded gate trench power device, in order to achieve the charge balance required for withstanding high voltage, a deep trench needs to be formed, a thick oxide layer needs to be grown on the sidewall of the deep trench, and then polysilicon is refilled to introduce potential. And the sum of the thickness of the oxide layer and the width of the polysilicon is the final width of the trench. The higher the voltage to be sustained, the thicker the sidewall oxide layer is required, so that the trench width of the SGT device is increased with the increase of the voltage, and at the same time, the size of the device cell is increased. In order to reduce the cell size and increase the device current density, it is desirable in SGT device design that the width of the polysilicon be as small as possible. Because the depth of the trench of the SGT device is usually deeper to withstand high voltage, the process requires the polysilicon to fill the trench with a high aspect ratio, which puts a strict requirement on the shape of the trench before the polysilicon is filled.
In the actual process, the shape of the groove before filling the polysilicon is determined by the etching of the silicon groove and the growth of the side wall oxide layer. The silicon trench etch is done in one step by an etch process, while the oxide layer on the sidewalls is formed by both thermal oxygen and CVD. Due to the characteristics of the CVD process, the width of the top end of the trench is often smaller than the width of the middle part and the bottom part, forming a "closed-up" feature of the trench, which may cause a void (void) to be formed in the middle part or the bottom part of the trench during the polysilicon filling, and finally cause abnormal feature during the polysilicon etching back, damage the charge balance, and cause final electrical failure.
Disclosure of Invention
The invention aims to provide a manufacturing method of a shielded gate groove power device, which improves the appearance of a groove before a shielded gate material layer is filled, avoids forming a cavity in the groove when the shielded gate material layer is filled, and improves the filling capacity of the shielded gate material layer.
In order to achieve the above object, the present invention provides a method for manufacturing a shielded gate trench power device, comprising:
providing a substrate, wherein at least one groove is formed in the substrate, and dielectric layers are formed at the bottom and the side wall of the groove and extend to the surface of the substrate;
filling a sacrificial layer in the groove, wherein the sacrificial layer extends to cover the dielectric layer on the surface of the substrate;
removing the sacrificial layer; and
and filling a shielding grid material layer in the groove.
Optionally, the dielectric layer is formed by a thermal oxidation method and a CVD method, and the dielectric layer on the surface of the substrate extends toward the center of the trench, and a closed end is formed at the top end of the trench.
Optionally, the step of removing the sacrificial layer includes:
etching the sacrificial layer to a first preset height position of the groove, and exposing the dielectric layer on the side wall of part of the groove;
cleaning the exposed part of the dielectric layer on the side wall of the groove by a wet method; and the number of the first and second groups,
and removing the remaining sacrificial layer in the groove.
Optionally, when the sacrificial layer is etched to a first predetermined height position of the trench, a part of the dielectric layer extending to the center of the trench is etched and removed to weaken or eliminate a closed end at the top end of the trench.
Optionally, the wet cleaning of the exposed part of the dielectric layer on the sidewall of the trench includes: and removing part of the exposed dielectric layer to enable the inclination angle of the top end of the groove to be larger than 90 degrees.
Optionally, after the trench is filled with the shielding gate material layer, the method further includes: and etching the shielding grid material layer to a second preset height position of the groove to form a shielding grid.
Optionally, the second predetermined height position is lower than or equal to the first predetermined height position.
Optionally, the sacrificial layer is made of photoresist, polyimide or BARC. .
Optionally, the sacrificial layer is removed by dry etching.
Optionally, the shielding gate material layer is a polysilicon layer, and the dielectric layer is a silicon oxide layer or a silicon nitride layer.
In summary, the present invention provides a method for manufacturing a power device with a shielded gate trench, wherein before filling a polysilicon layer, a sacrificial layer is filled in the trench, and the sacrificial layer is etched to weaken or eliminate a closed end at the top end of the trench, thereby preventing voids from occurring in the subsequent filling process of a shielded gate material layer, and further improving the electrical property of the device. Furthermore, the sacrificial layer is removed in two steps, after the sacrificial layer is etched to the first preset height position of the groove in the first step, the exposed dielectric layer is cleaned in a wet method, under the condition that the appearance of the lower part of the groove is not influenced, the inclination angle of the opening at the top end of the groove is increased, the appearance of the upper part of the groove is improved, the filling capacity of the shielding grid material layer is improved, the cell density is improved, and the device performance is improved.
Drawings
Fig. 1A to fig. 1C are schematic structural diagrams corresponding to respective steps of a method for manufacturing a shielded gate trench power device.
Fig. 2 is a flowchart of a method for manufacturing a shielded gate trench power device according to an embodiment of the present invention;
fig. 3A to 3G are schematic structural diagrams of corresponding steps in a method for manufacturing a shielded gate trench power device according to an embodiment of the present invention.
Wherein the reference numbers indicate:
100. 200-a substrate;
110. 210-a trench;
101. 201-a dielectric layer;
102 ', 202' -a layer of shielding gate material;
102. 202-shield grid
203-sacrificial layer.
Detailed Description
Fig. 1A to fig. 1C are schematic structural diagrams corresponding to respective steps of a method for manufacturing a shielded gate trench power device.
First, referring to fig. 1A, a trench 110 is formed on a substrate 100, a dielectric layer 101 is formed on the bottom and the sidewall of the trench 110, and the dielectric layer 102 extends to cover the surface of the substrate 100. The dielectric layer 101 is formed by two steps of a thermal oxidation method and a CVD process, and due to the characteristics of the CVD process, the dielectric layer on the surface of the substrate 100 extends toward the center of the trench 110, so that the width of the top of the trench 110 is smaller than the width of the middle and the bottom of the trench, and a 'closed-up' shape of the trench 110 is formed.
Next, referring to fig. 1B, a shielding gate material layer 102 'is filled in the trench 110, and the shielding gate material layer 102' extends to cover the surface of the substrate 100. Due to the "closed" feature of the trench 110, a void 120 is formed in the middle or bottom of the trench 110 when the shielding gate material layer 102' is filled, and the sizes of the voids 120 formed in different trenches 110 are different.
Then, referring to fig. 1C, the shielding gate material layer 102' is etched back to a predetermined height position of the trench 110 to form a shielding gate. Due to the voids 120 formed in the trench 110, the shield gate 102 formed after etching back the shield gate material layer 102' has an abnormal morphology, which may disrupt the charge balance and lead to a final electrical failure.
In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing a shielded gate trench power device, which includes providing a substrate, forming at least one trench in the substrate, forming a dielectric layer on the bottom and the sidewall of the trench, extending the dielectric layer to cover the surface of the substrate, filling a sacrificial layer in the trench, extending the sacrificial layer to cover the dielectric layer on the surface of the substrate, removing the sacrificial layer, and filling a shielded gate material layer in the trench. According to the invention, before the shielding gate material layer is filled, the sacrificial layer is filled in the groove, and the closing-in of the top end of the groove is weakened or eliminated by etching the sacrificial layer, so that a cavity is prevented from being generated in the subsequent filling process of the shielding gate material layer, and the electrical property of a device is further improved. Furthermore, the sacrificial layer is removed in two steps, after the sacrificial layer is etched to the first preset height position of the groove in the first step, the exposed dielectric layer is cleaned in a wet method, under the condition that the appearance of the lower portion of the groove is not affected, the inclination angle of the opening at the top end of the groove is increased, the appearance of the upper portion of the groove is improved, the filling capacity of the shielding grid material layer is improved, the cell density is improved, and the device performance is improved.
The method for manufacturing the shielded gate trench power device according to the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 2 is a flowchart of a method for manufacturing a shielded gate trench power device according to this embodiment, and as shown in fig. 2, the method for manufacturing a shielded gate trench power device according to this embodiment includes the following steps:
s01: providing a substrate, wherein at least one groove is formed in the substrate, and dielectric layers are formed at the bottom and the side wall of the groove and extend to the surface of the substrate;
s02: filling a sacrificial layer in the groove, wherein the sacrificial layer extends to cover the dielectric layer on the surface of the substrate;
s03: removing the sacrificial layer; and the number of the first and second groups,
s04: and filling a shielding grid material layer in the groove.
Fig. 3A to fig. 3G are schematic structural diagrams corresponding to corresponding steps of the manufacturing method of the shielded gate trench power device provided in this embodiment, and the manufacturing method of the shielded gate trench power device provided in this embodiment will be described in detail below with reference to fig. 2 and with reference to fig. 3A to fig. 3G.
First, referring to fig. 3A, step S01 is performed to provide a substrate 200, where the substrate 200 has at least one trench 210 formed thereon, and a dielectric layer 201 is formed on the bottom and the sidewall of the trench 210, where the dielectric layer 201 extends to the surface of the substrate 200. The substrate 200 may be a silicon-based semiconductor or a silicon-on-insulator (SOI) substrate, which is exemplified as a silicon substrate in the present embodiment. A silicon epitaxial layer (not shown) is formed on the surface of the substrate 200, and the trench 210 is formed in the silicon epitaxial layer, that is, the silicon epitaxial layer 1 is used for forming a drift region of a shielded gate trench power device. Taking an N-type MOSFET device as an example, the doping types of the substrate 200 and the epitaxial layer 201 are both N-type, and the doping concentration of the substrate 200 is higher than that of the epitaxial layer. The trench 210 has a high aspect ratio and can be completed in one step by an etching process. The trenches 210 are each, for example, between 3 μm and 6 μm deep. The bottom corner of the groove 210 may be arc-shaped or right-angled. In this embodiment, the bottom corner of the groove 210 is arc-shaped.
The dielectric layer 201 is, for example, a silicon oxide layer or a silicon nitride layer, has a thickness of 600nm to 700nm, and is formed by two steps of a thermal oxidation method and a CVD process. Due to the characteristics of the CVD process, the dielectric layer 201 on the substrate surface extends toward the center of the trench 210, so that the width of the top of the trench 210 is smaller than the width of the middle and the bottom, and a closed end is formed at the top of the trench 210 (as shown by the dashed circle in fig. 3A).
Next, referring to fig. 3B, in step S02, filling the trench 210 with a sacrificial layer 203, where the sacrificial layer 203 extends to cover the dielectric layer 201 on the surface of the substrate 200. The sacrificial layer 203 has better filling characteristics, and the closing-in at the top of the trench 210 does not affect the filling of the sacrificial layer 203. The material of the sacrificial layer 203 is, for example, a photoresist, a polyimide, or a Bottom Anti-Reflective Coatings (BARC) with good filling property. In this embodiment, the sacrificial layer 203 is made of a photoresist, and the photoresist has good fluidity to facilitate filling of the deep silicon trench and removal in a subsequent removal process. Other fillers may be used as the sacrificial layer 203 in other embodiments of the present invention.
Next, referring to fig. 3C to 3E, step S03 is performed to remove the sacrificial layer 203. Specifically, as shown in fig. 3C, the sacrificial layer 203 is etched to a first predetermined height position of the trench 210, and the dielectric layer 201 on a portion of the trench sidewall is exposed. For example, the sacrificial layer 203 may be dry etched and then removed by dry etchingAnd etching to remove a part of the dielectric layer 201 extending to the center of the trench 210 while the sacrificial layer 203 is used to weaken or eliminate the top end of the trench. Illustratively, when the material of the sacrificial layer 203 is photoresist, the dielectric layer 201 is silicon oxide, the sacrificial layer 203 is etched by using a combination of CF4, CHF3 and oxygen gas, and CF may be adjusted4And CHF3The ratio of gases, thereby achieving a certain selectivity ratio of silicon oxide to photoresist.
Then, as shown in fig. 3D, the exposed part of the dielectric layer 201 on the sidewall of the trench is wet-cleaned. For example, a hydrofluoric acid solvent or a phosphoric acid solvent may be used to clean a portion of the dielectric layer 201 exposed on the sidewall of the trench, and a wet cleaning may be used to remove a portion of the exposed dielectric layer 201, especially to remove the dielectric layer 201 located at the top end of the trench 210, so that the inclination angle of the dielectric layer 201 at the top end of the trench 210 is greater than 90 degrees, thereby increasing the opening of the trench 210, and facilitating the filling of the shielding gate material layer in the subsequent process.
Then, as shown in fig. 3E, the remaining sacrificial layer 203 in the trench 210 is removed. The remaining sacrificial layer 203 in the trench 210 may be removed, for example, using a dry etch.
In the process of removing part of the exposed dielectric layer 201 by wet cleaning, the lower part of the trench 210 is protected by the sacrificial layer 203, the thickness of the dielectric layer 201 at the lower part of the trench 210 is not changed, and only the dielectric layer 201 exposed at the top of the trench is removed by etching, so that the opening at the top end of the trench 210 is enlarged. In the subsequent process, the dielectric layer 210 on the upper portion of the sidewall of the trench 210 is etched to form a gate dielectric layer, so that the performance of a finally formed device is not reduced by removing part of the dielectric layer 210 on the upper portion of the sidewall of the trench 210 by wet cleaning, and on the contrary, part of the dielectric layer 210 on the upper portion of the sidewall of the trench 210 is taken out by wet cleaning, so that the aspect ratio of the upper portion of the trench 210 is improved, the opening of the trench 210 is enlarged, the filling of a gate material layer is easily shielded, the generation of a void.
Next, referring to fig. 3F and 3G, step S04 is performed to fill the trench 210 with the shielding gate material layer 202'. As shown in fig. 3F, the trench 210 is filled with a shielding gate material layer 202 ', and the shielding gate material layer 202' covers the dielectric layer 201 on the surface of the substrate. The shielding gate material layer 202 'may be polysilicon, aluminum, tantalum, tungsten, titanium, or the like, and may be formed by deposition, in which the shielding gate material layer 202' is a polysilicon layer in this embodiment. Then, as shown in fig. 3G, the shielding gate material layer 202' is etched to a second predetermined height position of the trench 210 to form the shielding gate 202, i.e., the shielding gate is formed at the lower portion of the trench 210. The layer 202' of shield gate material in the first trench 210 may be etched back, for example, by using a plasma dry etch or a wet etch. Depending on the product, the etch-back depth may be different, but preferably the second predetermined height position is lower than the first predetermined height position, or the second predetermined height position is the same as the first predetermined height position. In this embodiment, the second predetermined height position is the same as the first predetermined height position, so that the thickness of the dielectric layer around the shield gate can be ensured while the tilt angle of the top end of the trench 210 is enlarged as much as possible, and the requirement of the device for withstanding voltage can be met.
Finally, the method for manufacturing a shielded gate trench power device provided in this embodiment further includes: and forming a gate dielectric layer on the side wall of the upper part of the groove 210, forming a gate on the upper part of the groove 210, and the like so as to form a plurality of periodically arranged cellular structures in the substrate. The above subsequent steps are completed by adopting the prior art, and are not described again here.
In summary, the present invention provides a method for manufacturing a shielded gate trench power device, including: providing a substrate, wherein at least one groove is formed in the substrate, and dielectric layers are formed at the bottom and the side wall of the groove and extend to the surface of the substrate; filling a sacrificial layer in the groove, wherein the sacrificial layer extends to cover the dielectric layer on the surface of the substrate; removing the sacrificial layer; and filling a shielding grid material layer in the groove. According to the invention, before the shielding gate material layer is filled, the sacrificial layer is filled in the groove, and the closing-in of the top end of the groove is weakened or eliminated by etching the sacrificial layer, so that a cavity is prevented from being generated in the subsequent filling process of the shielding gate material layer, and the electrical property of a device is further improved. Furthermore, the sacrificial layer is removed in two steps, after the sacrificial layer is etched to the first preset height position of the groove in the first step, the exposed dielectric layer is cleaned in a wet method, under the condition that the appearance of the lower portion of the groove is not affected, the inclination angle of the opening at the top end of the groove is increased, the appearance of the upper portion of the groove is improved, the filling capacity of the shielding grid material layer is improved, the cell density is improved, and the device performance is improved.
Claims (10)
1. A method for manufacturing a shielded gate trench power device, comprising:
providing a substrate, wherein at least one groove is formed in the substrate, and dielectric layers are formed at the bottom and the side wall of the groove and extend to the surface of the substrate;
filling a sacrificial layer in the groove, wherein the sacrificial layer extends to cover the dielectric layer on the surface of the substrate;
removing the sacrificial layer; and the number of the first and second groups,
and filling a shielding grid material layer in the groove.
2. The method of claim 1, wherein the dielectric layer is formed by thermal oxidation and CVD, and the dielectric layer on the surface of the substrate extends to the center of the trench to form a closed end at the top of the trench.
3. The method of manufacturing a shielded gate trench power device of claim 2, wherein the step of removing the sacrificial layer comprises:
etching the sacrificial layer to a first preset height position of the groove, and exposing the dielectric layer on the side wall of part of the groove;
cleaning the exposed part of the dielectric layer on the side wall of the groove by a wet method; and the number of the first and second groups,
and removing the remaining sacrificial layer in the groove.
4. The method of claim 3, wherein the sacrificial layer is etched to a first predetermined height of the trench while partially etching away the dielectric layer extending toward the center of the trench to reduce or eliminate a constriction at the top of the trench.
5. The method of claim 4, wherein wet cleaning the exposed portion of the dielectric layer on the trench sidewall comprises:
and removing part of the exposed dielectric layer to enable the inclination angle of the top end of the groove to be larger than 90 degrees.
6. The method for manufacturing the shielded gate trench power device according to claim 5, further comprising, after filling the shielded gate material layer in the trench:
and etching the shielding grid material layer to a second preset height position of the groove to form a shielding grid.
7. The method of claim 6, wherein the second predetermined height position is less than or equal to the first predetermined height position.
8. The method of any of claims 1-7, wherein the sacrificial layer is made of photoresist, polyimide or BARC.
9. The method of claim 8, wherein the sacrificial layer is removed by dry etching.
10. The method of any of claims 1-7, wherein the shield gate material layer is a polysilicon layer, and the dielectric layer is a silicon oxide layer or a silicon nitride layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911404392.7A CN110993502A (en) | 2019-12-30 | 2019-12-30 | Manufacturing method of shielded gate trench power device |
| CN202010317839.3A CN111403291B (en) | 2019-12-30 | 2020-04-21 | Manufacturing method of shielded gate trench power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911404392.7A CN110993502A (en) | 2019-12-30 | 2019-12-30 | Manufacturing method of shielded gate trench power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110993502A true CN110993502A (en) | 2020-04-10 |
Family
ID=70079363
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911404392.7A Withdrawn CN110993502A (en) | 2019-12-30 | 2019-12-30 | Manufacturing method of shielded gate trench power device |
| CN202010317839.3A Active CN111403291B (en) | 2019-12-30 | 2020-04-21 | Manufacturing method of shielded gate trench power device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010317839.3A Active CN111403291B (en) | 2019-12-30 | 2020-04-21 | Manufacturing method of shielded gate trench power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN110993502A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415992A (en) * | 2020-04-20 | 2020-07-14 | 安建科技(深圳)有限公司 | Shielding gate MOSFET device and preparation method thereof |
| CN111834464A (en) * | 2020-09-15 | 2020-10-27 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor, forming method thereof and semiconductor device |
| CN112802752A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN113327860A (en) * | 2021-08-03 | 2021-08-31 | 绍兴中芯集成电路制造股份有限公司 | Manufacturing method of shielded gate trench type MOS device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582717A (en) * | 2020-11-30 | 2022-06-03 | 无锡华润上华科技有限公司 | Preparation method of semiconductor device and shielded gate trench device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6780731B1 (en) * | 2002-08-22 | 2004-08-24 | Taiwan Semiconductory Manufacturing Co., Ltd. | HDP gap-filling process for structures with extra step at side-wall |
| US8252647B2 (en) * | 2009-08-31 | 2012-08-28 | Alpha & Omega Semiconductor Incorporated | Fabrication of trench DMOS device having thick bottom shielding oxide |
| US20170125531A9 (en) * | 2009-08-31 | 2017-05-04 | Yeeheng Lee | Thicker bottom oxide for reduced miller capacitance in trench metal oxide semiconductor field effect transistor (mosfet) |
| CN102103996A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Preparation method of groove in preparation of groove MOS (Metal Oxide Semiconductor) device |
| CN107017167B (en) * | 2017-03-01 | 2019-12-10 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate device with shielding gate |
| US10510878B1 (en) * | 2018-06-13 | 2019-12-17 | Vanguard International Semiconductor Corporation | Semiconductor devices and methods for forming the same |
-
2019
- 2019-12-30 CN CN201911404392.7A patent/CN110993502A/en not_active Withdrawn
-
2020
- 2020-04-21 CN CN202010317839.3A patent/CN111403291B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415992A (en) * | 2020-04-20 | 2020-07-14 | 安建科技(深圳)有限公司 | Shielding gate MOSFET device and preparation method thereof |
| CN111834464A (en) * | 2020-09-15 | 2020-10-27 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor, forming method thereof and semiconductor device |
| CN112802752A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN113327860A (en) * | 2021-08-03 | 2021-08-31 | 绍兴中芯集成电路制造股份有限公司 | Manufacturing method of shielded gate trench type MOS device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111403291A (en) | 2020-07-10 |
| CN111403291B (en) | 2022-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111403291B (en) | Manufacturing method of shielded gate trench power device | |
| US9245963B2 (en) | Insulated gate semiconductor device structure | |
| US8610205B2 (en) | Inter-poly dielectric in a shielded gate MOSFET device | |
| CN111081540A (en) | Manufacturing method of shielded gate trench power device | |
| KR100610496B1 (en) | Field Effect Transistor device with fin structure and method for manufacturing thereof | |
| US20100308400A1 (en) | Semiconductor Power Switches Having Trench Gates | |
| CN101442074B (en) | Trench MOSFET and manufacturing method thereof | |
| US6511886B2 (en) | Method for manufacturing trench-gate type power semiconductor device | |
| KR101907175B1 (en) | Trench mos device having a termination structure with multiple field-relaxation trenches for high voltage applications | |
| US7910437B1 (en) | Method of fabricating vertical channel semiconductor device | |
| CN111446157A (en) | Shielded gate field effect transistor and method of forming the same | |
| KR20150036196A (en) | Method of forming a tapered oxide | |
| US9972690B2 (en) | Method for producing a dielectric field plate in a substrate trench, a corresponding substrate, and a power transistor | |
| CN114823531A (en) | Super junction device manufacturing method, super junction device, chip and circuit | |
| CN111627820B (en) | Shielded gate field effect transistor and preparation method thereof | |
| CN111681963B (en) | Shielded gate field effect transistor and forming method thereof | |
| KR102568095B1 (en) | Manufacturing method of semiconductor device | |
| CN114023811A (en) | Shielded gate trench type MOSFET device and manufacturing method thereof | |
| CN111863750B (en) | Method for manufacturing semiconductor device | |
| WO2011043780A1 (en) | Improved trench termination structure | |
| TWI817343B (en) | Trench-gate semiconductor device and method of forming the same | |
| KR102119483B1 (en) | Power semiconductor device and method of fabricating the same | |
| US20240145564A1 (en) | Semiconductor structure and the forming method thereof | |
| CN109216449B (en) | Trench type power semiconductor element and manufacturing method thereof | |
| Ng | Review on Methods for Trench MOSFET Gate Oxide Reliability and Switching Speed Improvement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20200410 |
|
| WW01 | Invention patent application withdrawn after publication |