KR20150036196A - Method of forming a tapered oxide - Google Patents

Abstract

Fabrication processes for a tapered field plate dielectric region for high voltage semiconductor devices are disclosed. One exemplary process includes depositing an oxide thin film, depositing a polysilicon hard mask, depositing a resist layer, and etching the trench region, performing a deep silicon trench etch, . The process may further include repeated steps of depositing an oxide layer and anisotropically etching the oxide to form a tapered wall in the trench. The process may further include the step of depositing poly and the further step of performing the additional process to form the semiconductor device. Another exemplary process includes etching a trench in a semiconductor wafer, depositing an insulating layer on the semiconductor wafer to form a gap in the trench, depositing a mask layer on the insulating layer, And alternately etching the mask layer and the insulating layer to form a plate dielectric region.

Description

TECHNICAL FIELD The present invention relates to a method of forming a tapered oxide,

This disclosure generally relates to the fabrication of field plate dielectrics for high voltage semiconductors, and more particularly, this disclosure relates to the fabrication of tapered field plate dielectrics for high voltage semiconductor devices.

This application claims priority to U.S. Patent Application No. 13 / 558,218, filed July 25, 2012, and U.S. Patent Application Serial No. 13 / 572,492, filed August 10, 2012, the entire disclosures of which are incorporated herein by reference, The entire contents of which are hereby incorporated herein by reference.

Electronic devices use electrical power to drive. Power is typically delivered as a high voltage alternating current (ac) through a wall sock. Devices, typically referred to as power converters or power supplies, can be used to convert high voltage alternating current inputs into well regulated direct current (dc) outputs through energy transfer components. One type of power converter is a switched mode power converter, which is commonly used in many electronic devices today due to its high efficiency, small size and low weight. Many switch mode power converters that provide electricity to electronic devices such as tablet computers, smart phones and LED lights rely on power semiconductor devices capable of handling high voltages. For example, semiconductor devices in mobile phone chargers may be required to handle peak voltages up to 600V without breaking down. Some of these high voltage devices deal with high voltages by spreading electric fields over larger areas of the semiconductor, which prevents electric fields from exceeding breakdown thresholds. To help disperse the electric fields, field plates are sometimes used.

One type of high-voltage transistor is a vertical thin silicon (VTS) high-voltage field effect transistor (HVFET). For example, FIG. 1 illustrates an exemplary VTS HVFET 10 made on a wafer 11. The VTS HVFET 10 includes source regions 15a and 15b, body region 14 and drain regions 12 and 13 (including a long drain extension) in a silicon pillar. do. The potential applied to the gates 17a and 17b can regulate the channel in the body region 14 and can control the conduction between the source regions 15a and 15b and the drain regions 12 and 13 . The potential of the body region 14 can be adjusted by the body contact 16. The HVFET 10 also has a field plate 18 that is separated from the silicon pillar by a field plate dielectric 19. The field plate 18 enables the breakdown voltage to be increased by distributing high voltage drops over the wider areas in the extended drain region (i. E., The dispersion of the electric fields).

The present disclosure provides a method of fabricating field plate dielectrics to overcome the problems of the high voltage transistors described above.

Non-limiting and non-area embodiments of the present invention are described with reference to the following drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Figures 1 to 10 illustrate the formation of tapered oxide by deposition and etching in various steps. 11 to 23 show the formation of a tapered oxide by deposition of a thick oxide in various steps.
Figure 1 shows an exemplary HVFET with a field plate.
Figures 2A-2C illustrate the formation of a hard mask in accordance with an exemplary process for forming a tapered field plate dielectric region.
Figures 3A and 3B illustrate etching of the trenches according to an exemplary process for forming the tapered field plate dielectric regions.
Figures 4A and 4B illustrate a first cycle of insulation layer deposition and etching in accordance with an exemplary process for forming the tapered field plate dielectric region.
5A and 5B illustrate a second cycle of insulation layer deposition and etching according to an exemplary process for forming the tapered field plate dielectric region.
Figures 6A and 6B illustrate a third cycle of insulation layer deposition and etching in accordance with an exemplary process for forming the tapered field plate dielectric regions.
Figure 7 illustrates a tapered field plate dielectric region prepared to receive a conductive material to form an exemplary tapered field plate according to an exemplary process.
Figure 8 shows a cross section of another tapered field plate dielectric region with another profile.
Figure 9 shows a conductive material deposited in the tapered region formed by the tapered field plate dielectric region to form the tapered field plate dielectric region.
Figure 10 shows a flowchart for an exemplary process for forming a tapered field plate dielectric region.
Figure 11 shows another exemplary HVFET structure with a field plate.
12A and 12B illustrate the formation of a trench field plate according to an exemplary process for forming a tapered field plate dielectric region and a mask for trench etch for a field plate dielectric region.
Figures 13A and 13B illustrate etching of the trenches according to an exemplary process for forming the tapered field plate dielectric regions.
FIGS. 14A and 14B illustrate depositing a first insulating layer and filling a gap in the insulating layer with a mask layer according to an exemplary process for forming the tapered field plate dielectric region. FIG.
15 illustrates etching of the mask layer according to an exemplary process for forming the tapered field plate dielectric region.
16A and 16B illustrate isotropic etching of the insulating layer according to an exemplary process for forming the tapered field plate dielectric regions.
Figures 17A and 17B illustrate a second iteration of etching the mask layer according to an exemplary process for forming the tapered field plate dielectric region.
Figures 18A and 18B illustrate a second iteration of the isotropic etching of the insulating layer according to an exemplary process for forming the tapered field plate dielectric region.
Figures 19a and 19b illustrate a third iteration of etching the mask layer according to an exemplary process for forming the tapered field plate dielectric region.
Figure 20 shows a tapered field plate dielectric region after etching the insulating layer and etching the mask layer several more times according to an exemplary process for forming the tapered field plate dielectric region.
Figure 21 shows a tapered field plate dielectric region with a less ideal profile.
Figures 22A and 22B illustrate deposition of a conductive material used to form the tapered field plate according to an exemplary process for forming the tapered field plate dielectric region.
Figure 23 shows a flowchart for another exemplary process for forming a tapered field plate dielectric.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the specific details need not necessarily be employed to practice the invention. In other instances, well-known materials and methods are not described in detail in order to avoid obscuring the present invention.

Reference throughout this specification to "one embodiment "," one embodiment ", "one example ", or" an example "refers to a particular feature, structure or characteristic described in connection with the embodiment or example Quot; are included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," in one embodiment, "an example," or "an example, " It is not pointing. In addition, certain features, structures, or characteristics may be combined within any suitable combinations and / or sub-combinations in one or more embodiments and examples. Certain features, structures, or characteristics may be included within an integrated circuit, an electronic circuit, a combinatorial logic circuit, or other suitable components that provide the functionality described above. In addition, it should be understood that the figures are provided to those skilled in the art for the purpose of illustration and that the drawings are not necessarily drawn to scale.

1 shows a field plate 18 having a field plate dielectric 19 with substantially the same thickness along the depth of the field plate 18. As shown in Fig. In order to develop a reliable device optimally, it may be suitable to maintain a constant electric field along the extended drain region 13. In order to maintain a constant field filament, a graded doping profile for the extended drain region 13 may be necessary. In particular, the tapered doping of the drain region 13 can be progressively reduced along the depth as it approaches the surface of the VTS device 10. [ In this manner, the VTS device 10 can be depleted between the extended drain region 13 and the oxide 19, so that the VTS device 10 is capable of supporting the maximum breakdown voltage. However, one disadvantage of having a graded doping profile is that it may have a lower doping nearer the surface of the VTS device 10, which may result in higher specific resistance and reduced efficiency.

As shown in the drawings and described below, the field plate dielectric thickness depends on the thickness of the device. In particular, the oxide thickness is minimal at the surface and increases along the depth of the device 10 until it reaches the bottom, which increases the thickness of the drain region 13 extending near the surface of the VTS device 10 Thereby enabling doping. As a result, the resistivity of the VTS device 10 can be reduced by a factor of three to four times. In one example, the specific on-resistance can be defined as an intrinsic resistance based on the design of the material and the semiconductor when the drain and source of the VTS device 10 are substantially at 0 V. [ In order to improve the efficiency of the semiconductor device, it will be understood that the resistivity may be reduced to reduce power consumption when the device is conductive. In one example, the varying thickness of the field plate dielectric may be achieved by tapering. In this way, a constant distribution of doping can be achieved.

An exemplary process for forming a tapered field plate dielectric within a semiconductor substrate is described below. This exemplary process may be useful in processes that form various types of devices, such as Schottky diodes, HVFETs, JFETs, IGBTs, bipolar transistors, and the like. The tapered field plate dielectric fabrication is described with reference to the drawings showing various steps of the exemplary process. For ease of discussion, an exemplary process is described with reference to the fabrication of one field plate dielectric region. It should be understood, however, that only a portion of the substrate is shown in the figures. In practice, many devices (e.g., HVFETs) having field plates with tapered field plate dielectric regions may be formed across the substrate in parallel.

2A shows a substrate 200 that includes a wafer 202, a protective layer 204, The wafer 202 may be formed of a material such as, for example, silicon, silicon carbide, diamond, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, May be formed of various materials. The wafer 202 may also be formed of a number of different materials to form a hetero structure. The wafer 202 may also be formed of a base wafer (e.g., a silicon wafer) having other layers (e.g., epitaxially grown layers) grown on top of the base wafer. In one example, the wafer 202 may be 700 to 1000 microns thick.

As shown, a protective layer 204 is deposited on the surface of the wafer 202 to protect the surface of the wafer 202 from defects and damage during processing. The protective layer 204 and the mask layer 206 may be optional within the various variations of the exemplary process. In a simpler process, a tapered oxide may be formed without the mask layer 206, and the silicon pillar itself may be used as a hard mask for the oxide. In an exemplary process variation using a silicon wafer for the wafer 202, the protective layer 204 may be a thermally grown oxide having a thickness of, for example, about 200 angstroms.

Mask layer 206 may be a hard mask (e.g., polysilicon, nitride, and the like). Mask layer 206 may be selected to have etch characteristics that are different from the insulating material to be used to form the field plate dielectric. By choosing the mask layer 206 to have etch characteristics that differ from the field plate dielectric, an etch with a high selectivity of the field plate dielectric material for the mask layer 206 may be used, To be used throughout the formation process of the tapered field plate dielectric. For example, polysilicon may be used for the mask layer 206. If the field plate dielectric material would be an oxide, it would be possible to choose an etch recipe with an oxide to silicon etch selectivity ratio of 10: 1 or 20: 1. In one example, the mask layer 206 may be about 2 to 5 占 퐉 thick, but other thicknesses may be possible depending on the selectivity of the etch recipe used for etching the field plate dielectric material.

Figure 2B shows the substrate 200 after the mask layer 208 has been deposited and patterned to define the location of the trench and field plate dielectric adjacent to the silicon pillar where the semiconductor device will be located Will be located below the remaining portions of mask layer 208). Mask layer 208 is a photoresist mask. In another example, a protective layer 204 and a mask layer may not be used, and a photoresist layer may be deposited directly on the surface of the silicon wafer 202.

Figure 2c illustrates the substrate 200 after the mask layer 206 and the protective layer 204 are etched to expose the surface of the wafer 202 in the area to be etched, ). In one example, the exposed portion of the wafer 202 is d _EXPOSED and may be about 10 to 12 micrometers wide.

Figure 3A shows the substrate 200 after the trenches 302 are formed. In one example, a deep reactive ion etch (DRIE) step is used which causes the formation of scallops 304 on the sidewalls 306 of the trench 302. Trench 302 may be etched to depth 308, which may be about 60 占 퐉 deep in one example. It should be appreciated that other etching techniques that do not form the sheds to form the trenches 302 may also be used.

Figure 3B shows the substrate 200 after the mask layer 208 has been removed. Removing mask layer 208 may be accomplished in various steps. For example, if mask layer 208 is a photoresist mask, a plasma ashing step may be used. In another example, if nitrides or oxides are used, a phosphoric acid or hydrofluoric acid etch step may be used, respectively. 4A shows the substrate 200 after the insulating layer 402 has been deposited. As described above, the field plate dielectric includes one or more insulating layers 402. ( _{E. G.} , Sidewalls 306) and horizontal surfaces (e. _G. , On the bottom of the trench 302 and on top of the mask layer 206) The process for depositing the insulating layer 302 so as to be present on the insulating layer 302 may be conformed. The insulating layer 402 may be silicon dioxide, silicon nitride, boron phosphide silicate glass (BPSG), and the like. Processes such as low pressure chemical vapor deposition, high density plasma, plasma enhanced chemical vapor deposition, and the like can be used to deposit the insulating layer 402. The thickness d _DEP1 can be determined in response to temperature, time and light within the processes. In another example, d _DEP1 is approximately 0.5 [mu] m.

4B shows the substrate 200 after etching the thickness d _ETCH1 of the insulating layer 402 with a high degree of anisotropic etching. In other words, the horizontal surfaces of the substrate are substantially more etched than the vertical surfaces. For example, the vertical to horizontal etch ratio may be 100 to 1, which may also be known as the directionality of the etch. In one example, d _ETCH1 may be a distance of 4 占 퐉 in the vertical direction. The etch recipe used to etch the insulating layer 402 so that the etch rate of the insulating layer 402 is much higher than the etch rate of the mask layer 206 or the wafer 202 may be selected. If the etch recipe selection ratio is sufficiently high, the same mask layer 206 may be used throughout the process to form the tapered field plate dielectric. In addition, if the same material is used for the semiconductor wafer 202 and the mask layer 206 (e.g., silicon wafer and polysilicon mask), the etch recipe for etching the insulating layer 402 may be removed from the trench 302, May have a similar selectivity for the material of the insulating layer 402 relative to the exposed portions of the semiconductor wafer 202 at the bottom of the semiconductor wafer 202 and the mask layer 206 at the surface of the semiconductor wafer 202. For example, a selection ratio of at least 10: 1 or 20: 1 may be used.

D _ETCH1 is d _DEP1 so that portions of the insulating layer 402 on the horizontal surfaces (e.g., the top surface of the mask layer 202 and the bottom portion of the trench 302) . However, as shown on the sidewalls 306 of the trench 302, portions of the insulating layer 402 on the vertical surfaces may be etched down to approximately d _ETCHl , or in some cases down to an amount less than d _ETCHl will be. In other words, only the upper portion of the insulating layer 402 on vertical surface is removed (e. G., Side walls 306, insulating layer 402 portion on the inside trench 302), the depth to which d _ETCH1 It is proportional.

Note that the sectors 304 are not shown in FIG. 4A. The sectors may be removed from the sidewalls of the trench 302 prior to deposition of the insulating layer 402. For example, if the wafer 202 is silicon, a thermal oxidation step may be used to consume the sectors, and an oxide removal step may be used to remove the thermal oxide and leave a smoother sidewall. Alternatively, in variations of the exemplary process, the sectors may remain. In other variations of the exemplary process, the sectors may not be present by the trench etch technique used, or the sectors may be sufficiently small such that the sectors are not apparent or significant.

5A shows the substrate 200 after the insulating layer 502 is deposited on the substrate 202. FIG. The insulating layer 502 may be deposited on top of the insulating layer 402 on the sidewalls 306 of the trench 302 where the insulating layer 402 was not previously removed. The process for depositing the insulating layer 502 such that the thickness d _DEP2 of the insulating layer 502 is deposited on both the vertical and horizontal surfaces can be _conformed . The insulating layer 502 may be the same material deposited to the same thickness, with the same technique as the insulating layer 402. In one alternative, in contrast to the insulating layer 402, the insulating layer 502 may be another material deposited with another technique, or it may have a different thickness. Portions of the sidewalls 306 without the removed insulating layer 402 may now have a total thickness d _DEP1 + d _DEP2 of approximately insulating material. However, portions of the wafer 202 exposed at the bottom of the trench 302 may have a thickness of only about d _DEP2 of the insulating material. In one example, the thickness d _DEP1 of the insulating layer 402 is substantially the same as the thickness d of the insulating layer _DEP2 502. In another example, the thicknesses d _DEP1 , d _{DEP2 of the} insulating layers 402, 502 are different.

5B shows the thickness d _ETCH2 of the insulating layer 502 and a portion of the insulating layer 402 in anisotropic etching (e.g., the same etch used to etch the insulating layer 402 as discussed with reference to FIG. 4B) The substrate 200 is etched. In particular, the upper portions of the insulating layer 502 (on the insulating layer 402) on the sidewalls of the mask 206 and the sidewalls of the trenches 302 were etched. The insulator layer 502 pillars are now located on the insulator layer 402 pillars.

6A shows a substrate 200 after an insulating layer 602 has been deposited on the substrate 202. FIG. A process for depositing the insulating layer 602 such that the thickness d _DEP3 of the insulating material 602 is deposited on both the vertical and horizontal surfaces may be _conformed . The insulating layer 602 may be the same material deposited to the same thickness with the same technique as the insulating layer 402 or the insulating layer 502. [ In alternative embodiments, in contrast to the insulating layer 402 or the insulating layer 502, the insulating layer 602 may be another material deposited with other techniques, or it may have a different thickness. The portions of the sidewalls 306 without the removed insulating layers 402 and 502 can now have a total thickness d _DEP1 + d _DEP2 + d _DEP3 of approximately insulating material. However, portions of the wafer 202 exposed at the bottom of the trench 302 have only a thickness d _DEP3 of approximately insulating material. As shown, the first region 609 includes only portions of the insulating layer 602, and the insulating material is the thickness of d _DEP3 . The second region 611 includes portions of the insulating layer 402 and 602 and the total thickness of the insulating material along the sidewalls 306 in the region 601 is d _DEP1 + d _DEP3 . The third region 613 includes portions of the insulating layer 402, 502 and 602 and the total thickness of the insulating material along the sidewalls 306 in the region 613 is equal to d _DEP1 + d _DEP2 + d _DEP3 .

6B shows the thickness d _ETCH3 (and the insulating layer 402) of the insulating layer 602 in anisotropic etching (e.g., the same etch used to etch the insulating layer 402 as discussed with reference to FIG. 4B) And a portion of the insulating layer 502) are etched. A pillar of insulating layer 602 is now located on the pillar of insulating layer 502 and a pillar of insulating layer 502 is located on the pillar of insulating layer 402. As shown, the first region 615 includes only the insulating layer 402, and the insulating material in the first region 615 has a thickness d _DEP1 . The second region 617 includes portions of the insulating layer 402 and 502 along the sidewall 306 and the total thickness of the insulating material in the region 617 is d _DEP1 + d _DEP2 . The third region 619 includes portions of the insulating layers 402, 502 and 602 and the total thickness of the insulating material along the sidewalls 306 in the region 619 is d _DEP1 + d _DEP2 + d _DEP3 same.

The process of depositing and etching the dielectric, as illustrated in any one of the sets of figures of FIGS. 4A and 4B, 5A and 5B and 6A and 6B, as described with reference to them, As many times as necessary it can be repeated. For example, as shown in FIG. 7, nine cycles of the deposition and etching steps were used to fill the trench shown in FIG. Specifically, nine cycles are associated with six additional cycles to generate the above-described insulating layers 402, 502, 602 and insulating layers 701-706. If the deposition thicknesses are all approximately equal (e.g., d _DEP1 = d _DEP2 = d _DEP3 = d _DEPX ) and the etch quantities are all approximately equal (e.g., d _ETCH1 = d _ETCH2 = d _ETCH3 = d _ETCHX ) , The slope ( m _OX ) of the tapered field plate dielectric region can be approximated by d _ETCHX / d _DEPX .

In other variations of the exemplary process, the profile of the tapered field plate dielectric region may be different. For example, by using insulating layers of different thicknesses and etching the insulating layers of different amounts, the profile of the tapered field plate dielectric region can be adjusted. In one example, the profile of the tapered field plate dielectric region will have a number of different slopes along the tapered field plate dielectric region.

The tapered field plate dielectric regions are shown having well-defined steps with one step representing each deposition / etch cycle. However, it should be understood that in practice, well-defined steps may not exist. For example, the profile of the tapered field plate dielectric region may have a more linear shape. FIG. 8 illustrates a substrate 800 having another example of a profile for a tapered field plate dielectric that is not ideal, such as the profile shown in FIG.

9 illustrates substrate 200 after deposition of a conductive material 902 that fills the rest (not shown) of trenches 302 that are not filled by tapered field plate dielectric regions 710. The conductive material 902 can be any number of materials, such as amorphous silicon, polycrystalline silicon, metal, and the like. If a semiconductor is used for the conductive material 902, the conductive material 902 may be in-situ doped when they are deposited. The top side of the conductive material 902 may then be planarized using chemical mechanical polishing (CMP) or an etch-back step. Electrical contact may then be formed with respect to the remaining portion of the conductive material 902 forming the tapered field plate.

Once the tapered field plate dielectric and the tapered field plate are formed, the semiconductor device fabrication flows may include active devices in the active regions (e.g., silicon pillars 904, 906) May be performed. For example, a VTS HVFET process may be used to form HVFETs in the silicon pillars 904, 906.

FIG. 10 shows a flowchart for an exemplary process 1000 (similar to the exemplary process described above with reference to FIGS. 2-9) for forming a tapered field plate dielectric region in a semiconductor substrate. In step 1002, a silicon wafer is obtained. The silicon wafer may comprise other doped layers, for example, produced with epitaxially grown layers of silicon. At step 1004, a thin film of oxide is grown on the surface of the silicon wafer to form a protective layer that protects the surface of the silicon wafer from process damage and debris. At step 1006, a polysilicon hard mask is deposited (e.g., see FIG. 2A). The polysilicon hard mask may be used throughout the formation of the tapered field plate dielectric region surrounding the tapered field plate. Polysilicon may be preferred for the hard mask since etch recipes that provide a high selectivity for etching the oxide (or other insulating materials) against the polysilicon may already be possible. In step 1008, the hard mask is then patterned and etched using a photolithography step (see, e.g., FIGS. 2B and 2C). The hard mask now defines the area to be etched for the trench for the tilted field plate. In step 1010, a DRIE process (or Bosch etch) is performed to define the trench for the tilted field plate (e.g., see FIG. 3A). In some variations of the exemplary process 1000, steps 1008 and 1010 may be combined in one step. At step 1012, any photoresist remaining from steps 1008, 1010 is removed to the plasma ashing step (e.g., see FIG. 3B). In step 1014, an oxide layer is deposited on the vertical and horizontal surfaces of the substrate, including the sidewalls and bottom of the trench formed in step 1010 (e.g., FIGS. 4A, 5A, 6A). At step 1016, an anisotropic etch is performed to remove a constant thickness of the oxide deposited at step 1014 (see, e.g., Figures 4b, 5b, and 6b). Because the etch is anisotropic (i.e., substantially anisotropic), the oxide on the horizontal surfaces of the wafer is completely removed, while only the top of the oxide on the vertical sides is removed. Thus, most of the oxide deposited on the sidewalls of the trench will remain (e. G., All of the oxides on the sidewalls except the top). At step 1018, it is determined whether the trench is sufficiently filled with oxide to accommodate the material forming the tapered field plate (e.g., see FIG. 7). For example, this can be determined based on the number of oxide deposition / etch cycles that have been performed. As another example, the cycles of steps 1014 and 1016 may be repeated after the oxide etch step 1016 until the threshold thickness of the oxide remains within the center bottom of the trench. In step 1020, once the tapered field plate dielectric is formed in the trench, polysilicon is deposited in the trench to form the tapered field plate (see, e.g., FIG. 9). A planarization step may be needed to ensure that the field plate and the surface of the wafer are coplanar. In step 1022, a semiconductor process flow is performed to form the HVFET in the silicon pillar adjacent to the trench containing the tilted field plate.

While the exemplary process 1000 has been described with reference to particular materials and layers, it should be understood that some layers may be optional and the materials of the wafers and layers may vary.

FIG. 11 illustrates an exemplary VTS HVFET 1100 formed on a wafer (N + substrate) 1110. The VTS HVFET 1100 includes an N extended drain region 1130 that includes source regions 1150, N +, body region 1140, P body, and a long drain extension in the silicon pillar. The potential applied to the gates 1170 can regulate the channel in the body region 1140 and control the conduction between the source regions 1150 and the drain regions. The HVFET 1100 also includes a field plate 1180 separated from the silicon pillar by a field plate dielectric 1190 (oxide). Field plate 1180 enables an increase in breakdown voltage by dispersing high voltage drops (i.e., distributing electric fields) over larger areas within the extended drain area.

The field plate dielectric 1190 is substantially the same thickness along the depth of the field plate 1180. In order to optimize and develop a reliable device, it may be appropriate to maintain a constant electric field along the extended drain region 1130. In order to maintain a constant electric field, a graded doping profile for the extended drain region 1130 may be necessary. In particular, the oblique doping of the drain region 1130 may progressively decrease along the depth as it approaches the surface of the VTS device 1100. In this way, the VTS device 1100 can be depleted between the extended drain region 1130 and the oxide 1190 to enable the VTS device 1100 to support the maximum breakdown voltage. However, one disadvantage of having a graded doping profile is that it has lower doping nearer the surface of the VTS device 1100, which may result in higher resistivity and reduced efficiency.

12A shows a substrate 1200 that includes a wafer 1202. The wafer 1202 may be formed of a variety of materials such as, for example, silicon, silicon carbide, diamond, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and the like. The wafer 1202 may also be formed of a number of different materials to form a heterostructure. Wafer 1202 may also be formed of a base wafer (e.g., a silicon wafer) having other layers (e.g., epitaxially grown layers) grown on top of the silicon wafer.

Figure 12B shows the substrate 1200 after the mask layer 1204 has been deposited and patterned to define the location of the trench and field plate dielectric adjacent to the silicon pillar where the semiconductor device will be located, Is below the remaining portions of the mask layer 1204. Mask layer 1204 can be a hard mask or a soft mask. In one example, the soft mask may be a photoresist layer. In some variations of the exemplary process, a protective layer may be deposited on the surface of the wafer 1202 prior to deposition and patterning of the mask layer 1204. The protective layer may protect the surface of the wafer 1202 from defects and damage in the process. If the exemplary process does not use a protective layer (as shown in FIG. 12B), it may be desirable to remove the damage from the surface of the wafer 1202 prior to performing another process where the wafer 1202 surface is associated, A restoration step can be used to clean. For example, if a silicon wafer is used for the wafer 1202, the protective layer (not shown) may be a thermally grown oxide, for example, to a thickness of about 200 ANGSTROM. In one example, the portion of mask layer 1204 may have a length d _MSEG of 1 to 3 占 퐉.

13A shows a substrate 1200 after the trenches 1302 are formed. In one example, a deep reactive ion etching (DRIE) step is used, which results in the formation of recesses 1304 on the sidewalls 1306 of the trench 1302. Trench 1302 may be etched to depth d _ETCH 1308, which may be about 60 占 퐉 deep in one example. It should be understood that other etch techniques that do not form sectors may also be used.

13B shows the substrate 1200 after the mask layer 1204 has been removed. Removing the mask layer 1204 can be accomplished in various steps. For example, if mask layer 1204 is a photoresist mask, a plasma ashing step may be used. In another example, if nitrides or oxides are used for the mask layer 1204, a phosphoric acid or hydrofluoric acid etch step may be used, respectively.

14A shows a substrate 1200 after the insulating layer 1402 has been deposited. The process for depositing the insulating layer 1402 such that the thickness d ₁ of the insulating material is approximately on the vertical sidewalls 1306, the bottom of the trenches 1302 and the top of the silicon pillars 1407, . The insulating layer 1402 will also form a gap 1404. The insulating layer 1402 may include silicon dioxide, silicon nitride, boron phosphide silicate glass, and the like. Processes such as low pressure chemical vapor deposition, high density plasma, plasma enhanced chemical vapor deposition, and the like can be used to deposit the insulating layer 1402. In one example, d ₁ may be between 0.5 μm and 10 μm, and gap 1404 may be approximately 10 μm across.

Note that the sectors 1304 are not shown in FIG. 14A. The sectors may be removed from the sidewalls 1306 of the trenches 1302 prior to the deposition of the insulating layer 1402. For example, if wafer 1202 is silicon, a thermal oxidation step may be used to consume the sectors, and an oxide removal step may be used to remove the thermal oxide leaving smoother sidewalls. Alternatively, in variations of the exemplary process, the sectors may remain. In other variations of the exemplary process, the sectors may not be present due to the trench etch technique used, or the sectors may be sufficiently small such that the sectors are not apparent or significant.

14B shows a substrate 1200 after a fill mask layer 1406 has been deposited on the substrate 1200. FIG. The thickness d ₂ of the fill mask layer 1406 can be selected to ensure that the gap 1404 is completely filled. In other variations of the exemplary process, the mask layer 1406 may not fill the gap 1404 completely. In particular, due to the possibility of loafing of the insulating layer 1402 and the fill mask layer 1406, the gap 1404 may be discarded (not shown) with portions of the gap 1404 unfilled. In one example, the material of the fill mask layer 1406 may be different from that of the insulating layer 1402 material to enable a highly selective etch recipe for the etch of the insulating layer 1402 material for the fill mask layer 1406 material. It must have etch characteristics. For example, if insulating layer 1402 is an oxide, mask layer 1406 may be polysilicon.

15 illustrates a method of removing the fill mask layer 1406 from the top surface of the insulating layer 1402 and portions of the sidewalls of the insulating layer 1406 to regenerate a portion of the gap 1404 (represented by region 1502) And substrate 1200 after mask layer 1406 underwent a planarized etch. In one example, FIG. 15 illustrates the starting point of the substrate 1200 prior to the alternating cycles of etching of the insulating layer 1402 and etching of the fill mask 1406 to create a tapered field plate dielectric region.

16A and 16B illustrate a substrate 1200 before and after the amount e ₁ of the insulating layer 1402 is isotropically etched, wherein the isotropic etching is carried out in an approximately equal amount Of the material is etched. In other words, the amount of insulating layer 1402 etched from the horizontal surfaces is approximately equal to the amount of insulating layer 1402 etched from the vertical surfaces. The isotropic property of the etch is shown by line 1602 which approximates the amount of insulating layer 1402 removed from FIGS. 16A and 16B during the etch. As can be observed from line 1602, the thickness e ₁ of the removed insulating material is approximately constant across the surface of the insulating layer 1402. If the etch for the insulating layer 1402 is appropriately selected such that the insulating layer 1402 is selected to have a high selectivity relative to the etched fill mask layer 1406, The amount should be etched. For example, if the insulating layer 1402 is an oxide and the fill mask layer 1406 is polysilicon, an etching step in aqueous solution hydrofluoric acid may be used to effect this isotropic etching. Note that since the sidewalls of the insulating layer 1402 adjacent to the region 1502 are exposed, the width of the region 1502 has increased by approximately 2 x e ₁ .

17A and 17B show a substrate 1200 before and after the thickness e ₂ of the fill mask layer 1406 is etched. By etching the fill mask layer 1406, a region 1702 defined by the sidewalls of the newly exposed insulating layer 1402 is formed below the region 1502. When the region 1702 is initially formed because it is narrower than the region 1502 and the original widths of the region 1702 and the region 1502 are both determined by the width of the gap 1404 (Fig. 14A) (See reference numeral 1502).

Figure 18a and 18b, the thickness of the insulating layer (1402) (e ₃₎ a shows the before and after the substrate 1200 is isotropic etching, the isotropic etching is approximately the same amount, regardless of the inclination of the surface that the etching takes place Lt; / RTI > material to be etched. In other words, the amount of insulating layer 1402 etched from the horizontal surfaces is approximately equal to the amount of insulating layer 1402 etched from the vertical surfaces. The isotropic properties of the etch are shown by line 1802 which approximates the amount of insulating layer 1402 removed from FIGS. 18A and 18B during the etch. As can be seen from line 1802, the amount of insulating material removed is approximately constant across the surface of insulating layer 1402. [ If the etch for insulating layer 1402 is appropriately selected, a very small amount of mask layer 140 should be etched (e.g., the same etch discussed with reference to FIGS. 16A and 16B). Since the sidewalls of the insulating layer 1402 adjacent to the regions 1502 and 1702 are exposed, the width of the region 1502 is greater than or equal to about 2 x e ₃ (or a total of 2 x e ₃ from the original width of the region 1502) + 2 x e ₁ ), and the width of region 1702 has grown by about 2 x e ₃ (or a total of 2 x e ₃ from the initial width of region 1702). In other words, there is less insulating layer 1402 thickness e ₃ between the inner sidewalls of the insulating layer 1402 and the sidewalls 1306.

Figure 19a and Figure 19b illustrates the substrate 1200 before and after etching the thickness (e ₄₎ of the filter mask layer 1406. By etching the fill mask layer 1406 an area 1902 defined by the newly exposed sidewalls of the insulating material 1402 is formed below the areas 1502 and 1702. Region 1902 is narrower than region 1702 and region 1902 is defined by the width of the regions 1902,1702 and 1502 because the initial width of regions 1902,1702 and 1502 is all determined by the width of gap 1404 (See Figs. 15 and 17, respectively) when the first and second substrates 1502 and 1702 are initially formed.

The etching of the insulating layer 1402 and the mask layer 1406 can be repeated until the required taper of the insulating layer 1402 is achieved. For example, the process of alternating two etchings (insulating layer and fill mask layer) may continue for any fixed number of repetitions known to produce the required taper. As another example, the alternating process of the two etchings can continue until the mask layer 1406 disappears or has a thickness below some threshold. Each repetition of alternating etches extends a portion of existing regions (e.g., regions 1502, 1702, 1902) by a certain amount and a new region having a width that is approximately the width of gap 1404 (Figure 14A) . Thus, by adding repetitions, the taper at the top of trench 1302 (FIG. 13A) widens and a new "step" is added further into trench 1302.

20 shows a substrate 1200 after mask layer 1406 and insulating layer 1402 are etched six times in total. All the etchings of the insulating layer 1402 remove approximately the same amount of insulating layer 1402 (i.e., e ₁ = e ₃ = e _{2x- 1} And, x is, if all the etching of etching the number of iterations), the mask layer 1406 are removed to approximately the same amount of the mask layer 1406 (i.e., e ₂ = e ₄ = and e _2x, x is the number of etching repeated), The slope ( m _TAPER ) of the taper of the insulating layer 1402 may be about e ₁ / e ₂ .

In other variations of the exemplary process, the profile of the insulating layer 1402 may vary. For example, by etching the insulating layer 1402 and other portions of the mask layer 1406 in different iterations, the profile of the insulating region can be adjusted. In one example, the profile of the insulating layer 1402 will have a number of different gradients along the exposed sidewalls of the insulating layer 1402.

The insulating material is shown to have well-defined steps, one step representing each deposition / etch cycle. However, it should be understood that, in practice, the well-defined steps may not be present. For example, the profile of the insulating region may have a more linear shape. FIG. 21 illustrates a substrate 2100 having another example of a profile for a tapered field plate dielectric that is not ideal, such as the profile shown in FIG.

Figure 22A shows a substrate 1200 after all repetitions of alternate etch steps are completed and any remaining portions of the fill mask layer 1406 have been removed. It should be understood that, in variations of the exemplary process, both the fill mask layer 1406 may be etched during repetitions of the alternate etch steps. Other variations of the exemplary process may also include removing the remaining portions of the fill mask layer 1406 from the field plate 1402 formed after depositing a conductive material in the trenches formed by the taper in the insulating layer 1402. [ (See FIG. 22B).

22B shows the substrate 1200 after deposition of the conductive material 2202 that is not filled by the insulating layer 1402 or that fills the rest (not shown) of the trench 1302 etched during the formation of the taper. do. Conductive material 2202 can be any number of materials, such as amorphous silicon, polycrystalline silicon, metals, and the like. If a semiconductor is used for the conductive material 2202, the conductive material 2202 may be in situ doped when they are deposited. The top side of the conductive material 2202 may then be planarized using a chemical mechanical polishing (CMP) or etchback step. An electrical contact can then be made in the remaining portion of the conductive material 2202, and the remaining portion forms the tapered field plate. Once the field plate is formed, the insulating layer 1402 becomes a tapered field plate dielectric region 2204.

Once the tapered field plate dielectric 2204 is formed and the surface of the wafer 1202 is planarized (if required), the active regions of the substrate 1200 (e.g., silicon pillars 2206, 2208) Semiconductor device fabrication flows can be performed to form active devices. For example, a VTS HVFET process may be used to form HVFETs in the silicon pillars 2206 and 2208. [

Figure 23 shows a flow chart for an exemplary process 2300 (similar to the exemplary process described above with reference to Figures 12-22 for forming a tapered field plate dielectric region in a semiconductor process). In step 2302, a silicon wafer is obtained. The silicon wafer may have other doped layers formed, for example, with epitaxially grown layers of silicon (see, e.g., FIG. 12A). In step 2304, a photoresist mask is patterned (e.g., see FIG. 12B). The photoresist mask defines the location and size of the trench including the tapered field plate and tapered field plate dielectric regions. In step 2306, a DRIE (or Bosch etch) step is performed to define the trench for the tapered field plate (e.g., see FIG. 13B), and any remaining photoresist is stripped See Fig. 13B). In step 2308, an oxide layer is deposited on the vertical and horizontal surfaces of the substrate (e.g., see FIG. 14A). The deposited oxide fills a substantial portion of the trench, leaving a gap in the center of the trench. In step 2310, a polysilicon mask layer is deposited on the wafer and in the gap formed by the oxide deposition of step 2308 (see, e.g., FIG. 14B). At step 2312, an etch of the polysilicon mask is performed to expose portions of the sidewalls of the oxide layer within the gap (e.g., see FIG. 15). In step 2314, an isotropic oxide etch is performed to remove a constant thickness of the oxide deposited in step 2308 (see, e.g., FIGS. 16A and 18A). Because the etch is isotropic (i.e., substantially isotropic), all exposed surfaces of the oxide layer must be etched by approximately the same amount. In step 2316, the polysilicon mask is etched by a further amount to expose a new portion of the sidewall of the oxide layer from step 2308 in the gap (see, e.g., FIGS. 17B and 19B) ). In step 2318, it is determined whether the taper of the oxide layer is complete (see, e.g., FIG. 20). For example, this can be determined based on the number of iterations of the oxide etch / poly etch performed. As another example, the iterations of steps 2314 and 2316 may be repeated until the threshold thickness of poly (or no poly) remains (or the poly does not remain). In step 2320, once the tapered field plate dielectric is formed in the trench, polysilicon is deposited in the trench to form the tapered field plate (see, e.g., FIG. 22B). A planarization step may be needed to ensure that the field plate and the surface of the wafer are coplanar. In step 2322, a MOSFET process flow is performed to form the HVFET in the silicon pillar adjacent to the trench containing the tilted field plate.

While the exemplary process 2300 is described with reference to specific materials and layers, it should be understood that some layers may be optional and the materials of the wafers and layers may vary.

The foregoing description of the illustrated examples of the present invention, including those set forth in the summary, is intended to be exhaustive or is not intended to be limited to the concise forms disclosed. Certain embodiments and examples of the invention are described herein for illustrative purposes and various equivalent improvements are possible without departing from the broader spirit and scope of the invention. Indeed, certain exemplary voltages, currents, frequencies, power range values, times, etc., are provided for illustrative purposes, and other values may also be employed within other embodiments and examples consistent with the teachings of the present invention It is understood that.

These improvements may be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope should be determined entirely by the claims below and interpreted according to established principles of claim interpretation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (33)

A method of forming a tapered field plate dielectric region in a semiconductor wafer,
Etching a trench having a sidewall in the semiconductor wafer;
Depositing a first insulating layer of a first thickness on the semiconductor wafer including the sidewall;
Etching said first amount of said first insulating layer such that a first upper portion of said first insulating layer adjacent to the top of said trench is removed; ;
Depositing a second insulating layer of a second thickness on the semiconductor wafer such that the second insulating layer overlaps a portion of the first insulating layer and the second insulating layer overlaps the first upper side portion Depositing the second insulating layer; And
Etching the second amount of the second insulating layer so that the second upper portion of the second insulating layer on the sidewall of the trench is removed; A method of forming a field-plate dielectric region. The method according to claim 1,
Wherein the step of etching the second amount of the second insulating layer exposes at least a portion of the first insulating layer adjacent to the second upper side portion. . The method according to claim 1,
Depositing a third insulating layer of a third thickness on the semiconductor wafer; And
Etching the third amount of the third insulating layer so that the third upper portion of the third insulating layer on the sidewalls of the trench is removed; Wherein the tapered field plate dielectric region is formed in the trench. The method of claim 3,
Wherein etching the third amount of the third insulating layer comprises exposing at least a portion of the first insulating layer adjacent to the third upper side portion and at least a portion of the second insulating layer adjacent the third upper side portion Wherein the tapered field plate dielectric region is formed on the semiconductor wafer. The method according to claim 1,
Wherein the first and second thicknesses are approximately the same. ≪ Desc / Clms Page number 20 > 6. The method of claim 5,
Wherein the first and second insulating layers are the same materials. ≪ Desc / Clms Page number 17 > The method according to claim 1,
Wherein the first thickness is substantially independent of the slope of the surface on which the first insulating layer is deposited. ≪ RTI ID = 0.0 > 11. < / RTI > The method according to claim 1,
Further comprising patterning a hardmask defining the location of the trench prior to etching the trench,
Wherein patterning the hardmask comprises depositing a hard mask material. ≪ Desc / Clms Page number 20 > 9. The method of claim 8,
Wherein the hard mask is formed of polysilicon. ≪ RTI ID = 0.0 > 8. < / RTI > 10. The method of claim 9,
Further comprising depositing a protection layer on the surface of the semiconductor wafer prior to depositing the hard mask. ≪ RTI ID = 0.0 > 11. < / RTI > 11. The method of claim 10,
Wherein the protective layer is an oxide. ≪ RTI ID = 0.0 > 11. < / RTI > The method according to claim 1,
Further comprising the step of depositing a conductive material on the first insulating layer and the second insulating layer in the trench,
Wherein the conductive material is separated from direct contact with the sidewall of the trench by the first insulating layer and the second insulating layer. ≪ Desc / Clms Page number 13 > The method according to claim 1,
Wherein etching the first insulating layer and etching the second insulating layer is performed by anisotropic etching. ≪ Desc / Clms Page number 20 > A method of forming a tapered field plate dielectric region in a semiconductor wafer,
Etching the trench in the semiconductor wafer;
Depositing an insulating layer on the semiconductor wafer including sidewalls of the trench, wherein the insulating layer forms a gap in the trench opened up to the top of the trench; ;
Depositing a mask layer on the insulating layer, the mask layer filling at least a portion of the gap; depositing the mask layer;
Etching a first amount of the mask layer to expose a first sidewall portion of the insulating layer in the gap;
Etching the second amount of the insulating layer, including the first sidewall portion of the insulating layer;
Etching the third portion of the mask layer to expose a second sidewall portion of the insulating layer within the gap, the second sidewall portion being located deeper within the trench than the first sidewall portion; Etching the volume; And
And etching the fourth amount of the insulating layer, including the first side wall portion and the second side wall portion of the insulating layer. 15. The method of claim 14,
Wherein etching the first volume and etching the third volume are performed in a solution comprising hydrofluoric acid. ≪ Desc / Clms Page number 20 > 15. The method of claim 14,
Depositing a conductive material on the insulating layer in the trench; And
And removing a portion of the conductive material outside the trench. ≪ RTI ID = 0.0 > 11. < / RTI > 17. The method of claim 16,
Wherein removing the portion of the conductive material outside the trench comprises performing a chemical mechanical polishing step. ≪ Desc / Clms Page number 20 > 15. The method of claim 14,
Etching the fifth amount of the mask layer to expose a third sidewall portion of the insulating layer in the gap, wherein the third sidewall portion has a depth greater than the first sidewall portion and the second sidewall portion in the trench, Etching said fifth quantity, wherein said fifth quantity is located; And
Etching the sixth amount of the insulating layer, including the first sidewall portion, the second sidewall portion, and the third sidewall portion of the insulating layer, to form a tapered field plate dielectric region / RTI > 15. The method of claim 14,
Wherein the mask layer comprises silicon. ≪ RTI ID = 0.0 > 11. < / RTI > 15. The method of claim 14,
Wherein the insulating layer comprises an oxide. ≪ RTI ID = 0.0 > 8. < / RTI > 15. The method of claim 14,
Further comprising forming an active semiconductor device in the semiconductor wafer adjacent the trench. ≪ RTI ID = 0.0 > 11. < / RTI > 15. The method of claim 14,
Wherein the first amount and the second amount are substantially equal. ≪ RTI ID = 0.0 > 11. < / RTI > 15. The method of claim 14,
Wherein the second amount and the fourth amount are substantially equal. ≪ RTI ID = 0.0 > 11. < / RTI > 24. The method of claim 23,
Wherein the first amount and the second amount are substantially equal. ≪ RTI ID = 0.0 > 11. < / RTI > A method of forming a tapered field plate dielectric region in a semiconductor wafer,
Etching the semiconductor wafer to form a trench therein;
Depositing an insulating layer on the semiconductor wafer, wherein a gap is formed in the insulating layer in the trench after the depositing step; depositing the insulating layer;
Depositing a mask layer on the insulating layer, the mask layer filling at least a portion of the gap; depositing the mask layer; And
Alternately etching portions of the mask layer and the insulating layer in the gap to form a tapered insulating layer in the trench. ≪ Desc / Clms Page number 21 > 26. The method of claim 25,
Wherein etching the mask layer is performed using a solution comprising hydrofluoric acid. ≪ RTI ID = 0.0 > 8. < / RTI > 26. The method of claim 25,
Depositing a conductive material on the insulating layer in the trench; And
And removing a portion of the conductive material outside the trench. ≪ RTI ID = 0.0 > 11. < / RTI > 28. The method of claim 27,
Wherein removing the portion of the conductive material outside the trench comprises performing a chemical mechanical polishing step. ≪ RTI ID = 0.0 > 11. < / RTI > 26. The method of claim 25,
Wherein the mask layer comprises silicon. ≪ RTI ID = 0.0 > 11. < / RTI > 26. The method of claim 25,
Wherein the insulating layer comprises an oxide. ≪ RTI ID = 0.0 > 8. < / RTI > 26. The method of claim 25,
Further comprising forming an active semiconductor device in the semiconductor wafer adjacent the trench. ≪ RTI ID = 0.0 > 11. < / RTI > 26. The method of claim 25,
The step of alternately etching the mask layer and portions of the insulating layer,
Etching a first amount of the mask layer to expose a first sidewall portion of the insulating layer in the gap;
Etching said second amount of said insulating layer, said second amount comprising a first portion of said first sidewall portion of said insulating layer;
Etching the third portion of the mask layer to expose a second sidewall portion of the insulating layer in the gap, wherein the second sidewall portion is located deeper than the first sidewall portion within the trench; Etching the third volume; And
Etching the fourth amount of the insulating layer, wherein the fourth amount comprises a second portion of the first sidewall portion of the insulating layer and a first portion of the second sidewall portion, And forming a tapered field plate dielectric region in the semiconductor wafer. 33. The method of claim 32,
Wherein the second quantity and the fourth quantity are approximately the same and wherein the first quantity and the second quantity are approximately the same.

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