CN118012203A - Band gap reference with high power supply noise resistance - Google Patents

Band gap reference with high power supply noise resistance Download PDF

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Publication number
CN118012203A
CN118012203A CN202410276469.1A CN202410276469A CN118012203A CN 118012203 A CN118012203 A CN 118012203A CN 202410276469 A CN202410276469 A CN 202410276469A CN 118012203 A CN118012203 A CN 118012203A
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tube
nmos tube
electrode
drain electrode
pmos
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CN202410276469.1A
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Inventor
明鑫
姚自宸
吴之久
陈霖民
王卓
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Priority to CN202410276469.1A priority Critical patent/CN118012203A/en
Publication of CN118012203A publication Critical patent/CN118012203A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a band gap reference with high power supply noise resistance. The invention aims to provide a band gap reference with high power supply noise resistance for severe power supply noise in a high-voltage driving circuit, which normally works in a severe noise environment of high-voltage gate driving and provides accurate and stable reference values for a high-voltage gate driving chip. The circuit comprises a starting and paranoid circuit, a pre-power rail generating circuit, a band gap reference core circuit and an operational amplifier for negative feedback clamping, wherein the pre-power rail technology and the feedback technology are utilized to improve the power noise suppression performance of the reference, and the negative feedback clamping of the operational amplifier and the BE junction temperature characteristic of an NPN tube are utilized to generate a reference voltage with high power noise resistance. The invention provides a band-gap reference circuit with high power supply noise resistance, which can normally work in high power supply noise of a high-voltage gate driving system.

Description

Band gap reference with high power supply noise resistance
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a band gap reference with high power supply noise resistance.
Background
Bandgap references are widely used in various fields as a very important part of analog integrated circuits. In a high voltage gate drive chip, the power supply rejection capability of the bandgap reference is important due to the high frequency flipping of the switching node. The band gap reference with strong noise immunity can effectively isolate the influence of a switch node, and is very important for the reliability of a driving chip. Therefore, the band gap reference with high power supply noise resistance is provided to have important significance for the high-voltage gate driving circuit.
Disclosure of Invention
The invention aims to provide a band gap reference with high power supply noise resistance for severe power supply noise in a high-voltage driving circuit, which normally works in a severe noise environment of high-voltage gate driving and provides accurate and stable reference values for a high-voltage gate driving chip.
The technical scheme of the invention is as follows:
A band gap reference with high power noise resistance comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NPN tube, a second NPN tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor;
The grid electrode of the first NMOS tube is connected with the source electrode of the eighth NMOS tube, the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the first NMOS tube is grounded; the grid electrode and the drain electrode of the second NMOS tube are connected with each other, and the source electrode of the second NMOS tube is grounded;
The grid electrode and the drain electrode of the third NMOS tube are interconnected, and the drain electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with a bias signal;
The source electrode of the second PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the second PMOS tube are connected with each other, and the drain electrode of the second PMOS tube is connected with the source electrode of the sixth NMOS tube, the drain electrode and the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the second PMOS tube; the source electrode of the fourth NMOS tube is grounded;
The source electrode of the third PMOS tube is connected with a power supply, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the fifth NMOS tube is grounded after passing through the first resistor;
The source electrode of the fourth PMOS tube is connected with a power supply, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube; the drain electrode and the grid electrode of the seventh NMOS tube are connected with the drain electrode of the fourth PMOS tube and one end of the first capacitor, and the source electrode of the seventh NMOS tube is connected with the drain electrode and the grid electrode of the ninth NMOS tube through the second resistor; the source electrode of the ninth NMOS tube and the other end of the first capacitor are grounded;
the drain electrode of the eighth NMOS tube is connected with the power supply, the grid electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth NMOS tube is connected with the drain electrode and the grid electrode of the tenth NMOS tube through the third resistor, and the source electrode of the tenth NMOS tube is grounded;
The collector of the first NPN tube is connected with the source electrode of the eighth NMOS tube, and the emitter of the first NPN tube is connected with one end of the fourth resistor and the grid electrode of the eighth PMOS tube; the collector of the second NPN tube is connected with the source electrode of the eighth NMOS tube, and the emitter of the second NPN tube is connected with one end of the fifth resistor and the grid electrode of the ninth PMOS tube after passing through the sixth resistor; the other end of the fourth resistor and the other end of the fifth resistor are grounded; one end of the second capacitor is connected with the source electrode of the eighth NMOS tube, and the other end of the second capacitor is grounded;
The source electrode of the fifth PMOS tube is connected with a power supply, the grid electrode of the fifth PMOS tube is connected with a bias signal, the drain electrode of the fifth PMOS tube is connected with the grid electrode and the drain electrode of the eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is grounded;
The source electrode of the sixth PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the sixth PMOS tube are connected with each other, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the twelfth NMOS tube; the grid electrode of the twelfth NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the source electrode of the twelfth NMOS tube is grounded;
The source electrode of the seventh PMOS tube is connected with a power supply, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube; the drain electrode of the eighth PMOS tube is connected with the drain electrode and the grid electrode of the thirteenth NMOS tube and the grid electrode of the fourteenth NMOS tube; the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are grounded;
The source electrode of the tenth PMOS tube is connected with a power supply, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with one end of the third capacitor and the drain electrode of the fifteenth NMOS tube; the other end of the third capacitor is connected with the grid electrode of the fifteenth NMOS tube and the drain electrode of the fourteenth NMOS tube through a seventh resistor; the source electrode of the fifteenth NMOS tube is grounded;
The grid electrode of the sixteenth NMOS tube is connected with the drain electrode of the tenth PMOS tube and one end of the fourth capacitor, the drain electrode of the sixteenth NMOS tube is connected with a load (formed by MP11 and MP 12) to output bias current, the source electrode of the sixteenth NMOS tube is grounded after passing through an eighth resistor and a ninth resistor in sequence, and the other end of the fourth capacitor is grounded;
one end of the fifth capacitor is connected with the source electrode of the sixteenth NMOS tube, and the other end of the fifth capacitor is grounded;
The connection point of the source electrode of the sixteenth NMOS tube, the eighth resistor and the fifth capacitor outputs a reference voltage.
The beneficial effects of the invention are as follows: the invention provides a band-gap reference circuit with high power supply noise resistance, which can normally work in high power supply noise of a high-voltage gate driving system.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of the present invention;
fig. 2 shows a specific circuit structure of the operational amplifier a according to the present invention;
FIG. 3 is a temperature coefficient simulation diagram of a reference voltage according to the present invention;
fig. 4 is a power supply suppression capability simulation diagram of the reference voltage of the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic circuit diagram of a bandgap reference circuit with high power noise immunity according to the present invention. The circuit can be roughly divided into four parts: a start-up and bias-handling circuit, a pre-supply rail generation circuit, a bandgap reference core circuit and an operational amplifier A for negative feedback clamping.
The technical scheme of the invention is as follows: the pre-power rail technology and the feedback technology are utilized to improve the power noise suppression performance of the reference, and the negative feedback clamping of the operational amplifier and the BE junction temperature characteristic of the NPN tube are utilized to generate a reference voltage with high power noise resistance.
The left marked part of fig. 1 is a starting and biasing circuit, the external input signal VB is a biasing signal generated by a power-on module of the whole circuit, and the biasing signal VB is generated first in the power-on process of the chip. The operation of the start-up circuit is as follows. When the chip is not powered on, VPRE is low, MN1 pipe is turned off, and the drain terminal of MN3 is placed at VSS by parasitic capacitance. When the chip is electrified, the bias signal VB enables MP1 to be started, the generated current enables MN2 and MN3 to be started, the drain terminal voltage of MN3 is enabled to be 2VGS, therefore MN6 is enabled to be started, the degeneracy state of the bias circuit is broken, and the bias current flowing through R1 is generated and used as the bias current of the pre-power rail generation circuit. When the pre-power supply rail VPRE is formed, the source terminal of MN3 is pulled down by turning on MN1, so that the gate voltage of MN5 is reduced from 2VGS to VGS, and the source terminal voltage of MN5 is VGS at this time, so that MN5 is turned off and the bias circuit is not affected.
The principle of operation of the pre-power rail generation circuit is as follows. When the bias is generated, the bias current passes through a current mirror composed of MP4, MN7 and MN8, so that VPRE is:
VPRE＝VGS,N10+IMN8×R3
Where V GS,N10 is the gate-source voltage of MN10, I MN8 is the current flowing through MN8, and is determined by the bias current and the aspect ratio of MN7 and MN 8. The pre-supply rail VPRE can be made to a reasonable value by choosing the appropriate width to length ratio of MN10 and the size of R3.
The basic core works as follows. NPN1, NPN2 and R6 generate PTAT currents with positive temperature coefficients. The voltage at the two ends of R6 is the difference between the be junction voltages of NPN1 and NPN2, and the ratio of the emission junction areas of NPN1 and NPN2 is 1:8, PTAT current flowing through R6 is
Thus, the pressure drop across R5 and R6 is
Thus, VREF can be obtained as
According to the temperature coefficients of NPN triode DeltaV BE and V BE, the circuit process can make
Thus, the reference voltage VREF with zero temperature coefficient can be obtained by adjusting the values of R5 and R6.
The operational amplifier a in fig. 1 is used to clamp the A, B two points to prevent the reference voltage from greatly fluctuating when the power supply is dithered. Fig. 2 shows a specific circuit configuration of the operational amplifier a. The specific working principle is as follows. VB is an external bias signal, MP8 and MP9 are input differential pair tubes, and MP7 is a tail current source. The amplifier is a two-stage operational amplifier, and the output of the two-stage operational amplifier is connected with a source follower buffer. The first stage of the operational amplifier is a differential pair transistor of a current mirror load, and the second stage is an NMOS common source amplifier. In order to meet the phase margin requirement, a miller compensation is employed between the first stage and the second stage, and R7 is used to compensate the secondary dominant pole of C3 at the second stage output node. The output of the second-stage operational amplifier is connected with a source follower, the resistors R8 and R9 are a poly resistor and a well resistor respectively, and the two resistors have different temperature characteristics, so that a temperature-independent current IREF can be generated, and the current IREF is used as bias current of other modules through current mirrors MN11 and MN 12.
The high power supply noise resistance of the invention mainly comes from the existence of the pre-power supply rail, when the power supply voltage generates a disturbance, as the pre-power supply rail VPRE is the source electrode of the MN8 pipe, only a small part of noise is coupled to the VPRE, and the existence of C1 and C2 acts as the filter capacitance to absorb most of power supply noise, the VPRE is very stable under the interference of the power supply noise, and a very clean reference voltage VREF can be obtained at the moment. Fig. 4 is a simulation diagram of the power supply rejection power PSR of the present invention, and it can be seen that the low frequency PSR is worst-76 dB and the high frequency PSR is worst-30 dB. The structure of the invention has the advantage of greatly improving the power supply noise resistance of the reference voltage.
As shown in fig. 3, a temperature coefficient simulation diagram of the reference voltage of the present invention is shown.
According to the formula
The temperature coefficient of the present invention is 2.5 ppm/. Degree.C (tt) to 10.12 ppm/. Degree.C (ss).

Claims (1)

1. The band gap reference with high power supply noise resistance is characterized by comprising a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NPN tube, a second NPN tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor;
The grid electrode of the first NMOS tube is connected with the source electrode of the eighth NMOS tube, the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the first NMOS tube is grounded; the grid electrode and the drain electrode of the second NMOS tube are connected with each other, and the source electrode of the second NMOS tube is grounded;
The grid electrode and the drain electrode of the third NMOS tube are interconnected, and the drain electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with a bias signal;
The source electrode of the second PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the second PMOS tube are connected with each other, and the drain electrode of the second PMOS tube is connected with the source electrode of the sixth NMOS tube, the drain electrode and the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the second PMOS tube; the source electrode of the fourth NMOS tube is grounded;
The source electrode of the third PMOS tube is connected with a power supply, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the fifth NMOS tube is grounded after passing through the first resistor;
The source electrode of the fourth PMOS tube is connected with a power supply, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube; the drain electrode and the grid electrode of the seventh NMOS tube are connected with the drain electrode of the fourth PMOS tube and one end of the first capacitor, and the source electrode of the seventh NMOS tube is connected with the drain electrode and the grid electrode of the ninth NMOS tube through the second resistor; the source electrode of the ninth NMOS tube and the other end of the first capacitor are grounded;
the drain electrode of the eighth NMOS tube is connected with the power supply, the grid electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth NMOS tube is connected with the drain electrode and the grid electrode of the tenth NMOS tube through the third resistor, and the source electrode of the tenth NMOS tube is grounded;
The collector of the first NPN tube is connected with the source electrode of the eighth NMOS tube, and the emitter of the first NPN tube is connected with one end of the fourth resistor and the grid electrode of the eighth PMOS tube; the collector of the second NPN tube is connected with the source electrode of the eighth NMOS tube, and the emitter of the second NPN tube is connected with one end of the fifth resistor and the grid electrode of the ninth PMOS tube after passing through the sixth resistor; the other end of the fourth resistor and the other end of the fifth resistor are grounded; one end of the second capacitor is connected with the source electrode of the eighth NMOS tube, and the other end of the second capacitor is grounded;
The source electrode of the fifth PMOS tube is connected with a power supply, the grid electrode of the fifth PMOS tube is connected with a bias signal, the drain electrode of the fifth PMOS tube is connected with the grid electrode and the drain electrode of the eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is grounded;
The source electrode of the sixth PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the sixth PMOS tube are connected with each other, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the twelfth NMOS tube; the grid electrode of the twelfth NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the source electrode of the twelfth NMOS tube is grounded;
The source electrode of the seventh PMOS tube is connected with a power supply, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube; the drain electrode of the eighth PMOS tube is connected with the drain electrode and the grid electrode of the thirteenth NMOS tube and the grid electrode of the fourteenth NMOS tube; the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are grounded;
The source electrode of the tenth PMOS tube is connected with a power supply, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with one end of the third capacitor and the drain electrode of the fifteenth NMOS tube; the other end of the third capacitor is connected with the grid electrode of the fifteenth NMOS tube and the drain electrode of the fourteenth NMOS tube through a seventh resistor; the source electrode of the fifteenth NMOS tube is grounded;
The grid electrode of the sixteenth NMOS tube is connected with the drain electrode of the tenth PMOS tube and one end of the fourth capacitor, the drain electrode of the sixteenth NMOS tube is connected with a load to output bias current, the source electrode of the sixteenth NMOS tube is grounded after passing through the eighth resistor and the ninth resistor in sequence, and the other end of the fourth capacitor is grounded;
one end of the fifth capacitor is connected with the source electrode of the sixteenth NMOS tube, and the other end of the fifth capacitor is grounded;
The connection point of the source electrode of the sixteenth NMOS tube, the eighth resistor and the fifth capacitor outputs a reference voltage.
CN202410276469.1A 2024-03-12 2024-03-12 Band gap reference with high power supply noise resistance Pending CN118012203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410276469.1A CN118012203A (en) 2024-03-12 2024-03-12 Band gap reference with high power supply noise resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410276469.1A CN118012203A (en) 2024-03-12 2024-03-12 Band gap reference with high power supply noise resistance

Publications (1)

Publication Number Publication Date
CN118012203A true CN118012203A (en) 2024-05-10

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ID=90956045

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410276469.1A Pending CN118012203A (en) 2024-03-12 2024-03-12 Band gap reference with high power supply noise resistance

Country Status (1)

Country Link
CN (1) CN118012203A (en)

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