CN113220057A - High-noise-resistance floating band-gap reference source - Google Patents

High-noise-resistance floating band-gap reference source Download PDF

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CN113220057A
CN113220057A CN202110428075.XA CN202110428075A CN113220057A CN 113220057 A CN113220057 A CN 113220057A CN 202110428075 A CN202110428075 A CN 202110428075A CN 113220057 A CN113220057 A CN 113220057A
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tube
electrode
resistor
nmos tube
nmos
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CN113220057B (en
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明鑫
张永瑜
叶自凯
王卓
张波
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a high-noise-resistance floating band-gap reference source. The circuit comprises a starting and biasing part, a floating band gap reference core circuit and a negative feedback operational amplifier clamping part, the suppression performance of the reference on power supply noise is improved by utilizing a pre-power supply rail technology and a feedback technology, a reference voltage value for power supply reference is generated through the relation between triode emitter junction voltage and temperature, and finally the high anti-noise reference voltage value for power supply reference is converted into reference voltage for ground reference through a negative feedback operational amplifier. The circuit has the capability of working in a severe noise environment driven by the high-voltage grid, and can provide a stable reference value for a high-voltage grid driving system.

Description

High-noise-resistance floating band-gap reference source
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a high-noise-resistance floating band-gap reference source.
Background
Bandgap reference sources are widely used in various fields of analog integrated circuits. In the high-voltage gate driving, due to huge noise caused by violent switching action and harsh process conditions, the design of the band gap reference source is more exquisite. In contrast to the power supply rejection performance of bandgap reference sources in general systems, the effect of ground noise on the reference voltage should also be of concern in high-voltage gate drive systems. As shown in fig. 1, the floating bandgap reference structure can effectively isolate noise of power and ground. A good bandgap reference source can give the whole gate drive system good performance. Therefore, in a severe working environment of high-voltage grid driving, the realization of the high-noise-resistant band-gap reference source has important significance.
Disclosure of Invention
The present invention is directed to solve the above problems, and an object of the present invention is to provide a floating reference source circuit with high noise immunity, which has the capability of operating in a noisy environment with poor high-voltage gate driving, and can provide a stable reference value for a high-voltage gate driving system.
The technical scheme of the invention is as follows:
a high noise-resistant floating band-gap reference source is shown in figure 2 and comprises a first LDPMOS tube, a second LDPMOS tube, a third LDPMOS tube, a first LDNMOS tube, a second LDNMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, an NPN tube, a first PNP tube, a second PNP tube, a first Zener diode and a second Zener diode; wherein the content of the first and second substances,
the source electrode of the first LDPMOS tube is connected with the power supply, and the grid electrode of the first LDPMOS tube is interconnected with the drain electrode of the first LDPMOS tube; the source electrode of the second LDPMOS tube is connected with the power supply, and the grid electrode of the second LDPMOS tube is connected with the drain electrode of the first LDPMOS tube; the source electrode of the third LDPMOS tube is connected with the power supply, and the grid electrode of the third LDPMOS tube is connected with the drain electrode of the first LDPMOS tube;
the drain electrode of the first LDNMOS tube is connected with the drain electrode of the first LDPMOS tube, the grid electrode of the first LDNMOS tube is connected with the power supply after passing through the first resistor, and the source electrode of the first LDNMOS tube is grounded after passing through the second resistor; the drain electrode of the second LDNMOS tube is connected with the drain electrode of the first LDPMOS tube, the grid electrode of the second LDNMOS tube is connected with the drain electrode of the second LDPMOS tube, and the source electrode of the second LDNMOS tube is grounded after passing through the third resistor and the second resistor in sequence; the connection point of the grid electrode of the second LDNMOS tube and the drain electrode of the second LDPMOS tube is grounded through a first capacitor;
the drain electrode of the first NMOS tube is connected with a power supply through a first resistor, the grid electrode of the first NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the first NMOS tube is grounded; the connection point of the drain electrode of the first NMOS tube and the first resistor is connected with the cathode of the first Zener diode, and the anode of the first Zener diode is grounded;
the drain electrode of the second NMOS tube is connected with the drain electrode of the second LDPMOS tube, the grid electrode of the second NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the second NMOS tube is grounded;
the collector of the NPN tube is connected with the power supply, the base of the NPN tube is connected with the cathode of the second Zener diode, and the anode of the second Zener diode is grounded;
the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third LDPMOS tube, and the grid electrode of the fourth NMOS tube is connected with the emitting electrode of the NPN tube; the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the collector electrode of the first PNP tube, and the source electrode of the third NMOS tube is grounded;
the drain electrode of the fifth NMOS tube is connected with the emitting electrode of the NPN tube, the grid electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is connected with the negative electrode of the second capacitor, and the positive electrode of the second capacitor is connected with the collector electrode of the first PNP tube;
the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the sixth NMOS tube is grounded;
the drain electrode of the seventh NMOS tube is connected with the collector electrode of the first PNP tube, the grid electrode of the seventh NMOS tube is connected with the collector electrode of the second PNP tube, and the source electrode of the seventh NMOS tube is grounded;
the emitter of the first PNP tube is connected with the emitter of the NPN tube through a fourth resistor, and the base of the first PNP tube is connected with the drain of the third PMOS tube; an emitter of the second PNP tube is connected with an emitter of the NPN tube after passing through the fifth resistor and the fourth resistor in sequence, and a base of the second PNP tube is connected with a drain of the third PMOS tube;
the drain electrode of the eighth NMOS tube is connected with the collector electrode of the second PNP tube, the grid electrode and the drain electrode of the eighth NMOS tube are interconnected, and the source electrode of the eighth NMOS tube is grounded;
the source electrode of the first PMOS tube is connected with the emitting electrode of the NPN tube through a sixth resistor, and the grid electrode of the first PMOS tube is connected with the drain electrode of the third PMOS tube; the source electrode of the second PMOS tube is connected with the emitting electrode of the NPN tube through a sixth resistor, and the grid electrode of the second PMOS tube is connected with the emitting electrode of the NPN tube through a ninth resistor;
the drain electrode of the ninth NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode and the drain electrode of the ninth NMOS tube are interconnected, and the source electrode of the ninth NMOS tube is grounded; the drain electrode of the tenth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the tenth NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the tenth NMOS tube is grounded;
the source electrode of the third PMOS tube is connected with the emitting electrode of the NPN tube through a seventh resistor, and the grid electrode of the third PMOS tube is connected with the emitting electrode of the NPN tube through a ninth resistor;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the eleventh NMOS tube is connected with the drain electrode of the second PMOS tube, and a third capacitor and an eighth resistor are connected between the drain electrode and the grid electrode of the eleventh NMOS tube;
and the connection points of the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the ninth resistor are grounded through a fourth resistor.
The invention has the beneficial effects that: a floating reference source circuit with high noise resistance is provided, which can stably work under a high-voltage grid driving system.
Drawings
FIG. 1 is a basic floating bandgap reference structure;
FIG. 2 is a schematic diagram of the circuit configuration of the present invention;
FIG. 3 is a schematic view of the high noise immunity principle of the present invention;
FIG. 4 is a graph of a reference voltage temperature coefficient simulation of the present invention;
fig. 5 is a simulation diagram of the suppression effect of the reference voltage on the ground/power supply noise according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
fig. 2 shows a complete circuit structure of the high noise immunity floating bandgap reference source proposed by the present invention. The circuit may be roughly divided into three parts: the circuit comprises a starting and biasing part, a floating band-gap reference core circuit, a negative feedback operational amplifier clamping part and a ground reference generating part.
The working principle of the invention is as follows: the method comprises the steps of improving the suppression performance of a reference on power supply noise by utilizing a pre-power-supply rail technology and a feedback technology, generating a reference voltage value for power supply reference through the relation between triode emitter junction voltage and temperature, and finally converting the high anti-noise reference voltage value for power supply reference into a reference voltage for ground reference through a negative feedback operational amplifier.
The left-hand portion of fig. 2 is labeled as a start-up circuit, which operates as follows. When the chip is not powered on, the source end of the MNH1 is connected to the ground through the R2, the initial potential is 0, when VCC starts to be powered on, the gate end of the MNH1 is pulled high, the MNH1 tube is opened, the branch where the high-voltage LDPMOS tube MPH1 is located is powered on, at the moment, the MPH1, the MPH2 and the MNH2 form a positive feedback loop to accelerate the power on of a bias part, the grids of the MN2 and the MNH2 are all pulled high, but at the moment, the MN2 tube does not reach the threshold value. As the current continues to increase, MN1, MN2 turn on, start to decrease the gate voltage of MNH2, gradually cut off the start-up branch, and negative feedback loops MN1, MNH2 are formed, gradually stabilizing the bias circuit current. Bias module is VGSthe/R type generates a fixed bias current, and the voltage at the grid end of the MN2 is taken as a bias voltage to be led to other parts for biasing. The capacitor C1 is a compensation capacitor for reducing the dominant pole frequency and preventing the coupling of the high frequency noise signal with the large bandwidth. The Zener tube Z1 is used for clamping pressure in the starting process, and the gate end of the MNH1 tube is protected to prevent gate oxide from breaking down. The MPH3 forms a high voltage current mirror with the MPH1 for powering the back side circuitry. The voltage regulator is used for VGS clamping protection inside the bias circuit and high voltage resistance of the high voltage tube VDS, so that the circuit can safely work when being powered on quickly.
The internal power supply rail of the floating band-gap reference is powered by NPN, and the current is amplified by the NPN to supply power to the floating reference core part and the negative feedback clamping operational amplifier part. The pre-power rail technology is adopted, so that the performance of inhibiting power supply noise by reference voltage is improved, wherein the pre-power rail voltage is as follows:
Figure BDA0003030311310000041
the band-gap reference core circuit works as follows. The PNP1, PNP2, and R5 generate a positive temperature PTAT current. The pressure drop across R5 is the difference between the two tubes Veb. The current flowing through R5 is set to PNP2: PNP 1: 8:1
Figure BDA0003030311310000042
Since MN8 and MN9 constitute a current mirror, the positive temperature PTAT voltage at R4 can be obtained as
Figure BDA0003030311310000043
V due to PNPEBFor a negative temperature dependent voltage, then from the NPN emitter to the base of PNP1 and PNP2, a floating reference voltage value can be obtained:
Figure BDA0003030311310000044
according to the circuit process NPN triode delta VbeAnd VbeTemperature coefficient of (2):
Figure BDA0003030311310000045
the floating band-gap reference voltage V irrelevant to the temperature can be obtained by adjusting the resistance value of the resistor according to the proportionality coefficient of the formularef. The floating band-gap reference is obtained by referring to a relatively clean pre-power supply rail, and the bottom NMOS tubes MN7 and MN8 isolate ground noise, so that the floating band-gap reference has good noise resistance.
The band-gap reference voltage circuit is provided with a negative feedback loop for stabilizing the reference value of the floating voltage and preventing the reference value from generating large fluctuation when the power supply shakes or the load changes. The invention is mainlyThe negative feedback loop is composed of MN3, MN4, NPN, R4 and PNP1 and used for ensuring the stability of the loop, and the positive feedback loop is composed of MN3, MN4, NPN, R1, PNP2, MN7 and MN8 and used for establishing the state of the acceleration reference. Meanwhile, a small loop formed by MN4 and NPN is introduced into the pre-power rail generation part and used for stabilizing the voltage of the pre-power rail. The use of the zener diodes Z2 and Z3 protects the tubes from breakdown during firing. When V isrefWhen the voltage value is disturbed to change, V is quickly adjusted through the action of a negative feedback looprefAnd (5) pulling back to the original value. The capacitor C2 is used for frequency stability compensation of a negative feedback loop, and because the junction capacitance between the lower plate of the C2 and the substrate has leakage at high temperature, the leakage can be introduced into a reference core or a feedback circuit, MN5 and MN6 tubes are introduced, and an MN6 source follower formed by MN5 absorbs the leakage of the parasitic capacitance of the C2 at high temperature, and simultaneously eliminates a zero point of a right half plane caused by the C2 as Miller capacitance.
MP1, MP2, MP3, MN9, MN10, MN11, R6, R7, R8 and C3 form a clamping negative feedback operational amplifier for transferring the voltage value of the floating reference core to the ground reference to facilitate the subsequent voltage comparison, and the high noise-resistant principle of the invention is shown in FIG. 3, wherein V isrefThe voltage of the reference structure is a floating reference voltage value, is obtained by referring to a pre-power rail, when a power tube is switched, high-frequency common mode noise is generated on the ground due to instant large current passing through a parasitic inductance connected with the ground, and at the moment, the floating reference value generated by the reference structure is not interfered (the high-voltage noise of the floating reference is obtained by transmitting ground noise through a MOS1:1 in a diode connection mode formed by MN3 under high frequency, and the low-voltage noise is obtained by transmitting ground noise through a MOS1:1 in a diode connection mode formed by MN11 under high frequency, so that the difference value can be offset to the ground noise). When the high-frequency noise disappears, a reference feedback loop is established, and the ground reference voltage can be compared with the floating reference voltage value through a clamp negative feedback operational amplifier to obtain a clean ground output reference voltage.
FIG. 4 shows the stability factor of the floating reference voltage according to the present invention
According to the formula:
Figure BDA0003030311310000051
the temperature coefficient obtained was 22.46 ppm/. degree.C
As shown in fig. 5, in order to output the gain of the reference after adding the small signal interference source to the ground, it can be seen that the ground noise can be effectively isolated in the low frequency band.

Claims (1)

1. A high noise-resistant floating band-gap reference source is characterized by comprising a first LDPMOS (laser diode channel metal oxide semiconductor) tube, a second LDPMOS tube, a third LDPMOS tube, a first LDNMOS (laser diode channel metal oxide semiconductor) tube, a second LDNMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, an NPN (negative-positive-negative-positive-negative) transistor, a first PNP tube, a second PNP tube, a first Zener diode and a second Zener diode; wherein the content of the first and second substances,
the source electrode of the first LDPMOS tube is connected with the power supply, and the grid electrode of the first LDPMOS tube is interconnected with the drain electrode of the first LDPMOS tube; the source electrode of the second LDPMOS tube is connected with the power supply, and the grid electrode of the second LDPMOS tube is connected with the drain electrode of the first LDPMOS tube; the source electrode of the third LDPMOS tube is connected with the power supply, and the grid electrode of the third LDPMOS tube is connected with the drain electrode of the first LDPMOS tube;
the drain electrode of the first LDNMOS tube is connected with the drain electrode of the first LDPMOS tube, the grid electrode of the first LDNMOS tube is connected with the power supply after passing through the first resistor, and the source electrode of the first LDNMOS tube is grounded after passing through the second resistor; the drain electrode of the second LDNMOS tube is connected with the drain electrode of the first LDPMOS tube, the grid electrode of the second LDNMOS tube is connected with the drain electrode of the second LDPMOS tube, and the source electrode of the second LDNMOS tube is grounded after passing through the third resistor and the second resistor in sequence; the connection point of the grid electrode of the second LDNMOS tube and the drain electrode of the second LDPMOS tube is grounded through a first capacitor;
the drain electrode of the first NMOS tube is connected with a power supply through a first resistor, the grid electrode of the first NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the first NMOS tube is grounded; the connection point of the drain electrode of the first NMOS tube and the first resistor is connected with the cathode of the first Zener diode, and the anode of the first Zener diode is grounded;
the drain electrode of the second NMOS tube is connected with the drain electrode of the second LDPMOS tube, the grid electrode of the second NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the second NMOS tube is grounded;
the collector of the NPN tube is connected with the power supply, the base of the NPN tube is connected with the cathode of the second Zener diode, and the anode of the second Zener diode is grounded;
the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third LDPMOS tube, and the grid electrode of the fourth NMOS tube is connected with the emitting electrode of the NPN tube; the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the collector electrode of the first PNP tube, and the source electrode of the third NMOS tube is grounded;
the drain electrode of the fifth NMOS tube is connected with the emitting electrode of the NPN tube, the grid electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is connected with the negative electrode of the second capacitor, and the positive electrode of the second capacitor is connected with the collector electrode of the first PNP tube;
the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the sixth NMOS tube is grounded;
the drain electrode of the seventh NMOS tube is connected with the collector electrode of the first PNP tube, the grid electrode of the seventh NMOS tube is connected with the collector electrode of the second PNP tube, and the source electrode of the seventh NMOS tube is grounded;
the emitter of the first PNP tube is connected with the emitter of the NPN tube through a fourth resistor, and the base of the first PNP tube is connected with the drain of the third PMOS tube; an emitter of the second PNP tube is connected with an emitter of the NPN tube after passing through the fifth resistor and the fourth resistor in sequence, and a base of the second PNP tube is connected with a drain of the third PMOS tube;
the drain electrode of the eighth NMOS tube is connected with the collector electrode of the second PNP tube, the grid electrode and the drain electrode of the eighth NMOS tube are interconnected, and the source electrode of the eighth NMOS tube is grounded;
the source electrode of the first PMOS tube is connected with the emitting electrode of the NPN tube through a sixth resistor, and the grid electrode of the first PMOS tube is connected with the drain electrode of the third PMOS tube; the source electrode of the second PMOS tube is connected with the emitting electrode of the NPN tube through a sixth resistor, and the grid electrode of the second PMOS tube is connected with the emitting electrode of the NPN tube through a ninth resistor;
the drain electrode of the ninth NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode and the drain electrode of the ninth NMOS tube are interconnected, and the source electrode of the ninth NMOS tube is grounded; the drain electrode of the tenth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the tenth NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the tenth NMOS tube is grounded;
the source electrode of the third PMOS tube is connected with the emitting electrode of the NPN tube through a seventh resistor, and the grid electrode of the third PMOS tube is connected with the emitting electrode of the NPN tube through a ninth resistor;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the eleventh NMOS tube is connected with the drain electrode of the second PMOS tube, and a third capacitor and an eighth resistor are connected between the drain electrode and the grid electrode of the eleventh NMOS tube;
and the connection points of the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the ninth resistor are grounded through a fourth resistor.
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CN116841342A (en) * 2023-07-27 2023-10-03 电子科技大学 Anti-noise band gap reference source suitable for GaN half-bridge gate driving system

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CN116841342B (en) * 2023-07-27 2024-03-26 电子科技大学 Anti-noise band gap reference source suitable for GaN half-bridge gate driving system

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