CN105388953A - Band-gap reference voltage source with high power rejection ratio - Google Patents
Band-gap reference voltage source with high power rejection ratio Download PDFInfo
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- CN105388953A CN105388953A CN201510603170.3A CN201510603170A CN105388953A CN 105388953 A CN105388953 A CN 105388953A CN 201510603170 A CN201510603170 A CN 201510603170A CN 105388953 A CN105388953 A CN 105388953A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract
The invention discloses a band-gap reference voltage source with the high power rejection ratio. The band-gap reference voltage source comprises a voltage self-adjustment circuit, a starting circuit, a first-order temperature compensation reference voltage generating circuit, an error amplifier, a bias voltage generating circuit and a reference starting circuit. According to the band-gap reference voltage source, power noise is inhibited to a certain degree through the voltage self-adjustment circuit, then power is supplied to a back-stage band-gap reference circuit, the noise is further inhibited through the band-gap reference circuit, and therefore the whole power source has the quite high power rejection ratio. In addition, the voltage self-adjustment circuit further comprises a feedback loop, an output current can be automatically adjusted, and the problem that as the current required by the back-stage circuit is increased suddenly, the whole circuit is unstable is solved; meanwhile, the power rejection ratio of the band-gap reference voltage source can be increased; compared with a traditional band-gap reference voltage source, stability is better, the power rejection ratio is higher, and the band-gap reference voltage source can meet high-accuracy working requirements.
Description
Technical field
The present invention relates to the reference voltage source for radio frequency, Digital Analog Hybrid Circuits, especially a kind of bandgap voltage reference with high PSRR.
Background technology
Along with the fast development of system integration technology, reference voltage source has become indispensable basic circuit module in digital-to-analog circuit, is widely used in telecommunication circuit, storer, sensor field.The effect of reference voltage source is mainly to provide stable reference voltage to other modules in circuit, and the stability of reference voltage source is directly connected to the duty of circuit and the performance of circuit.In order to meet the normal job requirement of circuit under different external environment, reference voltage source should have the advantages such as stable output, antijamming capability is strong, temperature coefficient is little, conventional reference voltage source mainly contains zener diode voltage source and bandgap voltage reference two kinds in the prior art, bandgap voltage reference is owing to being based upon in the band gap mechanism on non-surface, therefore have better stability, range of application is also more extensive.
In general circuit design, bandgap voltage reference adopts bipolar device to realize usually, base-launch site voltage the VBE of bipolar transistor is the voltage of a negative temperature coefficient, under two different current densities are biased, the difference Δ VBE of two base-launch site voltages is amounts of positive temperature coefficient (PTC), VBE and Δ VBE is combined in certain proportion, the voltage of a nearly zero-temperature coefficient can be produced, this voltage is exactly bandgap voltage reference, according to different designing requirements, bandgap voltage reference is about 1.25V to 10V.But, the noise effect of amplifier, power supply, resistance is inevitably subject in bandgap voltage reference, limit the application of bandgap voltage reference power supply in high precision field, in order to address this problem, the method usually adopted is improve the Power Supply Rejection Ratio of bandgap voltage reference power supply.Power Supply Rejection Ratio is the ratio of input power variable quantity and output voltage variable quantity, and this parameter has reacted the noise signal much variable quantities of corresponding generation in the output signal, and Power Supply Rejection Ratio is higher, and the suppression of indication circuit to noise is stronger.In the application scenario of high-speed, high precision, need the Power Supply Rejection Ratio of bandgap voltage reference very high, with the impact of restraint speckle signal on output signal.
Traditional independent bandgap voltage reference suppresses mainly through circuit medial error amplifier for low-frequency noise signal, HF noise signal is suppressed mainly through RC filtering, and the suppression of noise for intermediate frequency, then need to improve loop bandwidth and reduce to export RC bandwidth, the power consumption of bandgap voltage reference can be caused like this to increase, structure is more complicated, higher to the requirement of its manufacture craft.
Summary of the invention
Goal of the invention: for solving the problems of the technologies described above, one is provided to have low-power consumption, high PSRR, stable performance and the simple reference voltage source of structure, the present invention proposes a kind of bandgap voltage reference with high PSRR, adopt self-regulating votage circuit to carry out first time to power supply noise to suppress, and the voltage signal after suppressing is produced circuit as power supply signal input single order temperature compensated reference, single order temperature compensated reference produces circuit and carries out second time suppression to power supply noise, the mode of the present invention by self-regulating votage technology is combined with bandgap voltage reference technique for temperature compensation, effectively can improve the Power Supply Rejection Ratio of bandgap voltage reference, make bandgap voltage reference can adapt to high-precision application demand.
Technical scheme: for solving the problems of the technologies described above, realize above-mentioned technique effect, the present invention proposes a kind of bandgap voltage reference with high PSRR, comprise direct voltage source Vdd, single order temperature compensated reference produces circuit 3, error amplifier 4, bias-voltage generating circuit 5 and benchmark start-up circuit 6, also comprise self-regulating votage circuit 1 and start-up circuit 2; Direct voltage source Vdd provides supply voltage for described bandgap voltage reference; Self-regulating votage circuit 1 is using direct voltage source voltage Vdd as starting potential signal, receive the biasing voltage signal that bias-voltage generating circuit 5 exports, carrying out first time according to biasing voltage signal to the noise in starting potential suppresses generation first to suppress signal, and suppresses signal to input the power supply voltage signal input end of single order temperature compensated reference generation circuit 3, error amplifier 4, bias-voltage generating circuit 5 and benchmark start-up circuit 6 respectively by first; Described start-up circuit 2 is using direct voltage source voltage Vdd as starting potential signal, be connected with bias-voltage generating circuit 5 with self-regulating votage circuit 1 respectively simultaneously, when self-regulating votage circuit 1 works, start-up circuit 2 ends, when self-regulating votage circuit 1 quits work, start-up circuit 2 conducting, control voltage self-regulation circuit 1 is started working; Single order temperature compensated reference produces circuit 3 and is connected with error amplifier 4, amplifier bias voltage signal is provided to error amplifier 4, receive the regulated voltage signal that error amplifier 4 exports simultaneously, and regulation voltage signal is converted into the electric current of zero-temperature coefficient, and then generation reference voltage, reference voltage is as the output signal of described bandgap voltage reference; Single order temperature compensated reference produces circuit 3 and is connected with benchmark start-up circuit 6 simultaneously, receives the benchmark starting current signal that benchmark start-up circuit 6 exports, and starts offset signal to benchmark start-up circuit 6 input; Error amplifier 4 is connected with bias-voltage generating circuit 5, to bias-voltage generating circuit 5 input voltage regulation signal.
As decision design, self-regulating votage circuit 1 comprises: PMOS MP1a, MP2, MP3 and NMOS tube MN1a, MN1b, MN2; Wherein, the source electrode of MP1a with MP2 is connected, and its tie point is connected with direct supply Vdd; The grid of MP1a is connected with the grid of MP2, and the grid of MP1a is connected with drain electrode simultaneously, and the drain electrode of MP1a is connected with the drain electrode of MN1a; The drain electrode of MP2 is connected with the source electrode of MP3, and tie point suppresses signal output part as first of described self-regulating votage circuit 1, and this tie point is connected with the drain electrode of MN2 simultaneously; The grid of MP3 is as the second offset signal input end of self-regulating votage circuit 1, and the drain electrode of MP3 is connected with the grid of MN2 and is connected with the drain electrode of MN1b simultaneously; The source grounding of MN2, MN1a, MN1b; The grid of MN1a with MN1b is connected, and its tie point is as the first offset signal input end of self-regulating votage circuit 1; Self-regulating votage circuit 1 is connected with bias-voltage generating circuit 5 with the second offset signal input end by the first offset signal input end, receives the first biasing voltage signal and second biasing voltage signal of bias-voltage generating circuit 5 output.
Further, described self-regulating votage circuit 1 also comprises a backfeed loop, and backfeed loop comprises: PMOS MP1b, MP12 and NMOS tube MN3a and MN3b; The source electrode of MP1b with MP12 is all connected with direct supply Vdd, and the grid of MP1b is connected with the grid of MP1a, and the drain electrode of MP1b is connected with the drain electrode of MN3a and is connected with the grid of MN3a simultaneously; The grid of MN3a is connected with the grid of MN3b, and the source electrode of MN3a and MN3b is connected and tie point is connected with the drain electrode of MP2 with MN2; The drain electrode of MN3b is connected with the grid of MP2 and is connected with draining with the grid of MP12 simultaneously; Wherein MP12 and MP3b forms a feedback amplifier, MP1b and MN3a provides bias current for MN3b; The change of self-regulating votage circuit 1 output current controls within the specific limits by backfeed loop, avoids late-class circuit because the electric current of input changes suddenly cause cisco unity malfunction.
As preferably, described start-up circuit 2 comprises NMOS tube MN4, MN5 and resistance R1; One end of R1 is connected with direct supply Vdd, the other end is connected with the grid of MN5, the grid of MN5 is connected with the drain electrode of MN4 simultaneously, the drain electrode of MN5 is connected with the drain junction of MP1a with MN1a in self-regulating votage circuit 1, the source ground of MN5, the grid of MN4 is connected with the first offset signal input end of self-regulating votage circuit 1, the source ground of MN4.
As preferably, described single order temperature compensated reference produces circuit 3 and comprises: PMOS MP4a, MP4b, MP6, MP7, resistance R2, R3a, R3b, R4 and NPN pipe Q1, Q2, Q3, the source electrode of MP4a, MP4b, MP6, MP7 is connected, and tie point is the first suppression signal that described single order temperature compensated reference produces first input end receiver voltage self-regulation circuit 1 output of circuit 3, the grid of MP4a, MP4b, MP6 is connected, its tie point is the regulated voltage signal that described single order temperature compensated reference produces the 3rd input end reception error amplifier 4 output of circuit 3, this regulated voltage signal is converted to the electric current of zero-temperature coefficient by MP4a, MP4b, MP6, and then produces reference voltage by resistance R4, the drain electrode of MP4a is connected with the in-phase input end of described error amplifier 4, its tie point is that the 3rd output terminal of described single order temperature compensated reference generation circuit 3 is connected with error amplifier 4 in-phase input end, the drain electrode of MP4a is connected with resistance R3a with R2 simultaneously, the other end ground connection of R3a, the other end of R2 is connected with the collector of NPN pipe Q1, the collector of Q1 is connected with base stage, grounded emitter, the drain electrode of MP4b is connected with the inverting input of described error amplifier 4, its tie point is that the 4th output terminal of described single order temperature compensated reference generation circuit 3 is connected with the inverting input of error amplifier 4, the drain electrode of MP4b is connected with the collector of NPN pipe Q2, the collector of Q2 is connected with base stage, grounded emitter, the drain electrode of MP4b is connected with one end of resistance R3b, its tie point is the benchmark starting current signal that described single order temperature compensated reference produces the second input end reception benchmark start-up circuit 6 output of circuit 3, the other end ground connection of R3b, the drain electrode of MP4b is connected with the base stage of NPN pipe Q3, the drain electrode of MP6 is by resistance R4 ground connection, and the tie point of MP6 and R4 is the 5th output terminal that described single order temperature compensated reference produces circuit 3, as the reference voltage output end of described bandgap voltage reference, the base stage of MP7 is connected with drain electrode, its tie point is that described single order temperature compensated reference produces the first output terminal of circuit 3 to start-up circuit 6 output startup offset signal, the drain electrode of MP7 is connected with the collector of NPN pipe Q3, tie point is the second output terminal of described single order temperature compensated reference generation circuit 3 is that error amplifier 4 is powered, the grounded emitter of Q3.
As preferably, error amplifier 4 comprises PMOS MP10a, MP10b, MP11a, MP11b, NPN pipe Q4, Q5, NMOS tube MN7a, MN7b, MN8a, MN8b and electric capacity C1; The source electrode of MP10a, MP10b, MP11a, MP11b is connected, and what its tie point exported as the first input end receiver voltage self-regulation circuit 1 of error amplifier 4 first suppresses signal as supply voltage; The grid of MP10a, MP10b is connected, and its tie point receives as the second input end of error amplifier 4 supply voltage that single order temperature compensated reference produces circuit 3 output; The drain electrode of MP10a is connected with the collector of NPN pipe Q4, is connected with the drain electrode of NMOS tube MN8b simultaneously; The drain electrode of MP10b is connected with the collector of NPN pipe Q5, is connected with the drain electrode of NMOS tube MN7a simultaneously; NPN pipe Q4 with Q5 is that common emitter is connected, and tie point ground connection, and the base stage of Q4 is as the inverting input of error amplifier 4, and the base stage of Q5 is as the in-phase input end of error amplifier 4; The drain electrode of MN7a is connected with grid, the source ground of MN7a, and the grid of MN7a is connected with the grid of MN7b; The drain electrode of MN8a is connected with grid, the source ground of MN8a, and the grid of MN8a is connected with the grid of MN8b; The grid of MP11a and MP11b is connected, and the grid of MP11a is connected with drain electrode, and the drain electrode of MP11a is simultaneously connected with the drain electrode of MN8b; The drain electrode of MP11b is connected with the drain electrode of MN7b, and its tie point is as the output terminal of error amplifier 4; The source ground of MN8b and MN7b; One end of electric capacity C1 drains with MN7b and is connected, other end ground connection.
As preferably, described bias-voltage generating circuit 5 comprises: PMOS MP5, MP13, NMOS tube MN6 and resistance R6; The source electrode of MP5 is connected with the source electrode of MP13, and what its tie point exported as the first input end receiver voltage self-regulation circuit 1 of voltage generation circuit 5 first suppresses signal; The grid of MP5 is connected with the grid of MP13, and its tie point is connected with the output terminal of error amplifier 4 as the second input end of bias-voltage generating circuit 5; The drain electrode of MP5 is connected with the drain electrode of MN6, and tie point exports the first biasing voltage signal as the first output terminal of voltage generation circuit 5 to self-regulating votage circuit 1; The drain electrode of MN6 is connected with grid, the source ground of MN6; The drain electrode of MP13 is by R6 ground connection, and the contact of MP13 and R6 exports the second biasing voltage signal as the second output terminal of voltage generation circuit 5 to self-regulating votage circuit 1.
As preferably, described benchmark start-up circuit 6 comprises PMOS MP8, MP9 and resistance R5; The source electrode of MP8 with MP9 is connected, and what tie point exported as the first input end receiver voltage self-regulation circuit 1 of benchmark start-up circuit 6 first suppresses signal; The grid of MP8 receives single order temperature compensated reference as the second input end of benchmark start-up circuit 6 and produces the startup offset signal that circuit 3 exports; The drain electrode of MP8 is by R5 ground connection; The grid of MP9 is connected with the contact of MP8 with R5, and MP9 drain electrode produces circuit 3 input reference starting current signal as the output terminal of benchmark start-up circuit 6 to single order temperature compensated reference.
Beneficial effect: compared to traditional benchmark voltage source, the present invention has the following advantages:
1, the present invention's design of adopting self-regulating votage circuit and single order temperature compensated reference to produce circuit to combine, can carry out twice suppression for power supply noise, the Power Supply Rejection Ratio of band-gap reference supply voltage is improved greatly;
2, this self-regulating votage circuit has a backfeed loop, the size of the automatic regulation output electric current of energy, and the electric current solved needed for late-class circuit increases suddenly the problem causing instability to whole circuit, adds the stability of circuit;
3, this self-regulating votage circuit not only can be applied to the single order temperature compensation bandgap reference generating circuit used in the present invention, and the band-gap reference that can also be applicable to other produces circuit, compatible strong;
4, the single order temperature compensation bandgap reference voltage source in the present invention adopts parasitic NPN pipe, can realize under CMOS technology; Adopt current-mode structure, be applicable to operation at low power supply voltage, there is the advantage of low-power consumption.
Accompanying drawing explanation
Fig. 1 is structural drawing of the present invention;
Fig. 2 is the integrated circuit topological diagram of the embodiment of the present invention;
Fig. 3 is the circuit topology figure not comprising backfeed loop in start-up circuit and self-regulating votage circuit;
Fig. 4 is the circuit topology figure comprising backfeed loop in start-up circuit and self-regulating votage circuit;
Fig. 5 is the circuit topology figure of error amplifier;
Fig. 6 is traditional bandgap reference voltage source and the inhibition analogous diagram of bandgap voltage reference for power supply noise with high PSRR provided by the invention.
In figure, 1, self-regulating votage circuit, 2, start-up circuit, 3, single order temperature compensated reference produces circuit, 4, error amplifier, 5, bias-voltage generating circuit, 6, benchmark start-up circuit.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further described.
Be illustrated in figure 1 structural drawing of the present invention, the described bandgap voltage reference with high PSRR comprises direct voltage source Vdd, single order temperature compensated reference produces circuit 3, error amplifier 4, bias-voltage generating circuit 5 and benchmark start-up circuit 6, also comprises self-regulating votage circuit 1 and start-up circuit 2; Direct voltage source Vdd provides supply voltage for described bandgap voltage reference; Self-regulating votage circuit 1 is using direct voltage source voltage Vdd as starting potential signal, receive the biasing voltage signal that bias-voltage generating circuit 5 exports, carrying out first time according to biasing voltage signal to the noise in starting potential suppresses generation first to suppress signal, and suppresses signal to input the power supply voltage signal input end of single order temperature compensated reference generation circuit 3, error amplifier 4, bias-voltage generating circuit 5 and benchmark start-up circuit 6 respectively by first; Described start-up circuit 2 is using direct voltage source voltage Vdd as starting potential signal, be connected with bias-voltage generating circuit 5 with self-regulating votage circuit 1 respectively simultaneously, when self-regulating votage circuit 1 works, start-up circuit 2 ends, when self-regulating votage circuit 1 quits work, start-up circuit 2 conducting, control voltage self-regulation circuit 1 is started working; Single order temperature compensated reference produces circuit 3 and is connected with error amplifier 4, amplifier bias voltage signal is provided to error amplifier 4, receive the regulated voltage signal that error amplifier 4 exports simultaneously, and regulated voltage signal is converted into the electric current of zero-temperature coefficient, and then generation reference voltage, reference voltage is as the output signal of described bandgap voltage reference; Single order temperature compensated reference produces circuit 3 and is connected with benchmark start-up circuit 6 simultaneously, receives the benchmark starting current signal that benchmark start-up circuit 6 exports, and starts offset signal to benchmark start-up circuit 6 input; Error amplifier 4 is connected with bias-voltage generating circuit 5, to bias-voltage generating circuit 5 input voltage regulation signal.
Embodiment 1: the circuit structure of described self-regulating votage circuit 1 and start-up circuit 2 is as shown in Figure 3:
Self-regulating votage circuit 1 comprises PMOS MP1a, MP2, MP3 and NMOS tube MN1a, MN1b, MN2; Wherein, the source electrode of MP1a with MP2 is connected, and its tie point is connected with direct supply Vdd; The grid of MP1a is connected with the grid of MP2, and the grid of MP1a is connected with drain electrode simultaneously, and the drain electrode of MP1a is connected with the drain electrode of MN1a; The drain electrode of MP2 is connected with the source electrode of MP3, and tie point suppresses signal output part as first of described self-regulating votage circuit 1, and this tie point is connected with the drain electrode of MN2 simultaneously; The grid of MP3 is as the second offset signal input end of self-regulating votage circuit 1, and the drain electrode of MP3 is connected with the grid of MN2 and is connected with the drain electrode of MN1b simultaneously; The source grounding of MN2, MN1a, MN1b; The grid of MN1a with MN1b is connected, and its tie point is as the first offset signal input end of self-regulating votage circuit 1; Self-regulating votage circuit 1 is connected with bias-voltage generating circuit 5 with the second offset signal input end by the first offset signal input end, receives the first biasing voltage signal and second biasing voltage signal of bias-voltage generating circuit 5 output.
Start-up circuit 2 comprises: NMOS tube MN4, MN5 and resistance R1; One end of R1 is connected with direct supply Vdd, the other end is connected with the grid of MN5, the grid of MN5 is connected with the drain electrode of MN4 simultaneously, the drain electrode of MN5 is connected with the drain junction of MP1a with MN1a in self-regulating votage circuit 1, the source ground of MN5, the grid of MN4 is connected with the first offset signal input end of self-regulating votage circuit 1, the source ground of MN4.
Described single order temperature compensated reference produces the decision design of circuit 3, error amplifier 4, bias-voltage generating circuit 5 and benchmark start-up circuit 6 as shown in Figure 2:
Single order temperature compensated reference produces circuit 3 and comprises PMOS MP4a, MP4b, MP6, MP7, resistance R2, R3a, R3b, R4 and NPN pipe Q1, Q2, Q3, the source electrode of MP4a, MP4b, MP6, MP7 is connected, and tie point is the first suppression signal that described single order temperature compensated reference produces first input end receiver voltage self-regulation circuit 1 output of circuit 3, the grid of MP4a, MP4b, MP6 is connected, its tie point is the regulated voltage signal that described single order temperature compensated reference produces the 3rd input end reception error amplifier 4 output of circuit 3, this regulated voltage signal is converted to the electric current of zero-temperature coefficient by MP4a, MP4b, MP6, and then produces reference voltage by resistance R4, the drain electrode of MP4a is connected with the in-phase input end of described error amplifier 4, its tie point is that the 3rd output terminal of described single order temperature compensated reference generation circuit 3 is connected with error amplifier 4 in-phase input end, the drain electrode of MP4a is connected with resistance R3a with R2 simultaneously, the other end ground connection of R3a, the other end of R2 is connected with the collector of NPN pipe Q1, the collector of Q1 is connected with base stage, grounded emitter, the drain electrode of MP4b is connected with the inverting input of described error amplifier 4, its tie point is that the 4th output terminal of described single order temperature compensated reference generation circuit 3 is connected with the inverting input of error amplifier 4, the drain electrode of MP4b is connected with the collector of NPN pipe Q2, the collector of Q2 is connected with base stage, grounded emitter, the drain electrode of MP4b is connected with one end of resistance R3b, its tie point is the benchmark starting current signal that described single order temperature compensated reference produces the second input end reception benchmark start-up circuit 6 output of circuit 3, the other end ground connection of R3b, the drain electrode of MP4b is connected with the base stage of NPN pipe Q3, the drain electrode of MP6 is by resistance R4 ground connection, and the tie point of MP6 and R4 is the 5th output terminal that described single order temperature compensated reference produces circuit 3, as the reference voltage output end of described bandgap voltage reference, the base stage of MP7 is connected with drain electrode, its tie point is that described single order temperature compensated reference produces the first output terminal of circuit 3 to start-up circuit 6 output startup offset signal, the drain electrode of MP7 is connected with the collector of NPN pipe Q3, tie point is the second output terminal of described single order temperature compensated reference generation circuit 3 is that error amplifier 4 is powered, the grounded emitter of Q3.
Error amplifier 4 comprises PMOS MP10a, MP10b, MP11a, MP11b, NPN pipe Q4, Q5, NMOS tube MN7a, MN7b, MN8a, MN8b and electric capacity C1; The source electrode of MP10a, MP10b, MP11a, MP11b is connected, and what its tie point exported as the first input end receiver voltage self-regulation circuit 1 of error amplifier 4 first suppresses signal as supply voltage; The grid of MP10a, MP10b is connected, and its tie point receives as the second input end of error amplifier 4 supply voltage that single order temperature compensated reference produces circuit 3 output; The drain electrode of MP10a is connected with the collector of NPN pipe Q4, is connected with the drain electrode of NMOS tube MN8b simultaneously; The drain electrode of MP10b is connected with the collector of NPN pipe Q5, is connected with the drain electrode of NMOS tube MN7a simultaneously; NPN pipe Q4 with Q5 is that common emitter is connected, and tie point ground connection, and the base stage of Q4 is as the inverting input of error amplifier 4, and the base stage of Q5 is as the in-phase input end of error amplifier 4; The drain electrode of MN7a is connected with grid, the source ground of MN7a, and the grid of MN7a is connected with the grid of MN7b; The drain electrode of MN8a is connected with grid, the source ground of MN8a, and the grid of MN8a is connected with the grid of MN8b; The grid of MP11a and MP11b is connected, and the grid of MP11a is connected with drain electrode, and the drain electrode of MP11a is simultaneously connected with the drain electrode of MN8b; The drain electrode of MP11b is connected with the drain electrode of MN7b, and its tie point is as the output terminal of error amplifier 4; The source ground of MN8b and MN7b; One end of electric capacity C1 drains with MN7b and is connected, other end ground connection.
Bias-voltage generating circuit 5 comprises: PMOS MP5, MP13, NMOS tube MN6 and resistance R6; The source electrode of MP5 is connected with the source electrode of MP13, and what its tie point exported as the first input end receiver voltage self-regulation circuit 1 of voltage generation circuit 5 first suppresses signal; The grid of MP5 is connected with the grid of MP13, and its tie point is connected with the output terminal of error amplifier 4 as the second input end of bias-voltage generating circuit 5; The drain electrode of MP5 is connected with the drain electrode of MN6, and tie point exports the first biasing voltage signal as the first output terminal of voltage generation circuit 5 to self-regulating votage circuit 1; The drain electrode of MN6 is connected with grid, the source ground of MN6; The drain electrode of MP13 is by R6 ground connection, and the contact of MP13 and R6 exports the second biasing voltage signal as the second output terminal of voltage generation circuit 5 to self-regulating votage circuit 1.
Benchmark start-up circuit 6 comprises PMOS MP8, MP9 and resistance R5; The source electrode of MP8 with MP9 is connected, and what tie point exported as the first input end receiver voltage self-regulation circuit 1 of benchmark start-up circuit 6 first suppresses signal; The grid of MP8 receives single order temperature compensated reference as the second input end of benchmark start-up circuit 6 and produces the startup offset signal that circuit 3 exports; The drain electrode of MP8 is by R5 ground connection; The grid of MP9 is connected with the contact of MP8 with R5, and MP9 drain electrode produces circuit 3 input reference starting current signal as the output terminal of benchmark start-up circuit 6 to single order temperature compensated reference.
Self-regulating votage circuit 1 is set forth to the effect improving Power Supply Rejection Ratio below by concrete principle.
When above-mentioned bandgap voltage reference does not comprise self-regulating votage circuit 1, namely single order temperature compensated reference generation circuit is directly powered by direct supply Vdd, suppose that power supply noise is an ac small signal, be expressed as VaVdd, if be Vavf through circuit function at the output noise signal of the generation of the output terminal of band-gap reference, then can obtain Power Supply Rejection Ratio PSRR, expression formula is:
The suppression of the larger expression of value to power supply noise of Power Supply Rejection Ratio PSRR is stronger.
Circuit connecting relation according to Fig. 2, can also obtain following formula:
In formula, Vf is the output end signal of error amplifier 4, represent the change in voltage that PMOS MP4a and MP4b produces due to power supply noise VaVdd, Va is the in-phase input end change in voltage size of error amplifier, Vb is the inverting input change in voltage size of error amplifier, and Add represents the power supply rejection ability (small-signal gain of power supply noise from power supply to amplifier out) of error amplifier; Gm6 represents the mutual conductance of PMOS MP6, and gm4 represents the mutual conductance of PMOS MP4a and MP4b entirety, and wherein the value of gm6 and gm4 is equal; RQ1 and RQ2 is respectively the equivalent resistance of NPN transistor Q1 and Q2.Order,
Rx＝R
3b||R
Q2
Ry＝R
3a||(R
2+R
Q1)
Bring formula 2 into formula 1, can not be comprised the Power Supply Rejection Ratio PSRR of the bandgap voltage reference of self-regulating votage circuit 1, expression formula is:
When above-mentioned bandgap voltage reference comprises self-regulating votage circuit 1, as shown in Figure 3, self-regulating votage circuit 1 couple of power supply noise Vavdn carries out first time to be suppressed, and can obtain following formula according to Fig. 3:
In formula, Vregn is the noise signal that self-regulating votage circuit 1 exports, Vn is the effect due to power supply noise, the voltage change of PMOS MP2 grid, Ax represents that the gain that power supply noise Vavdn to MP2 grid voltage changes, Ax are a constant close to 1, and gm2 is the mutual conductance of PMOS MP2, Vreg is the output signal of DC voltage Vdd at self-regulating votage circuit 1 of input, and Rregn is the equivalent output resistance of entering viewed from self-regulating votage circuit 1 output terminal.Bring formula 4 into formula 1, the expression formula that can obtain the Power Supply Rejection Ratio of self-regulating votage circuit 1 is:
The value of Rregn is about
wherein gnm2 is the mutual conductance of NMOS tube MN2, and bringing the value of Rregn into formula 5 can obtain
Formula 6 being brought into the bandgap voltage reference Power Supply Rejection Ratio PSRR_H expression formula that formula 1 can comprise self-regulating votage circuit 1 is:
In formula,
Rx＝R
3b||R
Q2
Ry＝R
3a||(R
2+R
Q1)
Formula 3 is more known with formula 7, Power Supply Rejection Ratio PSRR_H with the bandgap voltage reference of self-regulating votage circuit 1 will produce the Power Supply Rejection Ratio of circuit above much larger than the single order temperature compensated reference not having self-regulating votage circuit 1 to act on of deriving, the bandgap voltage reference namely comprising self-regulating votage circuit 1 is stronger for the rejection ability of power supply noise.
Embodiment 2: according to the bandgap voltage reference of embodiment 1, self-regulating votage circuit 1 also comprises a feedback circuit, and backfeed loop as shown in Figure 4, comprising: PMOS MP1b, MP12 and NMOS tube MN3a and MN3b; The source electrode of MP1b with MP12 is all connected with direct supply Vdd, and the grid of MP1b is connected with the grid of MP1a, and the drain electrode of MP1b is connected with the drain electrode of MN3a and is connected with the grid of MN3a simultaneously; The grid of MN3a is connected with the grid of MN3b, and the source electrode of MN3a and MN3b is connected and tie point is connected with the drain electrode of MP2 with MN2; The drain electrode of MN3b is connected with the grid of MP2 and is connected with draining with the grid of MP12 simultaneously; Wherein MP12 and MP3b forms a feedback amplifier, MP1b and MN3a provides bias current for MN3b; The change of self-regulating votage circuit 1 output current controls within the specific limits by backfeed loop, avoids late-class circuit because the electric current of input changes suddenly cause cisco unity malfunction.
Feedback circuit is set forth to the effect improving circuit stability below by concrete principle.
Suppose that particularly single order temperature compensated reference generation circuit is due to king-sized noise due to late-class circuit, the ER effect that late-class circuit exports at the output terminal of self-regulating votage circuit 1 is large.When circuit does not comprise above-mentioned backfeed loop, as shown in Figure 3, PMOS MP2 drain electrode exports fixing electric current to circuit, and self-regulating votage circuit 1 output end voltage Vreg diminishes.Vreg diminishes and NMOS tube MN2 place branch current can be caused to diminish on the one hand, makes pipe enter linear zone.On the other hand, the circuit of rear class particularly single order temperature compensated reference produce circuit can diminish and cisco unity malfunction due to Vreg output end voltage.
But, when circuit comprises backfeed loop, circuit as shown in Figure 4, when Vreg output end voltage diminishes, PMOS MP2 grid voltage can corresponding reduction, thus the drain electrode output current of MP2 is increased, greatly reduce and make the possibility of circuit malfunction because rear class noise self-regulating votage circuit 1 output end voltage Vreg diminishes, add the stability of circuit.It is worth mentioning that in addition, feedback control loop can reduce the output impedance of Vreg output terminal further, improves Power Supply Rejection Ratio.
Fig. 6 illustrates the comparison diagram of two width Power Supply Rejection Ratio, and the former is the oscillogram of bandgap voltage reference to noise suppression effect of not making alive self-regulation circuit, and the latter the present invention is to the oscillogram of noise suppression effect.Relatively more visible, the bandgap voltage reference Power Supply Rejection Ratio with self-regulating votage circuit is higher.Common bandgap voltage reference Power Supply Rejection Ratio is about 72.29dB at low frequency, is about 62.34dB at 1kHz place.The bandgap voltage reference Power Supply Rejection Ratio that the present invention proposes is about 139.5dB at low frequency, compares the former and improves 67.21dB; Be about 120.4dB at 1kHz place, compare the former and improve 58.06dB.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. one kind has the bandgap voltage reference of high PSRR, comprise direct voltage source Vdd, single order temperature compensated reference produces circuit (3), error amplifier (4), bias-voltage generating circuit (5) and benchmark start-up circuit (6), it is characterized in that, also comprise self-regulating votage circuit (1) and start-up circuit (2); Direct voltage source Vdd provides supply voltage for described bandgap voltage reference; Self-regulating votage circuit (1) is using direct voltage source voltage Vdd as starting potential signal, receive the biasing voltage signal that bias-voltage generating circuit (5) exports, carrying out first time according to biasing voltage signal to the noise in starting potential suppresses generation first to suppress signal, and suppresses signal to input the power supply voltage signal input end of single order temperature compensated reference generation circuit (3), error amplifier (4), bias-voltage generating circuit (5) and benchmark start-up circuit (6) respectively by first; Described start-up circuit (2) is using direct voltage source voltage Vdd as starting potential signal, be connected with bias-voltage generating circuit (5) with self-regulating votage circuit (1) respectively simultaneously, when self-regulating votage circuit (1) works, start-up circuit (2) ends, when self-regulating votage circuit (1) quits work, start-up circuit (2) conducting, control voltage self-regulation circuit (1) is started working; Single order temperature compensated reference produces circuit (3) and is connected with error amplifier (4), amplifier bias voltage signal is provided to error amplifier (4), receive the regulated voltage signal that error amplifier (4) exports simultaneously, and regulation voltage signal is converted into the electric current of zero-temperature coefficient, and then generation reference voltage, reference voltage is as the output signal of described bandgap voltage reference; Single order temperature compensated reference produces circuit (3) and is connected with benchmark start-up circuit (6) simultaneously, receive the benchmark starting current signal that benchmark start-up circuit (6) exports, and start offset signal to benchmark start-up circuit (6) input; Error amplifier (4) is connected with bias-voltage generating circuit (5), to bias-voltage generating circuit (5) input voltage regulation signal.
2. a kind of bandgap voltage reference with high PSRR according to claim 1, is characterized in that, described self-regulating votage circuit (1) comprising: PMOS MP1a, MP2, MP3 and NMOS tube MN1a, MN1b, MN2; Wherein, the source electrode of MP1a with MP2 is connected, and its tie point is connected with direct supply Vdd; The grid of MP1a is connected with the grid of MP2, and the grid of MP1a is connected with drain electrode simultaneously, and the drain electrode of MP1a is connected with the drain electrode of MN1a; The drain electrode of MP2 is connected with the source electrode of MP3, and tie point suppresses signal output part as first of described self-regulating votage circuit (1), and this tie point is connected with the drain electrode of MN2 simultaneously; The grid of MP3 is as the second offset signal input end of self-regulating votage circuit (1), and the drain electrode of MP3 is connected with the grid of MN2 and is connected with the drain electrode of MN1b simultaneously; The source grounding of MN2, MN1a, MN1b; The grid of MN1a with MN1b is connected, and its tie point is as the first offset signal input end of self-regulating votage circuit (1); Self-regulating votage circuit (1) is connected with bias-voltage generating circuit (5) with the second offset signal input end by the first offset signal input end, the first biasing voltage signal that reception bias-voltage generating circuit (5) exports and the second biasing voltage signal.
3. a kind of bandgap voltage reference with high PSRR according to claim 2, it is characterized in that, described self-regulating votage circuit (1) also comprises a backfeed loop, and described backfeed loop comprises: PMOS MP1b, MP12 and NMOS tube MN3a and MN3b; The source electrode of MP1b with MP12 is all connected with direct supply Vdd, and the grid of MP1b is connected with the grid of MP1a, and the drain electrode of MP1b is connected with the drain electrode of MN3a and is connected with the grid of MN3a simultaneously; The grid of MN3a is connected with the grid of MN3b, and the source electrode of MN3a and MN3b is connected and tie point is connected with the drain electrode of MP2 with MN2; The drain electrode of MN3b is connected with the grid of MP2 and is connected with draining with the grid of MP12 simultaneously; Wherein MP12 and MP3b forms a feedback amplifier, MP1b and MN3a provides bias current for MN3b; The change of self-regulating votage circuit (1) output current controls within the specific limits by backfeed loop, avoids late-class circuit because the electric current of input changes suddenly cause cisco unity malfunction.
4. a kind of bandgap voltage reference with high PSRR according to claim 2, is characterized in that, described start-up circuit (2) comprises NMOS tube MN4, MN5 and resistance R1; One end of R1 is connected with direct supply Vdd, the other end is connected with the grid of MN5, the grid of MN5 is connected with the drain electrode of MN4 simultaneously, the drain electrode of MN5 is connected with the drain junction of MP1a with MN1a in self-regulating votage circuit (1), the source ground of MN5, the grid of MN4 is connected with the first offset signal input end of self-regulating votage circuit (1), the source ground of MN4.
5. a kind of bandgap voltage reference with high PSRR according to claim 2, it is characterized in that, described single order temperature compensated reference produces circuit (3) and comprises PMOS MP4a, MP4b, MP6, MP7, resistance R2, R3a, R3b, R4 and NPN pipe Q1, Q2, Q3, the source electrode of MP4a, MP4b, MP6, MP7 is connected, and tie point is the first suppression signal that first input end receiver voltage self-regulation circuit (1) of described single order temperature compensated reference generation circuit (3) exports, the grid of MP4a, MP4b, MP6 is connected, its tie point is the regulated voltage signal that the 3rd input end reception error amplifier (4) of described single order temperature compensated reference generation circuit (3) exports, this regulated voltage signal is converted to the electric current of zero-temperature coefficient by MP4a, MP4b, MP6, and then produces reference voltage by resistance R4, the drain electrode of MP4a is connected with the in-phase input end of described error amplifier (4), its tie point is that the 3rd output terminal of described single order temperature compensated reference generation circuit (3) is connected with error amplifier (4) in-phase input end, the drain electrode of MP4a is connected with resistance R3a with R2 simultaneously, the other end ground connection of R3a, the other end of R2 is connected with the collector of NPN pipe Q1, the collector of Q1 is connected with base stage, grounded emitter, the drain electrode of MP4b is connected with the inverting input of described error amplifier (4), its tie point is that the 4th output terminal of described single order temperature compensated reference generation circuit (3) is connected with the inverting input of error amplifier (4), the drain electrode of MP4b is connected with the collector of NPN pipe Q2, the collector of Q2 is connected with base stage, grounded emitter, the drain electrode of MP4b is connected with one end of resistance R3b, its tie point is the benchmark starting current signal that the second input end reception benchmark start-up circuit (6) of described single order temperature compensated reference generation circuit (3) exports, the other end ground connection of R3b, the drain electrode of MP4b is connected with the base stage of NPN pipe Q3, the drain electrode of MP6 is by resistance R4 ground connection, and the tie point of MP6 and R4 is the 5th output terminal that described single order temperature compensated reference produces circuit (3), as the reference voltage output end of described bandgap voltage reference, the base stage of MP7 is connected with drain electrode, its tie point is that described single order temperature compensated reference produces the first output terminal of circuit (3) to start-up circuit (6) output startup offset signal, the drain electrode of MP7 is connected with the collector of NPN pipe Q3, tie point is the second output terminal of described single order temperature compensated reference generation circuit (3) is error amplifier (4) power supply, the grounded emitter of Q3.
6. a kind of bandgap voltage reference with high PSRR according to claim 1, it is characterized in that, error amplifier (4) comprises PMOS MP10a, MP10b, MP11a, MP11b, NPN pipe Q4, Q5, NMOS tube MN7a, MN7b, MN8a, MN8b and electric capacity C1; The source electrode of MP10a, MP10b, MP11a, MP11b is connected, and what its tie point exported as first input end receiver voltage self-regulation circuit (1) of error amplifier (4) first suppresses signal as supply voltage; The grid of MP10a, MP10b is connected, and its tie point receives single order temperature compensated reference as the second input end of error amplifier (4) and produces the supply voltage that circuit (3) exports; The drain electrode of MP10a is connected with the collector of NPN pipe Q4, is connected with the drain electrode of NMOS tube MN8b simultaneously; The drain electrode of MP10b is connected with the collector of NPN pipe Q5, is connected with the drain electrode of NMOS tube MN7a simultaneously; NPN pipe Q4 with Q5 is that common emitter is connected, and tie point ground connection, and the base stage of Q4 is as the inverting input of error amplifier (4), and the base stage of Q5 is as the in-phase input end of error amplifier (4); The drain electrode of MN7a is connected with grid, the source ground of MN7a, and the grid of MN7a is connected with the grid of MN7b; The drain electrode of MN8a is connected with grid, the source ground of MN8a, and the grid of MN8a is connected with the grid of MN8b; The grid of MP11a and MP11b is connected, and the grid of MP11a is connected with drain electrode, and the drain electrode of MP11a is simultaneously connected with the drain electrode of MN8b; The drain electrode of MP11b is connected with the drain electrode of MN7b, and its tie point is as the output terminal of error amplifier (4); The source ground of MN8b and MN7b; One end of electric capacity C1 drains with MN7b and is connected, other end ground connection.
7. a kind of bandgap voltage reference with high PSRR according to claim 1, is characterized in that, described bias-voltage generating circuit (5) comprising: PMOS MP5, MP13, NMOS tube MN6 and resistance R6; The source electrode of MP5 is connected with the source electrode of MP13, and what its tie point exported as first input end receiver voltage self-regulation circuit (1) of voltage generation circuit (5) first suppresses signal; The grid of MP5 is connected with the grid of MP13, and its tie point is connected with the output terminal of error amplifier (4) as the second input end of bias-voltage generating circuit (5); The drain electrode of MP5 is connected with the drain electrode of MN6, and tie point exports the first biasing voltage signal as the first output terminal of voltage generation circuit (5) to self-regulating votage circuit (1); The drain electrode of MN6 is connected with grid, the source ground of MN6; The drain electrode of MP13 is by R6 ground connection, and the contact of MP13 and R6 exports the second biasing voltage signal as the second output terminal of voltage generation circuit (5) to self-regulating votage circuit (1).
8. a kind of bandgap voltage reference with high PSRR according to claim 1, is characterized in that, described benchmark start-up circuit (6) comprises PMOS MP8, MP9 and resistance R5; The source electrode of MP8 with MP9 is connected, and what tie point exported as first input end receiver voltage self-regulation circuit (1) of benchmark start-up circuit (6) first suppresses signal; The grid of MP8 receives single order temperature compensated reference as the second input end of benchmark start-up circuit (6) and produces the startup offset signal that circuit (3) exports; The drain electrode of MP8 is by R5 ground connection; The grid of MP9 is connected with the contact of MP8 with R5, and MP9 drain electrode produces circuit (3) input reference starting current signal as the output terminal of benchmark start-up circuit (6) to single order temperature compensated reference.
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| WO2017049840A1 (en) | 2017-03-30 |
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