CN111813175A - High-voltage large-drive high-power supply rejection ratio LDO (low dropout regulator) - Google Patents
High-voltage large-drive high-power supply rejection ratio LDO (low dropout regulator) Download PDFInfo
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- CN111813175A CN111813175A CN202010801443.6A CN202010801443A CN111813175A CN 111813175 A CN111813175 A CN 111813175A CN 202010801443 A CN202010801443 A CN 202010801443A CN 111813175 A CN111813175 A CN 111813175A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
A high-voltage large-drive high-power supply rejection ratio LDO belongs to the technical field of LDOs. The invention aims at the problems of large noise and poor circuit stability of the LDO circuit with the off-chip capacitor in the prior art by improving the power supply rejection ratio. The cascode resistive source degeneration circuit adopts NMOS differential pair transistors for input to obtain a low-voltage difference fixed primary output voltage; and the dynamic compensation circuit adopts a dynamic zero compensation and dynamic bias mode to the primary output voltage to obtain the final output voltage. The invention can greatly reduce the noise of the output voltage and ensure the stability of the working point.
Description
Technical Field
The invention relates to a high-voltage large-drive high-power supply rejection ratio LDO (low dropout regulator), belonging to the technical field of LDOs.
Background
LDOs (low dropout linear regulators) are critical components of integrated circuits, and are the core components of advanced systems such as data converters, precision amplifiers, and VCOs (voltage controlled oscillators), all of which require high power supply rejection ratio, low noise, and large current supplies. The noisy power supply of the DCDC output cannot meet the use requirements of the advanced system due to the large ripple. And the high-performance LDO can avoid the disadvantage of complaint, so that the probability of the performance of the advanced system influenced by noise is greatly reduced. Therefore, high power supply rejection ratio and low noise design of the LDO are crucial.
The LDO (low dropout regulator) with the off-chip capacitor is mainly dominated by 1/f noise of a low frequency band, and the 1/f noise is far higher than the thermal noise of a device in the low frequency band. The resistor is a passive element and mainly contributes to thermal noise, and a common MOS tube current source is transformed into a resistive source degradation (resistive source degradation) current source, so that the low-frequency noise of current output can be obviously reduced. Therefore, in a low noise LDO, a resistive source degeneration structure is widely used to reduce noise.
At the worst loop unit gain bandwidth of the LDO power supply rejection ratio with off-chip capacitance, a PMOSFET power tube can realize low voltage difference and good reliability, but the PSR (primary side feedback) of the LDO power supply rejection ratio is poor compared with an NMOSFET power tube, and the high power supply rejection ratio needs to be realized through the improvement of an internal circuit structure.
The improvement of the prior art on the LDO circuit often causes the operating point of the LDO to change to a great extent on the premise of process, voltage and temperature (PVT) changes, thereby affecting the performance of the LDO circuit and its normal operating state.
Disclosure of Invention
The invention provides a high-voltage large-drive LDO with a high power supply rejection ratio, aiming at the problems of high noise and poor circuit stability of the improvement of the LDO with an off-chip capacitor in the prior art.
The invention relates to a high-voltage large-drive high-power supply rejection ratio LDO (low dropout regulator), which comprises a cascode resistive source degeneration circuit and a dynamic compensation circuit,
the cascode resistive source degeneration circuit adopts NMOS differential pair transistors for input to obtain low-voltage difference fixed primary output voltage;
and the dynamic compensation circuit adopts a dynamic zero compensation and dynamic bias mode to the primary output voltage to obtain the final output voltage.
According to the high-voltage large-drive high-power supply rejection ratio LDO, the cascode resistive source degeneration circuit comprises a MOS tube Mn0, a MOS tube Mn1, a MOS tube Mn2, a MOS tube Mn3, a MOS tube Mp0, a MOS tube Mp1, a resistor R0, a resistor R2, a resistor R3 and a current source,
the source electrodes of the MOS transistor Mn0 and the MOS transistor Mn1 are connected with one end of a current source, and the other end of the current source is grounded;
the grid electrode of the MOS transistor Mn0 is connected with a primary output voltage connecting end VREF, and a resistor R0 is connected between the drain electrode and a low-voltage power supply; a resistor R1 is connected between the drain electrode of the MOS transistor Mn1 and a low-voltage power supply;
the drain electrode of the MOS tube Mn0 is connected with the source electrode of the MOS tube Mp0, the drain electrode of the MOS tube Mp0 is connected with the drain electrode of the MOS tube Mn2, and a resistor R2 is connected between the source electrode of the MOS tube Mn2 and the grounding point; the drain electrode of the MOS transistor Mn2 is connected with the grid electrode;
the gate of the MOS tube Mp0 is connected with the gate of the MOS tube Mp1, the source of the MOS tube Mp1 is connected with the drain of the MOS tube Mn1, the drain of the MOS tube Mp1 is connected with the drain of the MOS tube Mn3, the gate of the MOS tube Mn3 is connected with the gate of the MOS tube Mn2, and a resistor R3 is connected between the source of the MOS tube Mn3 and the grounding point;
and the drain electrode of the MOS transistor Mn3 is used as a primary output voltage connecting end VREF.
According to the high-voltage large-drive high-power-supply rejection ratio LDO, the cascode resistive source degeneration circuit (100) further comprises a MOS transistor Mn5 and a capacitor C0,
the drain electrode of the MOS transistor Mn3 is connected with the gate electrode of the MOS transistor Mn5, the source electrode of the MOS transistor Mn5 is grounded, and the capacitor C0 is connected between the drain electrode and the gate electrode.
According to the LDO with high voltage, large drive and high power supply rejection ratio, the dynamic compensation circuit (200) comprises a MOS tube Mn4, a MOS tube Mn6, a MOS tube Mp2, a MOS tube Mp3, a MOS tube PMOSFET, a resistor R4, a resistor R5 and a capacitor C1,
the grid electrode of the MOS tube Mn5 is connected with the grid electrode of the MOS tube Mn4, the source electrode of the MOS tube Mn4 is grounded, the drain electrode of the MOS tube Mn6 is connected with the source electrode of the MOS tube Mn6, the grid electrode of the MOS tube Mn6 is connected with fixed bias voltage, the drain electrode of the MOS tube Mn6 is connected with one end of a resistor R4, and the other end of the resistor R4 is connected with a high-voltage power supply; the drain electrode of the MOS tube Mn6 is connected with the gate electrode of the MOS tube Mp2, the gate electrode of the MOS tube Mp2 is connected with the drain electrode, the source electrode of the MOS tube Mp2 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a high-voltage power supply, and a capacitor C1 is connected between the other end of the resistor R5 and the drain electrode of the MOS tube Mn 4; the grid electrode of the MOS tube Mp2 is connected with the grid electrode of the MOS tube Mp3, the grid electrode of the MOS tube Mp3 is connected with the drain electrode, and the source electrode of the MOS tube Mp3 is connected with a high-voltage power supply; the grid electrode of the MOS tube Mp3 is connected with the grid electrode of the MOS tube PMOSFET, the source electrode of the MOS tube PMOSFET is connected with a high-voltage power supply, and the drain electrode of the MOS tube PMOSFET serves as an intermediate voltage output end.
According to the LDO with high voltage, large drive and high power supply rejection ratio, the dynamic compensation circuit (200) further comprises an off-chip resistor REXT0. Off-chip resistance REXT1 and off-chip capacitor CL，
An off-chip resistor R is sequentially connected between the drain electrode of the MOS tube PMOSFET and the grounding point in seriesEXT1 and an off-chip resistance REXT0, off-chip capacitance CLAnd an off-chip resistor REXT1 and an off-chip resistance REXT0 are connected in parallel;
off-chip resistance REXT1 and an off-chip resistance REXTThe outgoing line between 0 serves as a connection terminal VFB, and the connection terminal VFB is connected with the grid electrode of the MOS transistor Mn 1.
The invention has the beneficial effects that: the input voltage range of the invention can be 2.6V-40V; the output driving current can be as high as 200 mA; the off-chip capacitance is as low as 1 uF; the power supply rejection ratio reaches 50dB at a frequency point of 1 MHz; the lowest voltage difference of the circuit is 250 mV; meanwhile, the fixed output voltage has low noise and is only 10.5uVrms at normal temperature. The circuit adopts NMOS differential pair tube input and a resistive source degeneration cascode structure. The loop compensation of the circuit adopts dynamic zero compensation and a dynamic bias circuit, so that the no-load static power consumption is low, and the heavy-load loop is stable. Meanwhile, a feedforward zero point can be added at a high-frequency point of 1MHz to improve the PSR.
The circuit can greatly reduce the noise of the fixed output voltage of the LDO, and simultaneously, the stable working point is ensured by adopting a matching and dynamic compensation mode under the conditions of process, voltage, temperature and full load.
Drawings
FIG. 1 is a schematic circuit diagram of the LDO of the present invention;
fig. 2 is a basic low noise schematic of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
First embodiment, referring to fig. 1, the present invention provides a high-voltage large-driving high-power-supply-rejection-ratio LDO, which includes a cascode resistive source degeneration circuit 100 and a dynamic compensation circuit 200,
the cascode resistive source degeneration circuit 100 adopts NMOS differential pair transistors for input to obtain a low-voltage difference fixed primary output voltage;
the dynamic compensation circuit 200 obtains the final output voltage by using the dynamic zero compensation and the dynamic bias for the first-stage output voltage.
Further, as shown in fig. 1, the cascode resistive source degeneration circuit (100) includes a MOS transistor Mn0, a MOS transistor Mn1, a MOS transistor Mn2, a MOS transistor Mn3, a MOS transistor Mp0, a MOS transistor Mp1, a resistor R0, a resistor R2, a resistor R3, and a current source,
the source electrodes of the MOS transistor Mn0 and the MOS transistor Mn1 are connected with one end of a current source, and the other end of the current source is grounded;
the grid electrode of the MOS transistor Mn0 is connected with a primary output voltage connecting end VREF, and a resistor R0 is connected between the drain electrode and a low-voltage power supply; a resistor R1 is connected between the drain electrode of the MOS transistor Mn1 and a low-voltage power supply;
the drain electrode of the MOS tube Mn0 is connected with the source electrode of the MOS tube Mp0, the drain electrode of the MOS tube Mp0 is connected with the drain electrode of the MOS tube Mn2, and a resistor R2 is connected between the source electrode of the MOS tube Mn2 and the grounding point; the drain electrode of the MOS transistor Mn2 is connected with the grid electrode;
the gate of the MOS tube Mp0 is connected with the gate of the MOS tube Mp1, the source of the MOS tube Mp1 is connected with the drain of the MOS tube Mn1, the drain of the MOS tube Mp1 is connected with the drain of the MOS tube Mn3, the gate of the MOS tube Mn3 is connected with the gate of the MOS tube Mn2, and a resistor R3 is connected between the source of the MOS tube Mn3 and the grounding point;
and the drain electrode of the MOS transistor Mn3 is used as a primary output voltage connecting end VREF.
Still further, as shown in fig. 1, the cascode resistive source degeneration circuit 100 further includes a MOS transistor Mn5 and a capacitor C0,
the drain electrode of the MOS transistor Mn3 is connected with the gate electrode of the MOS transistor Mn5, the source electrode of the MOS transistor Mn5 is grounded, and the capacitor C0 is connected between the drain electrode and the gate electrode.
Still further, as shown in fig. 1, the dynamic compensation circuit 200 includes a MOS transistor Mn4, a MOS transistor Mn6, a MOS transistor Mp2, a MOS transistor Mp3, a MOS transistor PMOSFET, a resistor R4, a resistor R5, and a capacitor C1,
the grid electrode of the MOS tube Mn5 is connected with the grid electrode of the MOS tube Mn4, the source electrode of the MOS tube Mn4 is grounded, the drain electrode of the MOS tube Mn6 is connected with the source electrode of the MOS tube Mn6, the grid electrode of the MOS tube Mn6 is connected with fixed bias voltage, the drain electrode of the MOS tube Mn6 is connected with one end of a resistor R4, and the other end of the resistor R4 is connected with a high-voltage power supply; the drain electrode of the MOS tube Mn6 is connected with the gate electrode of the MOS tube Mp2, the gate electrode of the MOS tube Mp2 is connected with the drain electrode, the source electrode of the MOS tube Mp2 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a high-voltage power supply, and a capacitor C1 is connected between the other end of the resistor R5 and the drain electrode of the MOS tube Mn 4; the grid electrode of the MOS tube Mp2 is connected with the grid electrode of the MOS tube Mp3, the grid electrode of the MOS tube Mp3 is connected with the drain electrode, and the source electrode of the MOS tube Mp3 is connected with a high-voltage power supply; the grid electrode of the MOS tube Mp3 is connected with the grid electrode of the MOS tube PMOSFET, the source electrode of the MOS tube PMOSFET is connected with a high-voltage power supply, and the drain electrode of the MOS tube PMOSFET serves as an intermediate voltage output end.
The circuit of the embodiment adopts a diode following and dynamic compensation mode to realize the broadband high PSR characteristic. The MOS transistor Mn5, the MOS transistor Mn4 and the capacitor C0 realize matching and dynamic compensation in the circuit.
Still further, as shown in fig. 1, the dynamic compensation circuit 200 further includes an off-chip resistor REXT0. Off-chip resistance REXT1 and off-chip capacitor CL，
An off-chip resistor R is sequentially connected between the drain electrode of the MOS tube PMOSFET and the grounding point in seriesEXT1 and an off-chip resistance REXT0, off-chip capacitance CLAnd an off-chip resistor REXT1 and an off-chip resistance REXT0 are connected in parallel;
off-chip resistance REXT1 and an off-chip resistance REXTThe outgoing line between 0 serves as a connection terminal VFB, and the connection terminal VFB is connected with the grid electrode of the MOS transistor Mn 1.
The off-chip resistor REXT1 is a variable resistor.
The LDO circuit adopts a dynamic output resistance mode to increase the secondary pole along with the increase of the load so as to realize large drive and ensure the stability of a loop. The corresponding components comprise an MOS tube Mp2, an MOS tube Mp3, a resistor R4 and a resistor R5.
The following describes the implementation process of the low noise reference voltage circuit of the present invention with reference to fig. 2:
in the LDO of the present invention, a part of circuits for realizing noise shaping includes: MOS pipe Mn0, MOS pipe Mn1, MOS pipe Mp0, MOS pipe Mp1, capacitor C0 and bias current source. The circuit adopts an MOS tube asymmetric mirror image bias circuit, the MOS tube Mn0 is a proportional tube, the MOS tube Mn1 is an inverse ratio tube, the MOS tube Mp0 is a proportional tube, and the MOS tube Mp1 is an inverse ratio tube; it can be determined that VREF _ NOISE to VREF in fig. 2 is equivalent to high impedance, and thus forms a NOISE shaping circuit with the capacitor C0.
The LDO has high PSR in a wide frequency band by using a resistive source degeneration cascode structure, dynamic compensation and high-frequency compensation, the PSR is improved by adding a feedforward zero point at a high frequency position, and meanwhile, reference noise is filtered in the circuit by adopting a large RC (resistance-capacitance) mode, so that the noise of the fixed output voltage of the LDO is greatly reduced; meanwhile, the circuit has the characteristics of low power consumption and low noise, and the working point is ensured to be stable under the conditions of no load and full load and under the conditions of process, voltage and temperature fluctuation.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (5)
1. A high-voltage large-drive high-power supply rejection ratio LDO is characterized by comprising a cascode resistive source degeneration circuit (100) and a dynamic compensation circuit (200),
the cascode resistive source degeneration circuit (100) adopts NMOS differential pair transistor input to obtain low-voltage difference fixed primary output voltage;
and the dynamic compensation circuit (200) adopts a dynamic zero compensation and dynamic bias mode to the primary output voltage to obtain the final output voltage.
2. The LDO with high voltage, large drive and high power supply rejection ratio as claimed in claim 1, wherein the cascode resistive source degeneration circuit (100) comprises MOS transistor Mn0, MOS transistor Mn1, MOS transistor Mn2, MOS transistor Mn3, MOS transistor Mp0, MOS transistor Mp1, resistor R0, resistor R2, resistor R3 and a current source,
the source electrodes of the MOS transistor Mn0 and the MOS transistor Mn1 are connected with one end of a current source, and the other end of the current source is grounded;
the grid electrode of the MOS transistor Mn0 is connected with a primary output voltage connecting end VREF, and a resistor R0 is connected between the drain electrode and a low-voltage power supply; a resistor R1 is connected between the drain electrode of the MOS transistor Mn1 and a low-voltage power supply;
the drain electrode of the MOS tube Mn0 is connected with the source electrode of the MOS tube Mp0, the drain electrode of the MOS tube Mp0 is connected with the drain electrode of the MOS tube Mn2, and a resistor R2 is connected between the source electrode of the MOS tube Mn2 and the grounding point; the drain electrode of the MOS transistor Mn2 is connected with the grid electrode;
the gate of the MOS tube Mp0 is connected with the gate of the MOS tube Mp1, the source of the MOS tube Mp1 is connected with the drain of the MOS tube Mn1, the drain of the MOS tube Mp1 is connected with the drain of the MOS tube Mn3, the gate of the MOS tube Mn3 is connected with the gate of the MOS tube Mn2, and a resistor R3 is connected between the source of the MOS tube Mn3 and the grounding point;
and the drain electrode of the MOS transistor Mn3 is used as a primary output voltage connecting end VREF.
3. The LDO of claim 2, wherein the cascode resistive source degeneration circuit (100) further comprises a MOS transistor Mn5 and a capacitor C0,
the drain electrode of the MOS transistor Mn3 is connected with the gate electrode of the MOS transistor Mn5, the source electrode of the MOS transistor Mn5 is grounded, and the capacitor C0 is connected between the drain electrode and the gate electrode.
4. The high-voltage high-drive high-power-supply-rejection-ratio LDO according to claim 3,
the dynamic compensation circuit (200) comprises a MOS tube Mn4, a MOS tube Mn6, a MOS tube Mp2, a MOS tube Mp3, a MOS tube PMOSFET, a resistor R4, a resistor R5 and a capacitor C1,
the grid electrode of the MOS tube Mn5 is connected with the grid electrode of the MOS tube Mn4, the source electrode of the MOS tube Mn4 is grounded, the drain electrode of the MOS tube Mn6 is connected with the source electrode of the MOS tube Mn6, the grid electrode of the MOS tube Mn6 is connected with fixed bias voltage, the drain electrode of the MOS tube Mn6 is connected with one end of a resistor R4, and the other end of the resistor R4 is connected with a high-voltage power supply; the drain electrode of the MOS tube Mn6 is connected with the gate electrode of the MOS tube Mp2, the gate electrode of the MOS tube Mp2 is connected with the drain electrode, the source electrode of the MOS tube Mp2 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a high-voltage power supply, and a capacitor C1 is connected between the other end of the resistor R5 and the drain electrode of the MOS tube Mn 4; the grid electrode of the MOS tube Mp2 is connected with the grid electrode of the MOS tube Mp3, the grid electrode of the MOS tube Mp3 is connected with the drain electrode, and the source electrode of the MOS tube Mp3 is connected with a high-voltage power supply; the grid electrode of the MOS tube Mp3 is connected with the grid electrode of the MOS tube PMOSFET, the source electrode of the MOS tube PMOSFET is connected with a high-voltage power supply, and the drain electrode of the MOS tube PMOSFET serves as an intermediate voltage output end.
5. The high-voltage high-drive high-power-supply-rejection-ratio LDO according to claim 4,
the dynamic compensation circuit (200) further comprises an off-chip resistor REXT0. Off-chip resistance REXT1 and off-chip capacitor CL，
An off-chip resistor R is sequentially connected between the drain electrode of the MOS tube PMOSFET and the grounding point in seriesEXT1 and an off-chip resistance REXT0, off-chip capacitance CLAnd an off-chip resistor REXT1 and an off-chip resistance REXT0 are connected in parallel;
off-chip resistance REXT1 and an off-chip resistance REXTThe outgoing line between 0 serves as a connection terminal VFB, and the connection terminal VFB is connected with the grid electrode of the MOS transistor Mn 1.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113176802A (en) * | 2021-04-16 | 2021-07-27 | 中山大学 | Self-feedback multi-loop fully-integrated low-dropout linear regulator circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113176802A (en) * | 2021-04-16 | 2021-07-27 | 中山大学 | Self-feedback multi-loop fully-integrated low-dropout linear regulator circuit |
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