CN117855289A - Hf doped ITO (indium tin oxide) -based thin film transistor and preparation method thereof - Google Patents
Hf doped ITO (indium tin oxide) -based thin film transistor and preparation method thereof Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 title description 4
- 238000004544 sputter deposition Methods 0.000 claims abstract description 39
- 238000005516 engineering process Methods 0.000 claims abstract description 36
- 239000010408 film Substances 0.000 claims abstract description 31
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000013329 compounding Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000012298 atmosphere Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000012300 argon atmosphere Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 18
- 239000001301 oxygen Substances 0.000 abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 abstract description 18
- 230000007547 defect Effects 0.000 abstract description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 20
- 229910052786 argon Inorganic materials 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
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- 238000002834 transmittance Methods 0.000 description 1
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Abstract
The invention discloses an Hf doped ITO-based thin film transistor and a preparation method thereof. The ITO-based thin film transistor comprises a grid electrode, a grid medium, a channel layer and a source electrode and a drain electrode, wherein the channel layer is formed by compounding an ITO layer and an Hf doped ITO layer. P-type heavily doped silicon is adopted as a grid electrode, siO 2 The film is used as a gate dielectric layer; firstly preparing an ITO layer on a gate dielectric layer by magnetron sputtering, and on the prepared ITO layer, utilizing an ITO target and HfO 2 The target is prepared into an Hf doped ITO layer by a co-sputtering technology to form a channel layer; dividing the sputtered channel layer; after the division, a Mo metal layer is deposited by adopting direct current sputtering, and a source electrode and a drain electrode are formed by adopting a mask pattern, so that the Hf doped ITO-based thin film transistor is obtained. By passing throughThe invention can effectively reduce oxygen vacancy defects in the back channel, inhibit the capture and the capture removal of electrons on the surface of the back channel, thereby improving the stability of the ITO-based thin film transistor.
Description
1. Technical field:
the invention relates to the technical field of semiconductor devices, in particular to an Hf doped ITO (indium tin oxide) -based thin film transistor and a preparation method thereof.
2. The background technology is as follows:
in recent years, oxide semiconductors are widely used in channel materials of Thin Film Transistors (TFTs) due to their advantages of high mobility, good uniformity, low temperature production, and the like. Along with the continuous development of microelectronic circuit systems, flat panel displays and Internet of things, higher requirements are put forward on new generation electronic products which are economical, efficient and energy-saving. However, the commercial industrialized InGaZnO TFT has a mobility of about 10cm 2 Vs, it is difficult to meet the display requirements of advanced display devices for high resolution and high frame rates. Meanwhile, the TFT is required to have smaller starting voltage for portable electronic mobile equipment and small-capacity battery drive, and the TFT is required to have low processing temperature (< 300 ℃) and simple manufacturing process for flexible wearable equipment electronic products. Of the many channel layer materials, inSnO (ITO) has received attention from researchers as a channel layer material due to its high carrier concentration and high transmittance. High mobility is often accompanied by poor stability and negative threshold voltage issues, which certainly pose challenges for practical applications.
In general, device instability is caused by traps present at the semiconductor/insulator interface or back channel. In general, the stability of ITO TFT is improved by adjusting the oxygen vacancy concentration, such as doping N, ta and Ga, etc. However, these studies have focused on improving the bias stress only, and in practical applications, TFTs in a display panel are inevitably affected by moisture and bias stress. Electrolysis of water under Positive Bias Stress (PBS) can lead to electrical performance degradation and high power consumption problems. Because ofIn this case, it is highly demanded to study the influence of moisture and bias stress on the electrical properties and stability of the ITO TFTs. Passivation layers, e.g. HfO 2 、Al 2 O 3 And SiO 2 Water and oxygen can be effectively blocked from entering the channel layer, typically by an Atomic Layer Deposition (ALD) process. However, ALD processes require a rigorous separation of each precursor and slow film growth rates. Furthermore, the existing reports indicate that oxygen-related defects (mainly-OH and Vo) inherent in oxide semiconductors often act as electron capture sites, deteriorating carrier transport. It is necessary to study an oxide semiconductor TFT which is stable at low temperature without further increasing manufacturing complexity.
3. The invention comprises the following steps:
the invention aims to solve the technical problems that: in view of the above problems, TFT devices mainly based on ITO semiconductors are attracting attention as electronic switching devices, but their stability and threshold voltage are often unsatisfactory, limiting the technical problem of their application as channel layers in TFTs. Currently, conventional methods for improving the stability of TFT devices, such as optimizing the material composition of the channel layer, the passivation layer, and the like, have limitations such as deteriorated performance, increased manufacturing cost, or incompatibility with mainstream processes. Therefore, the invention provides an Hf doped ITO-based thin film transistor and a preparation method thereof. According to the technical scheme, when the ultrathin Hf doped ITO (HITO) layer is deposited on the back channel, the characteristic of strong oxygen combination capability is utilized, so that oxygen vacancy defects in the back channel can be effectively reduced, and the capture of electrons on the surface of the back channel are inhibited, so that the stability of the ITO-based thin film transistor is improved.
In order to solve the problems, the invention adopts the following technical scheme:
the invention provides an Hf doped ITO (indium tin oxide) based thin film transistor, which comprises a grid electrode, a grid medium, a channel layer and a source-drain electrode, wherein: the channel layer is formed by compounding an ITO layer and an Hf doped ITO layer.
According to the Hf doped ITO-based thin film transistor, the ITO layer is prepared through a magnetron sputtering technology.
According to the Hf doped ITO based thin film transistor described aboveThe Hf doped ITO layer is formed by an ITO target and HfO 2 The targets are prepared by co-sputtering techniques.
According to the Hf doped ITO-based thin film transistor, the grid electrode adopts a P-type heavily doped silicon thin film; siO prepared by adopting thermal oxidation method on gate dielectric layer 2 A film; the SiO is 2 The thickness of the film was 100nm.
In addition, there is provided a method of manufacturing an Hf doped ITO-based thin film transistor, the method comprising the steps of:
1) Preparing a gate and a gate dielectric: siO prepared by adopting P-type heavily doped silicon film as grid electrode and thermal oxidation method 2 The film is used as a gate dielectric layer;
2) Preparing a channel layer: firstly preparing an ITO layer on a gate dielectric layer by a magnetron sputtering technology, and then utilizing an ITO target and HfO on the prepared ITO layer 2 The target is prepared into an Hf doped ITO layer by a co-sputtering technology to form a channel layer; then dividing the sputtered channel layer into patterns of 500-550 multiplied by 500-550 mu m by using a mask;
3) Source-drain electrode preparation: after the channel layer is segmented, a direct-current sputtering technology is adopted, a Mo metal layer with the thickness of 100nm is deposited under the conditions of pure argon atmosphere and pressure of 0.5-1 Pa, and a mask pattern is adopted to form a source-drain electrode, so that the Hf doped ITO-based thin film transistor is prepared.
According to the preparation method of the Hf doped ITO-based thin film transistor, the SiO in the step 1) 2 The thickness of the film was 100nm.
According to the method for preparing the Hf doped ITO-based thin film transistor, in the step 2), when the ITO layer is prepared by the magnetron sputtering technology, the vacuum degree in the cavity is less than or equal to 2 multiplied by 10 -4 Pa, the ITO radio frequency sputtering power is 40-70W, and the sputtering atmosphere is Ar: o (O) 2 =9: 1, the working air pressure is 0.3-0.7 Pa, and the thickness of the ITO layer is 7-10 nm;
when the co-sputtering technology is used for preparing the Hf doped ITO layer, the vacuum degree in the chamber is less than or equal to 2 multiplied by 10 -4 Pa, double-target co-sputtering, wherein the ITO radio frequency sputtering power is 40-70W, hfO 2 The sputtering power is 10-20W, and the sputtering atmosphere is Ar: o (O) 2 =9: 1, the working air pressure is 0.30.7Pa, and the thickness of the Hf doped ITO layer is 1-2 nm.
According to the preparation method of the Hf doped ITO based thin film transistor, in the step 3), the channel length between the source electrode and the drain electrode is 120 μm, and the width is 150 μm.
According to the preparation method of the Hf doped ITO based thin film transistor, after the Mo metal layer is deposited in the step 3), annealing is performed for 1 hour under the atmospheric condition of 150 ℃.
In the technical scheme of the invention, the oxygen vacancy defect in the channel layer is controlled by adjusting the sputtering power of Hf, firstly, the ITO film with high mobility is deposited, and then, the Hf doped ITO film is deposited.
The invention has the positive beneficial effects that:
1. the invention uses the in-situ magnetron sputtering technology, effectively reduces the manufacturing cost and complexity, and is compatible with the mainstream technology.
2. According to the invention, the ultrathin Hf doped ITO (HITO) layer is deposited on the back channel, and the characteristic of strong oxygen combination capability is utilized, so that oxygen vacancy defects in the back channel can be effectively reduced, the capture and capture of electrons on the surface of the back channel are inhibited, and the stability of the ITO-based thin film transistor is improved.
3. The invention realizes 76.21cm at 150 ℃ low annealing temperature 2 The high mobility of/Vs, threshold voltage of-0.85V, the bias stability of HITO/ITO TFTs under different humid environments is greatly improved.
4. The invention has the advantages of better performance effect than the mainstream IGZO TFT, low manufacturing cost, simple method, high compatibility with the mainstream technology process, good repeatability, suitability for other amorphous oxide semiconductor devices and strong popularization.
4. Description of the drawings:
FIG. 1 is a schematic diagram of the overall structure of an ITO-based thin film transistor;
FIG. 2 shows ITO TFT (comparative example), HITO/ITO TFT (inventive example 1) and HfO, respectively 2 Transfer characteristic curve of ITO TFT (example 2);
FIG. 3 shows ITO TFTs (comparative example), HITO/ITO TFT (inventive example 1) and HfO 2 Electrical properties of ITO TFT (example 2)A performance evolution curve;
FIG. 4 output characteristics of HITO/ITO TFT (example 1 of the invention);
FIG. 5 AFM pictures of ITO TFT (comparative example) film;
FIG. 6 AFM photograph of HITO/ITO TFT (inventive example 1) film;
FIG. 7HfO 2 AFM pictures of ITO TFT (example 2) film;
FIG. 8 shows ITO TFT (comparative example), HITO/ITO TFT (inventive example 1) and HfO 2 ITO TFT (example 2) threshold voltage shift versus time at +20V voltage;
FIG. 9 is a schematic diagram of ITO TFT (comparative example), HITO/ITO TFT (inventive example 1) and HfO 2 ITO TFT (example 2) threshold voltage shift versus time at-20V;
FIG. 10 shows ITO TFT (comparative example), HITO/ITO TFT (inventive example 1) and HfO 2 ITO TFT (example 2) threshold voltage shift results after 3600s at +20V voltage application under different humidity test environments.
5. The specific embodiment is as follows:
the invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Comparative examples:
referring to fig. 1, 2, 3, 5 and 8, an ITO-based thin film transistor includes a gate electrode, a gate dielectric, a channel layer and a source/drain electrode, and the method for preparing the same is as follows:
1) Preparing a gate and a gate dielectric: p-type heavily doped silicon film is adopted as grid electrode, and 100nm thick SiO prepared by thermal oxidation method 2 The film is used as a gate dielectric layer;
2) Preparing a channel layer: preparing an ITO layer on the gate dielectric layer by a magnetron sputtering technology to form a channel layer; then dividing the sputtered channel layer into 500X 500 mu m square blocks by using a mask;
the magnetron sputtering technology comprises the following treatment processes: when the vacuum degree in the cavity is less than or equal to 2 multiplied by 10 -4 After Pa, high-purity argon and oxygen are introduced at flow rates of 12.6sccm and 1.4sccm respectively, and mixed gas is obtainedUnder the conditions of bulk atmosphere, air pressure of 0.5Pa and sputtering power of 50W, sputtering an ITO film with the thickness of 9nm to obtain a channel layer;
3) Source-drain electrode preparation: after the channel layer is segmented, depositing a 100nm thick Mo metal layer under the atmosphere of 0.7pa high-purity argon by adopting a direct-current sputtering technology, and forming a source-drain electrode by adopting a mask pattern to prepare the ITO-based thin film transistor;
the channel length between the source electrode and the drain electrode is 120 μm, and the width is 150 μm; after the deposition of the Mo metal layer, annealing was performed for 1 hour at 150 ℃ under atmospheric conditions.
Inventive example 1:
referring to the drawings, the Hf doped ITO based thin film transistor comprises a grid electrode, a grid medium, a channel layer and a source electrode and a drain electrode, wherein: the channel layer is formed by compounding an ITO layer and an Hf doped ITO layer; the ITO layer is prepared by magnetron sputtering technology, and the Hf doped ITO layer is prepared by an ITO target and HfO 2 The target is prepared by a co-sputtering technology;
further, the grid electrode adopts a P-type heavily doped silicon film; siO prepared by adopting thermal oxidation method on gate dielectric layer 2 A film; the SiO is 2 The thickness of the film was 100nm.
The preparation method of the Hf doped ITO based thin film transistor is basically the same as that of the comparative example, except that:
step 2) preparing a channel layer: firstly preparing an ITO layer on a gate dielectric layer by a magnetron sputtering technology, and then utilizing an ITO target and HfO on the prepared ITO layer 2 The target is prepared into an Hf doped ITO layer by a co-sputtering technology to form a channel layer; then dividing the sputtered channel layer into 50X 500 mu m square blocks by using a mask;
the process for preparing the ITO layer by the magnetron sputtering technology comprises the following steps: when the vacuum degree in the cavity is less than or equal to 2 multiplied by 10 -4 After Pa, high-purity argon and oxygen are introduced, the flow rates of the high-purity argon and the oxygen are respectively 12.6sccm and 1.4sccm, and an ITO layer with the thickness of 9nm is sputtered under the conditions of mixed gas atmosphere, air pressure of 0.5Pa and sputtering power of 50W;
using ITO target and HfO 2 The specific process for preparing the Hf doped ITO layer by the target through the co-sputtering technology is as follows: after depositing an ITO layer with the thickness of 9nm, introducing high-purity argon and oxygen at the flow rates of 12.6sccm and 1.4sccm respectively, and under the environment of mixed gas atmosphere and air pressure of 0.5Pa, the ITO target material and the HfO 2 Sputtering the target for 20s to prepare an Hf doped ITO layer, wherein the thickness of the Hf doped ITO layer is 2nm; wherein the ITO sputtering power is 50W, hfO 2 The sputtering power was 10W.
Example 2:
referring to the drawings, an Hf doped ITO based thin film transistor, comprising a gate electrode, a gate dielectric, a channel layer and a source-drain electrode, wherein: the channel layer is composed of an ITO layer and HfO 2 Layer composite; the ITO layer and HfO 2 The layers are all prepared by magnetron sputtering technology;
further, the grid electrode adopts a P-type heavily doped silicon film; siO prepared by adopting thermal oxidation method on gate dielectric layer 2 A film; the SiO is 2 The thickness of the film was 100nm.
The preparation method of the Hf doped ITO based thin film transistor is basically the same as that of the comparative example, except that:
step 2) preparing a channel layer: firstly preparing an ITO layer on a gate dielectric layer by a magnetron sputtering technology, and then utilizing HfO on the prepared ITO layer 2 The target is prepared into HfO by magnetron sputtering technology 2 A layer forming a channel layer; then dividing the sputtered channel layer into 500X 500 mu m square blocks by using a mask;
the process for preparing the ITO layer by the magnetron sputtering technology comprises the following steps: when the vacuum degree in the cavity is less than or equal to 2 multiplied by 10 -4 After Pa, high-purity argon and oxygen are introduced, the flow rates of the high-purity argon and the oxygen are respectively 12.6sccm and 1.4sccm, and an ITO layer with the thickness of 9nm is sputtered under the conditions of mixed gas atmosphere, air pressure of 0.5Pa and sputtering power of 50W;
preparation of HfO by magnetron sputtering technology 2 The treatment process of the layer comprises the following steps: depositing HfO on the 9nm ITO layer by using magnetron sputtering technology 2 In the sputtering process, high-purity argon and oxygen are introduced, the flow rates of the high-purity argon and the oxygen are respectively 12.6sccm and 1.4sccm, and the high-purity argon and the oxygen are in the mixed gas atmosphereThe air pressure is 0.5Pa, hfO 2 Sputtering for 20s under the condition of sputtering power of 10W target to form HfO 2 A layer;
step 3) preparing a source-drain electrode: the source and drain electrode material is Mo, after the communication layer is divided, a direct current sputtering technology is adopted, and 100nm is deposited under the pure argon atmosphere and 0.7 Pa; annealing on a hot plate at 150 ℃ for 1 hour after the electrode deposition is completed; preparing an ITO-based thin film transistor; the channel length between the source and drain electrodes of the obtained thin film transistor was 120 μm and the width was 150. Mu.m.
Analysis of the results of the ITO thin film transistors prepared in the above examples:
and testing the electrical property of the thin film transistor by using a semiconductor parameter analyzer. As shown in FIGS. 2 and 3, the threshold voltage of the comparative example was-9.73V and the field effect mobility was 83.56cm 2 Vs; the threshold voltage obtained for the device of example 1 was significantly shifted positive by-0.85V, field effect mobility 76.21cm 2 Vs, contributing to lower power consumption; the threshold voltage of example 2 was further shifted to-0.24V compared to example 1, but the mobility was significantly deteriorated as low as 42.52cm 2 /Vs。
Fig. 4 is an output characteristic of example 1, showing a significant saturation region, illustrating good ohmic contact between the electrode and the channel.
As can be seen from FIGS. 5-7, the ITO thin film has a higher roughness (0.585 nm) because of its thin, porous nature caused by the low annealing temperature of 150 ℃. In contrast, HITO/ITO films have smoother surfaces, lower root mean square values (0.499 nm), and higher film densities, effectively reducing surface scattering. HfO (HfO) 2 The ITO film appears sharp and rough, and the surface roughness is obviously improved to 1.410nm. The roughened surface may produce a greater scattering effect, resulting in a reduced stability of the TFT.
As can be seen from fig. 8-9, the HITO/ITO TFT exhibited significantly optimized bias stability after applying 3600s bias stress. FIG. 10 shows test results at different humidity levels for HITO/ITO TFTs that each exhibit acceptable threshold voltage shifts.
In conclusion, the invention can reduce the number of back channel defects through Hf doping, ensure compact and smooth film surface through reasonable sputtering power, and reduce performance deterioration caused by rough scattering.
According to the invention, the threshold voltage is reduced while the high mobility is ensured by doping the back channel interface; the in-situ magnetron sputtering technology is compatible with the current industrial technology, and the preparation technology is simple and controllable and is convenient to popularize and apply.
From the foregoing, it will be seen that the basic principles and advantages of the invention have been set forth. Although some examples have been given for detailed explanation, they should not be limited to these examples; those skilled in the art will appreciate that many changes and modifications can be made to the invention without departing from the core concept of the invention, all of which are within the scope of the invention as claimed. The final scope will be determined by the dependent claims.
Claims (9)
1. An Hf doped ITO based thin film transistor comprising a gate electrode, a gate dielectric, a channel layer, and a source drain electrode, characterized in that: the channel layer is formed by compounding an ITO layer and an Hf doped ITO layer.
2. The Hf doped ITO based thin film transistor of claim 1, wherein: the ITO layer is prepared by a magnetron sputtering technology.
3. The Hf doped ITO based thin film transistor of claim 1, wherein: the Hf doped ITO layer is formed by an ITO target and HfO 2 The targets are prepared by co-sputtering techniques.
4. The Hf doped ITO based thin film transistor of claim 1, wherein: the grid electrode adopts a P-type heavily doped silicon film; siO prepared by adopting thermal oxidation method on gate dielectric layer 2 A film; the SiO is 2 The thickness of the film was 100nm.
5. A method for preparing an Hf doped ITO-based thin film transistor, the method comprising the steps of:
1) Preparing a gate and a gate dielectric: siO prepared by adopting P-type heavily doped silicon film as grid electrode and thermal oxidation method 2 The film is used as a gate dielectric layer;
2) Preparing a channel layer: firstly preparing an ITO layer on a gate dielectric layer by a magnetron sputtering technology, and then utilizing an ITO target and HfO on the prepared ITO layer 2 The target is prepared into an Hf doped ITO layer by a co-sputtering technology to form a channel layer; then dividing the sputtered channel layer into patterns of 500-550 multiplied by 500-550 mu m by using a mask;
3) Source-drain electrode preparation: after the channel layer is segmented, a direct-current sputtering technology is adopted, a Mo metal layer with the thickness of 100nm is deposited under the conditions of pure argon atmosphere and pressure of 0.5-1 Pa, and a mask pattern is adopted to form a source-drain electrode, so that the Hf doped ITO-based thin film transistor is prepared.
6. The method for manufacturing an Hf doped ITO based thin film transistor of claim 5, wherein: siO as described in step 1) 2 The thickness of the film was 100nm.
7. The method for manufacturing an Hf doped ITO based thin film transistor of claim 5, wherein: when the ITO layer is prepared by the magnetron sputtering technology in the step 2), the vacuum degree in the cavity is less than or equal to 2 multiplied by 10 -4 Pa, the ITO radio frequency sputtering power is 40-70W, and the sputtering atmosphere is Ar: o (O) 2 =9: 1, the working air pressure is 0.3-0.7 Pa, and the thickness of the ITO layer is 7-10 nm;
when the co-sputtering technology is used for preparing the Hf doped ITO layer, the vacuum degree in the chamber is less than or equal to 2 multiplied by 10 -4 Pa, double-target co-sputtering, wherein the ITO radio frequency sputtering power is 40-70W, hfO 2 The sputtering power is 10-20W, and the sputtering atmosphere is Ar: o (O) 2 =9: 1, the working air pressure is 0.3-0.7 Pa, and the thickness of the Hf doped ITO layer is 1-2 nm.
8. The method for manufacturing an Hf doped ITO based thin film transistor of claim 5, wherein: the channel length between the source and drain electrodes in step 3) was 120 μm and the width was 150 μm.
9. The method for manufacturing an Hf doped ITO based thin film transistor of claim 5, wherein: after the deposition of the Mo metal layer described in step 3), an annealing treatment was performed at 150 ℃ for 1 hour under atmospheric conditions.
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