CN113013250B - Field effect transistor and preparation method thereof - Google Patents

Field effect transistor and preparation method thereof Download PDF

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CN113013250B
CN113013250B CN202110205068.3A CN202110205068A CN113013250B CN 113013250 B CN113013250 B CN 113013250B CN 202110205068 A CN202110205068 A CN 202110205068A CN 113013250 B CN113013250 B CN 113013250B
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insulating layer
metal
magnetron sputtering
titanium
gate electrode
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CN113013250A (en
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董俊辰
李琪
韩德栋
王漪
张兴
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Abstract

The invention discloses a field effect transistor and a preparation method thereof, belonging to the field of microelectronic devices. The field effect transistor comprises a substrate, a gate electrode, a metal-insulating layer dielectric medium, an active layer and a source/drain electrode, wherein the gate electrode is positioned on the substrate, the metal-insulating layer dielectric medium is positioned on the gate electrode, the active layer is positioned on the metal-insulating layer dielectric medium, the source/drain electrode is positioned on the active layer, the metal-insulating layer dielectric medium structure adopts a sandwich structure of aluminum oxide/titanium/aluminum oxide, the thicknesses of the aluminum oxide thin films are respectively 10-100 nanometers, the titanium thin film is a metal titanium thin film or a titanium oxide thin film, and the thickness of the titanium thin film is 10-100 nanometers. The invention provides a novel high-k dielectric material for a microelectronic device, the metal-insulating layer mixed dielectric is prepared by adopting magnetron sputtering and atomic layer deposition processes, and the metal-insulating layer mixed dielectric material has the advantages of simple steps, low cost and practical application potential.

Description

Field effect transistor and preparation method thereof
Technical Field
The invention belongs to the field of integrated circuit micro-nano electronic devices, and particularly relates to a field effect transistor and a preparation method thereof.
Background
Integrated circuits are the cornerstone of modern information technology and have played a very important role in various industries. China has huge demand of integrated circuits, and the import quantity of 2020 year all the year is up to 3515 hundred million dollars. Recently, the investment of the integrated circuit industry is increased in China, the related technologies make great progress, the innovation capability is continuously improved, and the problems that the technical level is not enough, the product is still at the middle and low end and the like still exist.
Micro-nano electronic devices are the basis of integrated circuits, and the most representative device is a Metal oxide semiconductor field-effect transistor (MOSFET). In order to better reduce the leakage current of MOSFET deviceOne important direction of research is to enhance the ability of MOSFET gate dielectrics to control channel carriers, i.e., gate control, to improve circuit integration. There are two main technical paths for enhancing the gating capability: (1) using high-k dielectric material instead of SiO 2 A dielectric; (2) a three-dimensional structure is used to increase the gate control area of MOSFET devices, such as fin-field-effect transistors (finfets). The combination of the two technical routes can further improve the gate control capability of the MOSFET. In addition, devices such as a nanosheet transistor (nanosheet transistor), a nanowire transistor (nanowire transistor), a negative capacitance transistor (negative capacitance transistor) and the like, which have been proposed in recent years, can be regarded as an extension of the above two technical routes. However, in the aspect of integrated circuit preparation process, China has few core patents on the technology. Therefore, the development and research of the original technology of the gate dielectric material and the structure have very important research value, and have great significance on the development of the integrated circuit technology in China.
The more widely used high-k dielectric materials are typically transition metal oxides, such as hafnium oxide (HfO) 2 ) Zirconium oxide (ZrO) 2 ) Titanium oxide (TiO) 2 ) And the like. Hafnium oxide dielectric technology is well established and is commercialized by the intel 45nm process. The dielectric constant (k 80-110) of titanium oxide is much higher than that of hafnium oxide (k 20-25) and zirconium oxide (k 20-30). However, the dielectric constant is inversely related to the band gap width, and the reduction of the band gap width deteriorates the device reliability. Oxygen defects and grain boundaries can be formed during the preparation of the titanium oxide dielectric, which seriously affect the performance of the device and show that the mobility of carriers is reduced. In addition, with SiO 2 The high-k dielectric/Si active layer interface has a poor quality compared to the dielectric/Si active layer interface, and may also adversely affect device performance. Therefore, innovative research on titanium-based gate dielectric materials and structures and application of related patents have great value for future development of integrated circuits in China.
Disclosure of Invention
The invention aims to provide a field effect transistor and a preparation method thereof. The invention adopts a novel metal-insulating layer mixed dielectric medium with a sandwich structure, and the metal-insulating layer mixed dielectric medium adopts an alumina/titanium/alumina structure.
The technical scheme of the invention is that,
the invention provides a field effect transistor which is characterized by comprising a substrate, a gate electrode, a metal-insulating layer dielectric medium, an active layer and a source/drain electrode, wherein the gate electrode is positioned on the substrate, the metal-insulating layer dielectric medium is positioned on the gate electrode, the active layer is positioned on the metal-insulating layer dielectric medium, the source/drain electrode is positioned on the active layer, the metal-insulating layer dielectric medium structure adopts a sandwich structure of aluminum oxide/titanium/aluminum oxide, the thicknesses of the aluminum oxide films are respectively 10-100 nanometers, the titanium film is a metal titanium film or a titanium oxide film, and the thickness of the titanium film is 10-100 nanometers.
The gate electrode is one or a combination of more of metals such as Al, Ti, Mo and the like, or one or a combination of more of conductive films such as a transparent conductive film ITO, AZO and the like, and the thickness of the gate electrode is 100-500 nanometers.
The thickness of the metal-insulating layer mixed dielectric medium is 30-300 nanometers.
The active layer is zinc oxide or a doped zinc oxide film, and the thickness of the active layer is 10-100 nanometers. For the doped zinc oxide, the doping element is one or a combination of more of metal elements such as aluminum, tin, molybdenum and titanium, inorganic nonmetal elements such as silicon, carbon and phosphorus, or rare earth elements such as lanthanum and erbium. The content of doping elements in the zinc oxide doping film is as follows: 0.1 to 20 percent of doping element.
The source/drain electrode is one or more of Al, Ti, Mo and other metals, or one or more of transparent conductive films ITO, AZO and other conductive films, and the thickness of the source/drain electrode is 100-500 nm.
Meanwhile, the invention provides a preparation method of the field effect transistor. The method comprises the following specific steps:
(1) sequentially placing the substrate in acetone, ethanol and deionized water for ultrasonic cleaning;
(2) depositing a gate electrode on the surface of the substrate by adopting a magnetron sputtering process;
(3) depositing a metal-insulating layer dielectric on the gate electrode by adopting a magnetron sputtering process and an atomic layer electrode process;
(4) depositing an active layer on the metal-insulating layer dielectric by adopting an atomic layer deposition process or a magnetron sputtering process;
(5) depositing a source/drain electrode on the active layer by adopting a magnetron sputtering process;
(6) and (4) optimizing the field effect transistor by adopting an annealing process.
The specific preparation process of the metal-insulating layer dielectric in the step (3) comprises the following steps:
(a) the substrate is fixed in the reaction cavity of the atomic layer deposition equipment;
(b) pumping the pressure at the back bottom of the reaction cavity to 50-100 Pa;
(c) introducing nitrogen into the reaction cavity, wherein the reaction temperature is set to be 100-200 ℃;
(d) introducing a reaction source into the reaction chamber, and starting to deposit the bottom insulating layer, wherein the reaction source comprises trimethylaluminum and deionized water (H) 2 O)；
(e) Closing the atomic layer deposition equipment after the deposition of the aluminum oxide film insulating layer (bottom layer) is finished;
(f) fixing the substrate with the insulating layer on the surface on a tray of the magnetron sputtering equipment;
(g) the back bottom air pressure of the cavity of the magnetron sputtering equipment is pumped to 1 multiplied by 10 -4 -9×10 -4 Handkerchief;
(h) introducing oxygen and argon into a cavity of the magnetron sputtering equipment, adjusting an air pressure control valve, and setting the air pressure of the cavity to be 1 Pa;
(i) opening a tray rotating button, and setting the rotating speed to be 10-15 revolutions per minute;
(j) turning on a power supply, pre-sputtering for 2-5 minutes, wherein the sputtering target used by the magnetron sputtering process is a metallic titanium target;
(l) Rotating the magnetron sputtering target baffle plate, and formally sputtering for 20-30 minutes;
(m) after the titanium film deposition is finished, turning off the radio frequency power supply and turning off the instrument;
(n) repeating steps (a) - (e) and depositing another thin film insulating layer of aluminum oxide (top layer).
The invention has the advantages that:
(1) the invention provides a novel high-k dielectric material for microelectronic devices, which has strong originality and provides technical support for the development of integrated circuits in China. (2) The metal-insulating layer mixed dielectric prepared by the invention is prepared by adopting magnetron sputtering and atomic layer deposition processes, and has simple steps and low cost. (3) The field effect transistor has excellent performance and practical application potential.
Drawings
FIG. 1 is a schematic view of a field effect transistor fabricated in accordance with the present invention;
FIG. 2 is a schematic diagram of a metal-insulator hybrid dielectric structure according to the present invention;
FIG. 3 is a graph showing current-voltage characteristics of a field effect transistor fabricated according to the present invention;
1-a substrate; 2-a gate electrode; 3-metal-insulator layer dielectric; 4-an active layer; 5-source/drain electrodes; 6-an aluminum oxide film; 7-titanium thin film.
Detailed Description
The invention is further illustrated by way of example in the accompanying drawings. It is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Fig. 1 shows a field effect transistor of the present invention, which includes a substrate, a gate electrode on the substrate, a metal-insulator dielectric on the gate electrode, an active layer on the metal-insulator dielectric, and source/drain electrodes on the active layer.
The titanium film is sandwiched between two aluminum oxide films in the metal-insulating layer mixed dielectric structure shown in fig. 2. The thickness of the aluminum oxide film is 10-100 nanometers, the titanium film is a metal titanium film or a titanium oxide film, and the thickness of the titanium film is 10-100 nanometers.
The field effect transistor active layer takes zinc oxide as an example, and the specific preparation process comprises the following steps:
(1) and (3) sequentially placing the glass substrate in acetone, ethanol and deionized water for ultrasonic cleaning for 5 minutes.
(2) Depositing a metal aluminum film on a glass substrate by a magnetron sputtering process, wherein the thickness of the aluminum film is 100 nm; and forming an aluminum gate electrode pattern by adopting photoetching and etching processes.
(3) Depositing a metal-insulating layer mixed dielectric on the gate electrode; and forming a metal-insulating layer mixed dielectric pattern by adopting photoetching and etching processes.
(4) Depositing a zinc oxide film on the metal-insulating layer mixed dielectric medium by a magnetron sputtering process, wherein the thickness of the zinc oxide film is 30 nm; and forming a zinc oxide active layer pattern by adopting photoetching and etching processes.
(5) Depositing a metal aluminum film on the zinc oxide active layer by a magnetron sputtering process, wherein the thickness of the aluminum film is 100 nm; and forming an aluminum source/drain electrode pattern by adopting photoetching and etching processes.
(6) And (3) optimizing the transistor by using an annealing furnace, wherein the annealing temperature is 300 ℃, the annealing time is 1 hour, and the annealing atmosphere is vacuum.
The metal-insulating layer mixed dielectric provided by the invention comprises the following specific steps:
(1) and fixing the glass substrate in the reaction cavity of the atomic layer deposition equipment.
(2) The pressure of the back bottom of the reaction cavity of the atomic layer deposition equipment is pumped to 70 Pa.
(3) And introducing nitrogen into the reaction cavity of the atomic layer deposition equipment, and setting the reaction temperature to be 150 ℃.
(4) And introducing a reaction source into the reaction cavity of the atomic layer deposition equipment, and beginning to deposit the alumina film. The reaction source used was trimethylaluminum (trimethylaluminum) and deionized water (H) 2 O). During the reaction, trimethyl aluminum (trimethyl aluminum) and deionized water (H) 2 O) cycle number 50.
(5) And closing the atomic layer deposition equipment after the deposition of the aluminum oxide film insulating layer (bottom) is finished.
(6) The substrate with the insulating layer (bottom) grown on the surface is fixed on a tray of the magnetron sputtering equipment.
(7) The back bottom air pressure of the cavity of the magnetron sputtering equipment is pumped to 5 multiplied by 10 -4 And (6) handkerchief.
(8) Oxygen and argon are introduced into a cavity of the magnetron sputtering equipment, and the flow ratio of the oxygen to the argon is 10: 90. And adjusting the air pressure control valve to set the air pressure of the cavity to be 1 Pa.
(9) The tray rotation button was turned on and the rotation speed was set to 15 rpm.
(10) And turning on a power supply, and pre-sputtering for 2 minutes. The sputtering target material used in the magnetron sputtering process is a metallic titanium target.
(11) And rotating the magnetron sputtering target baffle plate, and formally sputtering for 30 minutes.
(12) And after the titanium film deposition is finished, the radio frequency power supply is turned off, and the instrument is turned off.
(13) And (5) repeating the steps (1) to (5) and depositing an aluminum oxide film insulating layer (top).
The current-voltage characteristics of the field effect transistor prepared by the invention are shown in figure 3, and the device shows good transfer characteristics, field effect mobility>25cm 2 V -1 s -1 。
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the means and techniques disclosed above, without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (8)

1. A field effect transistor is characterized by comprising a substrate, a gate electrode, a metal-insulating layer dielectric medium, an active layer and a source/drain electrode, wherein the gate electrode is positioned on the substrate, the metal-insulating layer dielectric medium is positioned on the gate electrode, the active layer is positioned on the metal-insulating layer dielectric medium, the source/drain electrode is positioned on the active layer, the metal-insulating layer dielectric medium structure adopts a sandwich structure of aluminum oxide/titanium/aluminum oxide, the thicknesses of the aluminum oxide films are respectively 10-100 nanometers, the titanium film is a metal titanium film or a titanium oxide film, and the thickness of the titanium film is 10-100 nanometers.
2. The FET of claim 1, wherein the gate electrode is one or more of Al, Ti, Mo, ITO, AZO, or combinations thereof, and has a thickness of 100-500 nm.
3. The field effect transistor of claim 1, wherein said active layer is zinc oxide or a doped zinc oxide thin film, said active layer having a thickness of 10-100 nm.
4. The FET of claim 3, wherein the doped ZnO and the doping element are Al, Sn, Mo, Ti, Si, C, P, or La, Er, or a combination of one or more rare earth elements.
5. The field effect transistor of claim 4, wherein the doped zinc oxide film comprises the following doping elements: 0.1 to 20 percent of doping element.
6. The FET of claim 1, wherein the source/drain electrode is one or a combination of Al, Ti, Mo metals, or one or a combination of ITO and AZO transparent conductive films, and the thickness of the source/drain electrode is 100-500 nm.
7. The method of manufacturing a field effect transistor according to claim 1, comprising the steps of:
(1) sequentially placing the substrate in acetone, ethanol and deionized water for ultrasonic cleaning;
(2) depositing a gate electrode on the surface of the substrate by adopting a magnetron sputtering process;
(3) depositing a metal-insulating layer mixed dielectric on the gate electrode by adopting a magnetron sputtering process and an atomic layer electrode process;
(4) depositing an active layer on the metal-insulating layer mixed dielectric medium by adopting an atomic layer deposition process or a magnetron sputtering process;
(5) depositing a source/drain electrode on the active layer by adopting a magnetron sputtering process;
(6) and optimizing the field effect transistor by adopting an annealing process.
8. The preparation method according to claim 7, wherein the step (3) comprises the following specific steps:
(a) the substrate is fixed in the reaction cavity of the atomic layer deposition equipment;
(b) pumping the pressure at the back bottom of the reaction cavity to 50-100 Pa;
(c) introducing nitrogen into the reaction cavity, wherein the reaction temperature is set to be 100-200 ℃;
(d) introducing a reaction source into the reaction chamber, and starting to deposit the bottom insulating layer, wherein the reaction source comprises trimethylaluminum and deionized water (H) 2 O)；
(e) Closing the atomic layer deposition equipment after the deposition of the aluminum oxide film insulating layer is finished;
(f) fixing the substrate with the insulating layer on the surface on a tray of the magnetron sputtering equipment;
(g) the back bottom air pressure of the cavity of the magnetron sputtering equipment is pumped to 1 multiplied by 10 -4 -9×10 -4 Handkerchief;
(h) introducing oxygen and argon into a cavity of the magnetron sputtering equipment, adjusting an air pressure control valve, and setting the air pressure of the cavity to be 1 Pa;
(i) opening a tray rotating button, and setting the rotating speed to be 10-15 revolutions per minute;
(j) turning on a power supply, pre-sputtering for 2-5 minutes, wherein a sputtering target material used by the magnetron sputtering process is a metal titanium target;
(l) Rotating the magnetron sputtering target baffle plate, and formally sputtering for 20-30 minutes;
(m) after the titanium film deposition is finished, turning off the radio frequency power supply and turning off the instrument;
(n) repeating steps (a) - (e) and depositing another thin film insulating layer of aluminum oxide.
CN202110205068.3A 2021-02-24 2021-02-24 Field effect transistor and preparation method thereof Active CN113013250B (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
CN101162737A (en) * 2006-10-12 2008-04-16 施乐公司 Thin film transistor using an oriented zinc oxide layer

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US7588988B2 (en) * 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US20060091483A1 (en) * 2004-11-02 2006-05-04 Doczy Mark L Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
US7524727B2 (en) * 2005-12-30 2009-04-28 Intel Corporation Gate electrode having a capping layer
CN103311110B (en) * 2012-03-12 2016-08-31 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure, the forming method of transistor

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CN101162737A (en) * 2006-10-12 2008-04-16 施乐公司 Thin film transistor using an oriented zinc oxide layer

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