CN1178294C - 电子元件 - Google Patents

电子元件 Download PDF

Info

Publication number
CN1178294C
CN1178294C CNB021319715A CN02131971A CN1178294C CN 1178294 C CN1178294 C CN 1178294C CN B021319715 A CNB021319715 A CN B021319715A CN 02131971 A CN02131971 A CN 02131971A CN 1178294 C CN1178294 C CN 1178294C
Authority
CN
China
Prior art keywords
sealing ring
cover board
metal cover
chip carrier
wave device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB021319715A
Other languages
English (en)
Other versions
CN1404144A (zh
Inventor
松田英�
松田英樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN1404144A publication Critical patent/CN1404144A/zh
Application granted granted Critical
Publication of CN1178294C publication Critical patent/CN1178294C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00015Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

本发明揭示一种电子元件,包括在具有凹部的陶瓷制的芯片载体2的该凹部内,存放入声表面波元件芯片3。围住芯片载体2的凹部开口,将可伐铁镍钴合金制的密封圈4用Ag焊料焊接在芯片载体2的上面。放置在密封圈4上的可伐铁镍钴合金制的金属盖板5的表面上施加镍镀层,以该镍镀层作为焊材,将金属盖板5缝焊在密封圈4上。该镍镀层的厚度取1~2μm,可保证金属盖板5与密封圈4之间良好的气密性。在将元件芯片存放在陶瓷制的芯片载体内,芯片载体上面的密封圈上焊有盖板,使元件芯片气密封止的电子元件中,能确保被镀镍的盖板与密封圈间的充分的气密性。

Description

电子元件
技术领域
本发明涉及封装的声表面波装置等的电子元件,特别涉及在陶瓷制的芯片载体内存有元件芯片,通过缝焊把盖板焊接到密封圈上以实现气密封止的电子元件。
背景技术
把声表面波单元封装而成的声表面波装置,广泛应用于移动通信机的RF段用滤波器及IF段用滤波器等的各领域。作为此种用途的声表面波装置的封装构造的一例,见图1的剖视图,以下对这种构造加以说明。
这种声表面波装置1,由芯片载体2,声表面波元件芯片3,密封圈4,及金属盖板5构成。在芯片载体2、密封圈4及盖板5构成的封装体内,声表面波元件芯片3被气密封止。在构造上,芯片载体2在实质上矩形板状的陶瓷构成的基极6上,由多层陶瓷层7,8堆压而成。密封圈4,由可伐铁镍钴合金(Fe-Co-Ni合金)形成环状。在最上层的陶瓷层8上重合着密封圈4,通过Ag焊料等把密封圈4带焊料放在陶瓷层8的上面。此外,密封圈4的表面,通常进行衬底用Ni缝焊,结束用Au缝焊。
下层的陶瓷层7内侧有实质上矩形的开口9,这陶瓷层7的上面形成有多个电极部分10。从各电极部分10的端部,经陶瓷层7及基极6的侧面到基极6的下面形成外部电极11。电极部分10及外部电极11,通常在W(钨)金属化电极上进行衬底用Ni缝焊,结束用Au缝焊来形成的。上层的陶瓷层8上形成有同样实质上矩形的开口12,这样芯片载体2上,通过陶瓷层7,8的开口9,12形成存储空间14。另外,密封圈4上也开有实质上矩形的开口13。
声表面波元件芯片3被存入芯片载体2的存储空间14内,在存储空间14的基极6的上面用粘接剂固定。声表面波元件芯片3用焊接线15把相应电极与各电极部分10作电气连接,通过外部电极11,可将声表面波元件芯片3的各电极与外部进行电气连接。
把声表面波元件芯片3实装入芯片载体2内后,密封圈4上将封止用的金属盖板5重叠作缝焊,用金属盖板5对密封圈4的开口13作气密封止。封止用的金属盖板5是与密封圈4同样以可伐铁镍钴合金作为母材的,金属盖板5的表面进行镍镀。作为这种镍镀,过去用的是有3μm以上的较厚镀层的大镀件。另外,可伐铁镍钴合金是一种热膨胀系数接近于陶瓷的金属,作为密封圈4及金属盖板5的母材,由于应用可伐铁镍钴合金,应当防止在焊接时及焊接后冷却时因密封圈4及金属盖板5与陶瓷的芯片载体2之间的膨胀率差异导致芯片载体2上产生偏歪,以及应力导致裂缝的产生。
在这样构造的声表面波装置1中,通过同时烧成基极6,陶瓷层7、8,及电极部分10,将芯片载体2形成为一体。在芯片载体2的上面,采用Ag焊料使密封圈4带上焊料,以保证芯片载体2与密封圈4之间的气密性。还有,密封圈4上重叠有金属盖板5,将表面的镍镀层作为焊材进行缝焊,使金属盖板5焊接于密封圈4,以保持密封圈4与金属盖板5之间的气密性。这样,声表面波元件芯片3在由芯片载体2、密封圈4、及金属盖板5构成的封装构造中可被气密封止,确保了声表面波装置1的防水性及防湿性。此外,不使用其他焊料,以金属盖板5的镍镀层使金属盖板5焊接于密封圈4,焊接成本可降低,同时,可避免焊料涂布离散导致的焊接参数的离散。
此外,作为另外的封装构造的声表面波装置,也有如图2所示那样构造的。这是将声表面波元件芯片3面朝下实装的。声表面波元件芯片3的凸头16与基极6上面的电极部分17电气连接。
例如,在图1那样的声表面波装置1中,金属盖板5焊接于密封圈4,作为气密封止手段,采用缝焊。图3展示金属盖板5与密封圈4焊接的情况。在缝焊场合,如图3所示,实装着声表面波元件芯片3的芯片载体2上的密封圈4上,放置金属盖板5后,使一对筒形电极18a、18b与金属盖板5的角部接触,用交流电源19使焊接电流I1+I2流过两筒形电极18a、18b之间,使两筒形电极18a、18b转动,并沿金属盖板5的外周移动。靠此时发生的焦耳热量使密封圈4与金属盖板5的镍镀层融化,使金属盖板5焊接于密封圈4。由于两筒形电极18a、18b沿着金属盖板5全周移动,可使金属盖板5全周焊接于密封圈4上。即,金属盖板5的镍镀层与密封圈4的镀层作为焊材,将密封圈4与金属盖板5实现焊接。这样的缝焊能实现封装构造的高气密性。
但是,即使用这样的缝焊,由于用来进行缝焊的焊机的细小的条件变化及芯片载体的个体差异,有时也发生气密性不很好。从而成为声表面波装置的合格率及可靠性下降的原因。
本发明针对上述以往例中存在的问题,目的在于将元件芯片存于陶瓷制的芯片载体内,在芯片载体上面的密封圈上焊接盖板,将元件芯片气密封止的电子元件中,镀镍的盖板与密封圈之间确保充分的气密封性。
发明内容
本发明的电子元件,在包括具有凹部的陶瓷制的芯片载体,收容在上述芯片载体的凹部开口内的芯片,把上述芯片载体的凹部开口围住并与芯片载体焊接的金属密封圈,以及用来堵塞上述密封圈的开口、对上述凹部气密封止的金属盖板的声表面波装置中,上述盖板的表面施加厚度为1~2μm的镍镀层,用于与上述密封圈连接。因此,作为将上述盖板焊到密封圈上的方法,最好是以表面的镍镀层作为焊材,把盖板缝焊在密封圈上。
本发明的电子元件,用在密封圈上焊接盖板的镍镀层的厚度薄得只有1~2μm。使制造盖板与密封圈的焊接性良好,盖板与密封圈之间的气密性,防水性,防湿性都能得到改善,可靠性高的声表面波装置成为可能。特别是,作为镍镀层,由于采用无电解镍镀层,使高气密性进一步得到实现。
附图说明
图1表示声表面波装置的构造剖视图。
图2表示另一种封装构造的声表面波装置的构造剖视图。
图3表示用焊机将声表面波装置的金属盖板缝焊到密封圈的情况的概略图。
图4表示金属盖板表面的镍镀层厚度为1~2μm的声表面波装置中的精密泄漏率的分布情况的测量结果图。
图5表示金属盖板表面的镍镀层厚度为3~4μm的声表面波装置中的精密泄漏率的分布情况的测量结果图。
图6表示金属盖板表面的镍镀层厚度为5~6μm的声表面波装置中的精密泄漏率的分布情况的测量结果图。
图7表示对于金属盖板的镍镀层厚度为5~6μm的声表面波装置,在湿中放置试验中随着时间经过测量频率变化量的结果图。
图8表示对于金属盖板的镍镀层厚度为1~2μm的组的声表面波装置,在湿中放置试验中随着时间经过测量频率变化量的结果图。
符号说明
1声表面波装置
2芯片载体
3声表面波元件芯片
4密封圈
5金属盖板
6基极
7陶瓷层
8陶瓷层
9开口
10电极部分
11外部电极
18a,18b筒形电极
19交流电源
具体实施形态
下面说明本发明的实施形态。本发明的声表面波装置的实施形态,具有与图1所示的以往例相同的构造,因此,为节省篇幅,省略了图示,举与图1构造相同的例进行说明。另外说明中以与以往例的不同点作为中心,关于同一构造的部材引用图1中的符号进行说明。又,对于涉及本申请的声表面波装置,可使用于图2所示的面朝下的实装声表面波元件芯片3的装置。还有,在本发明的声表面波装置中,金属盖板5缝焊到密封圈4的方法也与图3所示的一样,关于缝焊的方法,引用图3及其符号进行说明。
如在以往例中说明的那样,在以往的声表面波装置中,把金属盖板5缝焊到密封圈4上时,由于用来进行缝焊的焊机的细小的条件变化及芯片载体2的个体差异,有时也发生气密性不很好。从而成为合格率及可靠性下降的原因。对于这样的问题,在本发明中,对可伐铁镍钴合金制的金属盖板5的镍镀层的厚度加以关注。
利用如图3所示的缝焊的焊机,研究一下声表面波装置中流动的电流。两筒形电极18a、18b中电流流过的路径中,一方的电流路径,如图3中用箭头I1示出的电流那样,从一方的筒形电极18a(或,筒形电极18b)流向金属盖板5,通过金属盖板5中流出到另一方的筒形电极18b(或,筒形电极18a)。另外,另一方的电流路径,如图3中用箭头I2示出的电流那样,从一方的筒形电极18a(或,筒形电极18b)通过金属盖板5流向密封圈4,通过密封圈4中流出到另一方的筒形电极18b(或,筒形电极18a)侧,通过金属盖板5从另一方的筒形电极18b(或,筒形电极18a)流出。对于密封圈4与金属盖板5的气密性或者对焊接性来说,它们的焊接电流I1,I2中认为从I2给予的大,即,通过更增大焊接电流I2,金属盖板5与密封圈4之间界面的焦耳热量产生得更大,其结果可促进镍镀层的融化,提高了焊接性,改善了气密性。
不过,焊接电流I1,I2,对于焊机的某一焊接条件是一定的,增大I2时,相对I1就应减小。此时,金属盖板5的表面的镍镀层的厚度变薄,可通过增大I1流过部分的电阻来实现。从这方面考察,使封止用的金属盖板5的表面所加的镍镀层的厚度减薄,可推测能使气密性提高。
这里,为证明这一点,在加于表面的镍镀层的厚度1~2μm,3~4μm,5~6μm各范围内取3组的可伐铁镍钴合金制的金属盖板5作准备,然后,分别对各组的金属盖板5适用4种焊接条件,把金属盖板5焊接到密封圈4上,组装成声表面波装置。然后,检查各声表面波装置的精密泄漏率,在金属盖板5表面的镍镀层厚度为1~2μm的组,它的精密泄漏率的分布如图4所示。另外,在金属盖板5表面的镍镀层厚度为3~4μm的组,它的精密泄漏率的分布如图5所示。又,在金属盖板5表面的镍镀层厚度为5~6μm的组,它的精密泄漏率的分布如图6所示。还有,在图4~图6中的「E」是表示指数部的标志,例如,3.8E-11表示3.8×10-11
这里,所谓精密泄漏率,是按JIS等通用标准规定的表示气密封性程度的指标。高压的He气体中关闭一定时间时抽样,如抽样结果为完全气密封状态,则He气不能侵入样品内部。如气密性受损,样品内充满He气。另外,把它放入有He检出器的容器内,容器内部如呈真空状态,则样品内的He气体从样品内向容器内泄漏,此时通过测量He的流量,可测得定量的泄漏程度,这就称为精密泄漏率。
如果对图4~6所示的精密泄漏率的分布作比较,可看到,随着金属盖板5的镍镀层厚度的变厚,精密泄漏率的参数离散也随之加大。在镍镀层厚度为1~2μm的组,作为测量对象的全部取样中,1×10-9Pa·m3/sec以下的高气密性是可实现的。对此,在镍镀层厚度为3~4μm的组,存在着1×10-8Pa·m3/sec的数量级,还有,在镍镀层厚度为5~6μm的组,存在着1×10-7Pa·m3/sec的数量级。由此,从图5及图6看出,如镍镀层的厚度变厚,使以镍镀层作为焊材,将金属盖板5焊到密封圈4的声表面波装置的气密性恶化。
其次,对镍镀层厚度为1~2μm的组的声表面波装置与镍镀层厚度为5~6μm的组的声表面波装置进行湿中放置试验(温度60℃,湿度95%)。这种试验的结果分别在图7及图8中示出。
图7是对于金属盖板5的镍镀层厚度为5~6μm组的声表面波装置,在湿中放置试验中随着时间经过,测量频率变化量的结果。同样,图8是对于金属盖板5的镍镀层厚度为1~2μm组的声表面波装置,在湿中放置试验中随着时间经过,测量频率变化量的结果。
对于金属盖板5的镍镀层厚度为5~6μm的组,如图7所示,经过1000小时后,出现频率急剧下降。这对于镍镀层厚度为5~6μm的声表面波装置,金属盖板5与密封圈4之间的气密性不充分,所以水分侵入声表面波装置内部,成为电极被腐蚀的原因。对此,对于金属盖板5的镍镀层厚度为1~2μm的声表面波装置,即使经过2000小时,频率降低量仍保持在-20p·p·m以下。通过将金属盖板5的镍镀层厚度减薄到1~2μm,使金属盖板5与密封圈4之间的气密性提高。这种点通过测量结果可以得到确认。
这样,从上述测量得知,在由(I)作成平板状的第1陶瓷层与堆迭在第1陶瓷层上并有开口的至少1层的第2陶瓷层构成的芯片载体、(II)位于第2陶瓷层中最上层且堆迭在第2陶瓷层上的可伐铁镍钴合金制的密封圈、(III)上述芯片载体的、实装在以上述开口构成的存放空间内的声表面波元件芯片、及(IV)为封止上述密封圈的开口的可伐铁镍钴合金制的盖板组成的声表面波装置中,通过在上述盖板加上厚度为1~2μm的镍镀层,可使盖板与密封圈之间的气密性保持良好。
此外,金属盖板5的镍镀层好在是用无电解电镀形成的。无电解电镀是由于含在还元剂中的磷(P)的融点低于电解镀层,所以可通过相对较小的焊接电流即可使镀层融化,使焊接条件缓和。这关系到抑制焊接过程中产生的热应力与由它引起的封装裂缝的发生。采用无电解电镀还有一个优点,用无电解电镀得到的镍镀层的厚度的面内参数离散比电解电镀要小,这就意味着焊接时的电流分布,即焊接状态的参数离散也比电解电镀时小。气密性不良引起的不适当就更难以发生了。
对于本发明的电子元件,将元件芯片存放在陶瓷制的芯片载体内,芯片载体上面的密封圈上焊有盖板,以使元件芯片气密封止。可使被镀镍的盖板与密封圈间的焊接性良好,使盖板与密封圈之间的气密性,防水性,防湿性良好,从而能制成高可靠性的声表面波装置,特别是,作为镍镀层是采用无电解镍镀层,能进一步实现高气密性。

Claims (3)

1.一种电子元件,包括
具有凹部的陶瓷制的芯片载体,
收容在所述芯片载体的凹部开口内的芯片,
把所述芯片载体的凹部开口围住并与芯片载体焊接的金属密封圈,和
用来堵塞所述密封圈的开口并气密地封止所述凹部的金属盖板,
其特征在于,
所述盖板的表面施加用于与所述密封圈焊接的厚度为1~2μm的镍镀层。
2.如权利要求1所述的电子元件,其特征在于,
所述盖板通过表面的镍镀层与所述密封圈缝焊。
3.如权利要求1或2所述的电子元件,其特征在于,
用无电解电镀形成施加在所述盖板上的镍镀层。
CNB021319715A 2001-08-30 2002-08-30 电子元件 Expired - Fee Related CN1178294C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001261860 2001-08-30
JP2001261860A JP2003068901A (ja) 2001-08-30 2001-08-30 電子部品

Publications (2)

Publication Number Publication Date
CN1404144A CN1404144A (zh) 2003-03-19
CN1178294C true CN1178294C (zh) 2004-12-01

Family

ID=19088841

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021319715A Expired - Fee Related CN1178294C (zh) 2001-08-30 2002-08-30 电子元件

Country Status (3)

Country Link
US (1) US6720648B2 (zh)
JP (1) JP2003068901A (zh)
CN (1) CN1178294C (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179667A (ja) * 2004-12-22 2006-07-06 Oki Electric Ind Co Ltd 半導体装置用パッケージ
JP5286628B2 (ja) * 2005-02-09 2013-09-11 パナソニック株式会社 電池
US20070120270A1 (en) * 2005-11-23 2007-05-31 Kuroda Roger T Flip chip hermetic seal using pre-formed material
CN100424863C (zh) * 2005-11-25 2008-10-08 全懋精密科技股份有限公司 芯片埋入基板的封装结构
CN101740413B (zh) * 2009-12-15 2013-04-17 天水七四九电子有限公司 Csop陶瓷小外形封装方法
JP6070702B2 (ja) 2012-06-04 2017-02-01 日立金属株式会社 シールリングおよびシールリングの製造方法
EP2750182A1 (en) * 2012-12-28 2014-07-02 Services Pétroliers Schlumberger Electronic device sealing for a downhole tool
US20180005916A1 (en) * 2016-06-30 2018-01-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN114423271A (zh) * 2021-09-30 2022-04-29 中国船舶重工集团公司第七二四研究所 一种气密性电子封装金锡封帽方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2089435C (en) * 1992-02-14 1997-12-09 Kenzi Kobayashi Semiconductor device
US6218730B1 (en) * 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
JP3726998B2 (ja) * 1999-04-01 2005-12-14 株式会社村田製作所 表面波装置
JP2000357937A (ja) * 1999-06-17 2000-12-26 Murata Mfg Co Ltd 弾性表面波装置

Also Published As

Publication number Publication date
US6720648B2 (en) 2004-04-13
US20030062617A1 (en) 2003-04-03
JP2003068901A (ja) 2003-03-07
CN1404144A (zh) 2003-03-19

Similar Documents

Publication Publication Date Title
CN1178294C (zh) 电子元件
CN1214458C (zh) 包括表面弹性波元件的射频模块部件及其制造方法
JP6480806B2 (ja) セラミックと金属を接合するための方法およびその封止構造
US20100123993A1 (en) Atomic layer deposition process for manufacture of battery electrodes, capacitors, resistors, and catalyzers
CN1040385C (zh) 电子器件的同时批量封接和电连接
KR101098956B1 (ko) 연료전지 스택, 연료전지 스택용 밀봉부 및 이 장치들의 제조 방법
IE904277A1 (en) Pressure Sensor and Method Manufacturing same
KR101094597B1 (ko) 전기화학 전지
CN105161640B (zh) 一种盖板组件及包含该盖板组件的电池
CN101068647A (zh) 热膨胀系数相匹配的铜焊体系
CN1281140A (zh) 压力传感器及其制造方法
CN103730264B (zh) 电化学电容器
CN114823552B (zh) 一种适于批量生产的高可靠芯片封装结构及封装方法
CN211788968U (zh) 一种高可靠性陶瓷封接结构
EP1001453A1 (en) Electricity lead-in body for bulb and method for manufacturing the same
JP2004511067A (ja) 接合電気化学電池構成要素
CN112582549B (zh) 一种薄型无溶剂钙钛矿太阳能电池封装方法
EP0660449A2 (en) Electrical feedthrough and its manufacture, and apparatus utilizing the feedthrough
US5146313A (en) Metallized ceramic structure comprising aluminum nitride and tungsten layers
CN107749351B (zh) 全密封超级电容器及其制造方法
KR100934827B1 (ko) 처리 장치용 워크피스 지지체 및 이를 사용하는 처리 장치
CN115985595A (zh) 陶瓷绝缘组件及其制备方法
JP2678511B2 (ja) 半導体素子収納用パッケージ
JP2011096756A (ja) 電子部品収納用パッケージおよび電子装置
CN209729885U (zh) 封装双mos管且原位替换sop8塑封器件的陶瓷外壳

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20041201

Termination date: 20090930