CN117810330A - LED structure, manufacturing method thereof and corresponding LED chip - Google Patents

LED structure, manufacturing method thereof and corresponding LED chip Download PDF

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Publication number
CN117810330A
CN117810330A CN202311851323.7A CN202311851323A CN117810330A CN 117810330 A CN117810330 A CN 117810330A CN 202311851323 A CN202311851323 A CN 202311851323A CN 117810330 A CN117810330 A CN 117810330A
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layer
type
thin film
led structure
manufacturing
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陈子夏
王俊
朱明星
李华
王伟明
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Jiangsu Yixing Derong Technology Co ltd
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Jiangsu Yixing Derong Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025Physical imperfections, e.g. particular concentration or distribution of impurities

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses an LED structure, a manufacturing method thereof and a corresponding LED chip. The LED structure comprises an epitaxial lamination and metal electrode layers positioned on two sides of the epitaxial lamination, wherein the epitaxial lamination comprises an n-type expansion layer, an n-type limiting layer, an active layer, a p-type limiting layer and a p-type conducting layer which are sequentially stacked along a growth direction, the n-type expansion layer is an n-type AlInP layer or an n-type AlGaInP layer, and high-concentration Te doping is realized through a high-temperature diffusion process. According to the invention, an independent n-type conducting layer is not required, and under the condition of realizing the same or higher transverse conducting capability, the epitaxial thickness of the n-type expansion layer can be thinned, the epitaxial time is reduced, the quality of material growth is improved, and the epitaxial cost is reduced.

Description

LED structure, manufacturing method thereof and corresponding LED chip
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LED structure, a manufacturing method thereof and a related LED chip.
Background
Light Emitting Diodes (LEDs) are used as electroluminescent light sources, are energy-saving and environment-friendly, and have a series of excellent performances such as high light efficiency, high brightness, low power consumption, long service life and the like, and are widely applied. From the first development of the red light emitting diode, the luminous efficiency of the red light emitting diode is continuously improved along with the progress of the material growth technology and the development of the device technology.
In the existing red light LED epitaxial structure, a current expansion layer is designed, which is favorable for expanding the light-emitting area and improving the external quantum efficiency of the diode. The current spreading layer is long to a certain thickness to effectively spread the current. If the current spreading layer is not grown or the growing thickness is insufficient, the light emitted by the diode is mainly concentrated below the electrode, and the emitted light is reflected back to cause the failure of effective extraction due to the fact that the electrode is made of non-transparent metal materials, so that the light extraction effect is poor. The current expansion layer with a certain thickness is grown to diffuse current to the whole diode chip, so that the chip can emit light as uniformly as possible, and the light-emitting efficiency is improved. Therefore, in the current red LEDs, in order to achieve an effective lateral expansion of the current, the current expansion layer is relatively thick, but a too thick current expansion layer has several drawbacks: (1) too thick an extension layer spreads the current all the way to the edge of the LED chip, which can lead to increased surface recombination and reduced efficiency; (2) the absorption of light below the band gap of the layer of material increases with increasing thickness; (3) the longer the growth time, the more likely the dopant source diffuses into the active region, reducing internal quantum efficiency. (4) The growth time is long, and the growth quality of the layer and the active region can be affected. In addition, the raw materials Al, in and P of the n-face expansion layer of the current LED are expensive, especially In and P, alInP with the thickness capable of achieving the n expansion effect grows to Si, and the cost is high.
Therefore, it is necessary to provide a method of thinning the current spreading layer without reducing the n-plane spreading effect.
Disclosure of Invention
First, the technical problem to be solved
The invention aims to provide an LED structure and a preparation method thereof, which are used for thinning a current expansion layer of the LED structure and solving the problem of thicker current expansion layer of a flip red LED in the prior art on the premise of not reducing the n-face expansion effect.
(II) technical scheme
In order to achieve the above object, one aspect of the present invention proposes an LED structure comprising an epitaxial stack and metal electrode layers on both sides of the epitaxial stack, the epitaxial stack comprising an n-type extension layer, an n-type confinement layer, an active layer, a p-type confinement layer and a p-type conductive layer stacked in a growth direction; the n-type expansion layer is an n-type AlInP layer or an n-type AlGaInP layer; te is doped in the n-type extension layer.
As a preferred embodiment of the present invention, the n-type extension layer is doped with Te having a high concentration.
As a preferred embodiment of the present invention, the metal electrode layer includes an n-side metal electrode layer directly provided on the surface of the n-type extension layer.
As a preferred embodiment of the present invention, the concentration of Te doped in the n-type extension layer is 1×10 or more 19 /cm 3
As a preferred embodiment of the invention, the doped high-concentration Te adopts an ex-situ high-temperature diffusion mode to carry out Te doping.
As a preferred embodiment of the present invention, the n-type extension layer is doped with Si, the doping concentration of Si is 0.5X10 17 /cm 3 And 5X 10 17 /cm 3 Between them.
As a preferred embodiment of the present invention, the thickness of the n-type extension layer is between 400nm and 2000 nm.
Another aspect of the present invention provides a method for manufacturing an LED structure, including the steps of: manufacturing an epitaxial lamination through an epitaxial growth process, wherein the epitaxial lamination comprises an n-type expansion layer, an n-type limiting layer, an active layer, a p-type limiting layer and a p-type conducting layer which are sequentially stacked along a growth direction, and the n-type expansion layer is an n-type AlInP layer or an n-type AlGaInP layer; forming a Te-containing thin film layer on the n-type extension layer, and performing ex-situ growth on the Te-containing thin film layer to enable Te in the Te-containing thin film layer to enter the n-type extension layer; and forming metal electrode layers on two sides of the epitaxial lamination.
In a preferred embodiment of the present invention, an n-side metal electrode layer is directly formed on the surface of the n-type extension layer.
As a preferred embodiment of the present invention, the step of diffusing Te in the Te-containing thin film layer into the n-type extension layer is performed by a high temperature diffusion method
As a preferred embodiment of the present invention, after the annealing step is performed on the Te thin film layer, the remaining Te-containing component on the n-type extension layer is removed.
As a preferred embodiment of the present invention, the residual Te-containing component is washed with potassium hydroxide or nitric acid.
As a preferred embodiment of the present invention, the Te-containing thin film layer is a Te thin film layer or a CdTe thin film layer.
As a preferred embodiment of the present invention, in the step of forming the Te-containing thin film layer on the n-type extension layer: when the Te-containing thin film layer is a Te thin film layer, the thickness of the Te thin film layer is at least 0.03% of the thickness of the n-type extension layer; when the Te-containing thin film layer is a CdTe thin film layer, the thickness of the CdTe thin film layer is at least 0.07% of the thickness of the n-type extension layer.
As a preferred embodiment of the present invention, the high temperature diffusion is performed at 300 to 500 ℃ for 1 to 10 minutes.
In a preferred embodiment of the present invention, the metal electrode layer material formed on the n-type extension layer side is Au.
A third aspect of the present invention proposes an LED chip comprising the LED structure proposed above.
A fourth aspect of the present invention provides an LED chip comprising an LE structure made by the method of manufacturing an LED structure described above.
(III) beneficial effects
According to the invention, under the condition of realizing the same transverse conductivity, the epitaxial thickness of the n-type expansion layer can be thinned, the epitaxial time is reduced, the quality of material growth is improved, and the epitaxial cost is reduced.
Drawings
Fig. 1 is a schematic structural view of an epitaxial stack generated in the method of manufacturing an LED structure of the comparative example.
Fig. 2 is a schematic diagram of a structure in which a p-side gold electrode layer is formed on an epitaxial stack in a method of manufacturing an LED structure of a comparative example.
Fig. 3 is a schematic view of a structure in which a metal electrode layer is formed on the n-type extension layer side in the manufacturing method of the LED structure of the comparative example.
Fig. 4 is a schematic structural view of an epitaxial stack layer generated in the method for manufacturing an LED structure of embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of a structure in which a p-side gold electrode layer is formed on an epitaxial stack in the method for manufacturing an LED structure according to embodiment 1 of the present invention.
Fig. 6 is a schematic view of a structure in which Te is doped in an n-type extension layer in the method of manufacturing an LED structure of embodiment 1 of the present invention.
Fig. 7 is a schematic view of a structure in which a metal electrode layer is formed on the n-type extension layer side in the method for manufacturing an LED structure of embodiment 1 of the present invention.
Detailed Description
As previously mentioned, in a red LED, the current spreading layer is relatively thick in order to achieve an efficient lateral spreading of the current. The invention aims to provide an LED structure and a preparation method thereof, wherein a current expansion layer is thinned, and the problems in the prior art are solved on the premise of not reducing the n-face expansion effect.
On the premise of not reducing the n-face expansion effect, the problem of conductivity of the n-face needs to be considered when the n-face current expansion layer is thinned. According to the resistance formula r=ρl/S (R: resistance; ρ: resistivity; L: current diffusion length; S cross-sectional area through which current passes). There are two methods of reducing resistance, regardless of the L variation: (1) reducing the resistivity ρ; (2) the cross-sectional area S through which the current passes is increased.
In the method (2), increasing the cross-sectional area S through which the current passes requires increasing the thickness of the n-plane current spreading layer, which is not suitable for the purpose of thinning. In method (1), according to the formula ρ=1/nqμ n (n: carrier concentration, q: unit charge, μ) n : mobility), typically with less mobility change, the resistivity can be reduced by increasing the doping concentration.
The n-face extension layer material of the LED structure is generally Si doped Al (Ga) InP (expressed as AlInP: si or AlGaInP: si), and the doping concentration of Si in the Al (Ga) InP is low, so that the purpose of reducing the resistance by high doping can be achieved by changing the doping source. Te can reach higher doping concentration in Al (Ga) InP and meets the requirements. Doping of Te in Al (Ga) InP can also have two methods:
the first is in-situ doping, which directly dopes growth Te when epitaxially growing Al (Ga) InP. However, the method has two limiting factors or disadvantages, firstly, the difficulty of epitaxially growing high-quality high-Te doped AlInP material by using the MOCVD method is high, and the growth quality of the material is difficult to guarantee, so that the growth quality of a subsequent active region is possibly influenced; and secondly, the diffusion coefficient of Te in III-V semiconductor materials such as Al (Ga) InP is very high, and Te atoms are likely to diffuse into an active region under the high-temperature growth condition of high doping concentration or under the condition that a subsequent chip works at high temperature for a long time, so that the internal quantum efficiency is reduced, and the performance of the chip is affected.
The second is non-in-situ doping, in the chip process, a layer of Te is evaporated on the Al (Ga) InP doped with low Si, and through RTP annealing, te is thermally diffused into the Al (Ga) InP: si, so that the purposes of increasing doping concentration, reducing the resistance of the n-face expansion layer and thinning the n-face expansion layer are achieved.
According to literature reports, high Si doping can affect the growth quality of Al (Ga) InP materials, and the subsequent Te diffusion has the advantage that when an Si doped Al (Ga) InP material layer is epitaxially grown by MOCVD, the doping concentration of Si can be reduced, the growth quality of the layer can be improved, and the material quality of a subsequent active region can be improved or ensured. Meanwhile, the method can also control the diffusion depth of Te so that Te does not diffuse into an active region and the internal quantum efficiency is not affected.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
the LED structure comprises an epitaxial lamination and metal electrode layers positioned on two sides of the epitaxial lamination, wherein the epitaxial lamination at least comprises an n-type expansion layer, an n-type limiting layer, an active layer, a p-type limiting layer and a p-type conducting layer which are sequentially stacked along the growth direction, the n-type expansion layer is an n-type AlInP layer or an n-type AlGaInP layer, and Te is doped in the n-type expansion layer.
Te doped in the n-type expansion layer is diffused into the n-type expansion layer by the high temperature diffusion process of the invention, and the concentration of Te in the n-type expansion layer can be more than or equal to 1 multiplied by 10 by controlling the thickness, the process time and the temperature of the Te film layer 19 /cm 3 . Meanwhile, in order to improve the growth quality of the n-type AlInP layer or the n-type AlGaInP layer, the invention can reduce the doping concentration of Si in the n-type AlInP layer or the n-type AlGaInP layer, for example, the invention can make it at 0.5X10 17 /cm 3 And 5X 10 17 /cm 3 And is much lower than the doping concentration of Te.
The high temperature diffusion process includes an annealing process.
After the scheme is adopted, the high doping concentration of the n-type diffusion layer is realized, and the resistance is further reduced. Therefore, the thickness of the n-type diffusion layer can be reduced while the same lateral conductivity is achieved, the growth quality of the n-type layer is improved, and the epitaxial time and cost are reduced. Alternatively, the n-type extension layer may be thinned to 1/4 to 1/6 of that of the n-type extension layer when it is undoped with Te, for example, 1/5 of that of the original one.
The present invention is not strictly limited to the constitution of the epitaxial stack, but in general, the epitaxial stack structure of the LED includes an n-type extension layer, an n-type confinement layer, an active layer, a p-type confinement layer, and a p-type conductive layer stacked in this order along the growth direction. It should be noted that other layers, such as ohmic contact layers, may also be present in the epitaxial stack, which are considered to be within the scope of the present invention. Also, temporary structures such as temporary substrates and temporary functional layers including buffer layers, etch layers, etc. may also occur during the formation process of the epitaxial layer stack.
However, since GaAs has a relatively small band gap, it can absorb part of the light emitted from the active layer, and thus the external quantum efficiency of the LED is reduced, and in view of this, it is preferable that an n-type GaAs ohmic contact layer is not provided in the present invention.
As a specific embodiment, the temporary substrate may be a GaAs substrate. For example, one embodiment is to grow an epitaxial stack on a GaAs substrate, the epitaxial stack including an n-type buffer layer, an n-type etch layer, an n-type extension layer, an n-type confinement layer, an active layer, a p-type confinement layer, a p-type conductive layer, which are stacked in this order along the growth direction.
In the manufacturing process of the invention, a Te thin film layer or a CdTe thin film layer is evaporated on the n-type extension layer in order to dope Te in the n-type extension layer.
The thickness of the Te film layer or the CdTe film layer is determined according to the thickness of the n-type expansion layer, and simulation and practical measurement according to the invention show that the thickness of the Te film layer is preferably greater than or equal to 0.03% of the thickness of the n-type expansion layer, and the thickness of the CdTe film layer is preferably greater than or equal to 0.07% of the thickness of the n-type expansion layer; further, cleaning the residual Te film layer or CdTe film layer, and selecting nitric acid or potassium hydroxide.
Te enters the n-type expansion layer through a high-temperature diffusion process, the RTP annealing temperature is 300-500 ℃, the high doping of the n-type expansion layer is realized, and the process time is 1-10 min. An alternative process is the RTP annealing process.
According to the invention, the doping concentration of the n-type extension layer after the high-temperature diffusion process step can be increased to 1×10 19 /cm 3 The above. At the same time, the doping concentration of Si is 10 compared with the conventional Si 18 /cm 3 Compared with an order-of-magnitude extension layer, the invention can reduce the Si doping concentration to 10 17 /cm 3 On the order of magnitude. As a specific embodiment, an n-metal semiconductor contact structure, such as an n-type AlInP: si layer/n-metal structure, is preferably used in the metal electrode layer of the present invention. Wherein n metal is preferably Au.
Therefore, the Te/CdTe thin film layer is formed and annealed in the working procedure of the manufacturing process, so that the high doping concentration of the n-type extension layer is realized, and the resistance is further reduced. The thickness of the n-type expansion layer can be thinned while the same transverse conductivity is realized, the growth quality of the n-type expansion layer is improved, and the epitaxial time and cost are reduced.
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
In order to embody the features and advantages of the present invention over the prior art, a comparative example is first described herein for comparison, which employs a conventional LED structure, i.e., an n-type extension layer that is free of Te.
Fig. 1 is a schematic structural view of an epitaxial stack generated in the method of manufacturing an LED structure of the comparative example. As shown in FIG. 1, this comparative example employs a metal organic vapor phase epitaxy method to grow an n-type GaAs: si buffer layer 2 (200 nm), an n-type GaInP: si etch layer 3 (150 nm), an n-type AlInP: si extension layer 4 (3 μm), an n-type AlInP: si confinement layer 5 (500 nm), an active layer 6 (Al is grown in sequence) on a GaAs substrate 1 in this order 0.6 GaInP barrier layer, gaInP and Al 0.55 GaInP、Al 0.6 GaInP barrier), p-type AlInP: mg confinement layer 7 (500 nm and p-type GaP: mg conductive layer 8 (3 μm).
Wherein the n-type AlInP: si extension layer 4 has a thickness of 3 μm and a Si doping concentration of 2X 10 18 /cm 3
Fig. 2 is a schematic diagram of a structure in which a p-side gold electrode layer is formed on an epitaxial stack in a method of manufacturing an LED structure of a comparative example. The direction of fig. 2 is the direction after the upside down in fig. 1, and after the epitaxial stack is formed, a p-side metal electrode layer 9 is grown on the p-type conductive layer 8 side as shown in fig. 2. The GaAs substrate 1, the GaAs: si buffer layer 2, and the n-type GaInP: si etching layer 3 are etched down to expose the n-type AlInP: si extension layer 4.
Fig. 3 is a schematic view of a structure in which a metal electrode layer is formed on the n-type extension layer side in the manufacturing method of the LED structure of the comparative example. As shown in fig. 3, this comparative example performs a vapor deposition process of an n-side metal electrode layer 10 on an n-type AlInP: si extension layer 4, where Au is used.
Inventive example 1:
fig. 4 is a schematic structural view of an epitaxial stack layer generated in the method for manufacturing an LED structure of embodiment 1 of the present invention. As shown in FIG. 4, this comparative example, example 1 of the present invention has a similar structure to the comparative example described above, which is also a method of growing an n-type GaAs: si buffer layer 2, an n-type GaInP: si etch layer 3, an n-type AlInP: si extension layer 4, an n-type AlInP: si confinement layer 5, an active layer 6 (Al is grown in order) on a GaAs substrate 1 in this order from bottom to top by a metal organic vapor phase epitaxy method 0.6 GaInP barrier layer, gaInP and Al 0.55 GaInP、Al 0.6 GaInP barrier), p-type AlInP Mg confinement layer 7 and p-type GaP Mg conductive layer 8.
However, unlike the comparative example, the thickness of the n-type AlInP: si extension layer in practical example 1 of the present invention can be reduced to 400nm to 2000nm, for example 600nm. At the same time, the doping concentration of Si can be reduced to 0.5X 10 17 /cm 3 ~5ⅹ10 17 /cm 3 For example 1 x 10 17 /cm 3 1ⅹ10 17 /cm 3
Fig. 5 is a schematic diagram of a structure in which a p-side gold electrode layer is formed on an epitaxial stack in the method for manufacturing an LED structure according to embodiment 1 of the present invention. Next, as shown in fig. 5, similarly to the comparative example, after the epitaxial stack is formed, a p-side metal electrode layer 9 is grown on the p-type conductive layer 8 side. The GaAs substrate 1, the GaAs: si buffer layer 2, and the n-type GaInP: si etching layer 3 are etched down to expose the n-type AlInP: si extension layer 4.
Fig. 6 is a schematic structural view of doping Te in the n-type extension layer and forming a metal electrode layer on the side in the manufacturing method of the LED structure of embodiment 1 of the present invention. As shown in fig. 6, a Te thin film 41 is vapor-deposited on the n-type AlInP: si extension layer 4 to a thickness of 1nm, and then RTP annealing is performed at 400 ℃ for 1min, so that Te enters the n-type AlInP: si extension layer 4 (arrow direction in the drawing), high doping of the n-type AlInP: si extension layer 4 is achieved, and then the remaining Te thin film layer 41 is washed with potassium hydroxide.
Fig. 7 is a schematic view of a structure in which a metal electrode layer is formed on the n-type extension layer side in the method for manufacturing an LED structure of embodiment 1 of the present invention. Similarly to the comparative example, the evaporation process of the n-side metal electrode layer 10 was performed on the n-type AlInP: si extension layer 4, and Au was used here.
Example 2:
example 2 is similar to example 1 except that the Te thin film layer employed in example 1 is replaced with a CdTe thin film layer. Since the Te content in the CdTe film layer is less than that of the Te film layer, a thicker CdTe film layer is required to achieve the same Te doping concentration.
In example 2, too, a metal organic gas is first usedThe phase epitaxy method sequentially grows an n-type GaAs: si buffer layer 2, an n-type GaInP: si etch layer 3, an n-type AlInP: si extension layer 4, an n-type AlInP: si confinement layer 5, and an active layer 6 (sequentially grows Al) on a GaAs substrate 1 from bottom to top 0.6 GaInP barrier layer, gaInP and Al 0.55 GaInP、Al 0.6 GaInP barrier), p-type AlInP Mg confinement layer 7, p-type GaP Mg conductive layer 8. Then, the p-side metal electrode layer 9 is grown, and the substrate 1, gaAs: si buffer layer 2, and n-type GaInP: si etch layer 3 are etched. Then, a CdTe film 41 is evaporated on the n-type AlInP: si extension layer 4 to a thickness of 2nm, and then RTP annealing is performed at 400 ℃ for 1min, so that Te enters the n-type AlInP: si extension layer 4, thereby realizing Te high doping of the n-type AlInP: si extension layer 4. The residual CdTe film is then cleaned with nitric acid, after which a vapor deposition process of the n-side metal electrode layer 9, here Au, is carried out.
In this example 2 as well, the n-type AlInP: si extension layer 4 may have a thickness of 400nm to 2000nm, for example 600nm, while the doping concentration of Si is reduced to 0.5X 10 17 /cm 3 ~5ⅹ10 17 /cm 3 For example 1 x 10 17 /cm 3
In the above-described embodiment 1 and embodiment 2, the n-type AlInP: si extension layer may be replaced by an n-type AlGaInP: si extension layer.
The LED structure proposed in the present invention and the LED structure manufactured by the above manufacturing method may be manufactured to form an LED chip by a flip-chip packaging process or the like.
In summary, in the above-described embodiments 1 and 2, since Te is doped in the n-type extension layer by the annealing process, the conductivity of the n-type extension layer is enhanced. Therefore, compared with the prior art, the thickness of the n-type extension layer can be thinned and the epitaxial time can be reduced under the condition of realizing the same lateral conductivity. Meanwhile, the doping concentration of Si in the n-type expansion layer can be reduced, so that the invention is also beneficial to improving the growth quality of the expansion layer material and reducing the epitaxial cost.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.

Claims (13)

1. An LED structure, includes epitaxial lamination and the metal electrode layer that is located epitaxial lamination both sides, its characterized in that:
the epitaxial lamination comprises an n-type expansion layer, an n-type limiting layer, an active layer, a p-type limiting layer and a p-type conductive layer which are stacked along the growth direction;
the n-type expansion layer is an n-type AlInP layer or an n-type AlGaInP layer;
the n-type expansion layer is doped with high-concentration Te;
the metal electrode layer comprises an n-face metal electrode layer which is directly arranged on the surface of the n-type expansion layer.
2. The LED structure of claim 1, wherein a maximum Te doping concentration in the n-type extension layer is greater than or equal to 1 x 10 19 /cm 3
3. The LED structure of claim 1, wherein the doped high concentration Te is Te doped by ex-situ high temperature diffusion.
4. The LED structure of claim 3 wherein the n-type extension layer is doped with Si at a doping concentration of 0.5 x 10 17 /cm 3 And 5X 10 17 /cm 3 Between them.
5. The LED structure of claim 4, wherein the n-type extension layer has a thickness between 400nm and 2000 nm.
6. A method of manufacturing an LED structure, comprising the steps of:
manufacturing an epitaxial lamination through an epitaxial growth process, wherein the epitaxial lamination comprises an n-type expansion layer, an n-type limiting layer, an active layer, a p-type limiting layer and a p-type conducting layer which are sequentially stacked along a growth direction, and the n-type expansion layer is an n-type AlInP layer or an n-type AlGaInP layer;
forming a Te-containing thin film layer on the n-type extension layer, and performing ex-situ growth on the Te-containing thin film layer to diffuse Te in the Te-containing thin film layer into the n-type extension layer;
and directly forming an n-face metal electrode layer on the surface of the n-type expansion layer.
7. The method of manufacturing an LED structure according to claim 6, wherein the step of diffusing Te in the Te-containing thin film layer into the n-type extension layer is performed by high temperature diffusion.
8. The method of manufacturing an LED structure according to claim 6, wherein after diffusing Te in the Te-containing thin film layer into the n-type extension layer, residual Te-containing components on the n-type extension layer are removed.
9. The method of manufacturing an LED structure of claim 6, wherein said Te-containing thin film layer is a Te thin film layer or a CdTe thin film layer.
10. The method of manufacturing an LED structure of claim 9, wherein in the step of forming a Te-containing thin film layer on the n-type extension layer: when the Te-containing thin film layer is a Te thin film layer, the thickness of the Te thin film layer is at least 0.03% of the thickness of the n-type extension layer; when the Te-containing thin film layer is a CdTe thin film layer, the thickness of the CdTe thin film layer is at least 0.07% of the thickness of the n-type extension layer.
11. The method of manufacturing an LED structure according to claim 7, wherein the high-temperature diffusion is performed at a temperature of 300 ℃ to 500 ℃ for a time of 1min to 10min.
12. An LED chip comprising the LED structure of any one of claims 1 to 5.
13. An LED chip comprising an LED structure made by the method of manufacturing an LED structure according to any one of claims 6 to 11.
CN202311851323.7A 2023-12-29 2023-12-29 LED structure, manufacturing method thereof and corresponding LED chip Pending CN117810330A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643783A (en) * 1979-09-18 1981-04-22 Toshiba Corp Light emitting diode for optical communication
CN1099521A (en) * 1993-07-22 1995-03-01 东芝株式会社 Semiconductor luminous equipment
CN102664226A (en) * 2012-05-18 2012-09-12 厦门乾照光电股份有限公司 Light-emitting diode with modulation-doped current expansion layer
CN104332537A (en) * 2014-10-17 2015-02-04 厦门乾照光电股份有限公司 High concentration Te doped light emitting diode epitaxial structure
CN104813487A (en) * 2012-11-12 2015-07-29 欧司朗光电半导体有限公司 Optoelectronic semiconductor chip and a method for producing optoelectronic semiconductor chips
CN112088431A (en) * 2018-05-01 2020-12-15 脸谱科技有限责任公司 Micron-sized light emitting diode design
CN117219697A (en) * 2023-09-27 2023-12-12 中国石油大学(华东) Te in-situ high-concentration doped SnSe/Si heterojunction-based self-driven photoelectric detector and preparation method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643783A (en) * 1979-09-18 1981-04-22 Toshiba Corp Light emitting diode for optical communication
CN1099521A (en) * 1993-07-22 1995-03-01 东芝株式会社 Semiconductor luminous equipment
CN102664226A (en) * 2012-05-18 2012-09-12 厦门乾照光电股份有限公司 Light-emitting diode with modulation-doped current expansion layer
CN104813487A (en) * 2012-11-12 2015-07-29 欧司朗光电半导体有限公司 Optoelectronic semiconductor chip and a method for producing optoelectronic semiconductor chips
CN104332537A (en) * 2014-10-17 2015-02-04 厦门乾照光电股份有限公司 High concentration Te doped light emitting diode epitaxial structure
CN112088431A (en) * 2018-05-01 2020-12-15 脸谱科技有限责任公司 Micron-sized light emitting diode design
CN117219697A (en) * 2023-09-27 2023-12-12 中国石油大学(华东) Te in-situ high-concentration doped SnSe/Si heterojunction-based self-driven photoelectric detector and preparation method thereof

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