CN117810330A - LED structure, manufacturing method thereof and corresponding LED chip - Google Patents
LED structure, manufacturing method thereof and corresponding LED chip Download PDFInfo
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Abstract
Description
技术领域Technical Field
本发明涉及半导体技术领域,具体涉及一种LED结构及其制造制方法,以及相关的LED芯片。The present invention relates to the field of semiconductor technology, and specifically relates to an LED structure and a manufacturing method thereof, as well as related LED chips.
背景技术Background technique
发光二极管(LED)作为电致发光光源,节能环保,具有高光效、高亮度、低功耗、长寿命等一系列优良性能,应用广泛。从红光发光二极管初次问世发展至今,随着材料生长技术的进步和器件工艺技术的发展,红光LED的发光效率不断提高。As an electroluminescent light source, light-emitting diodes (LEDs) are energy-saving and environmentally friendly. They have a series of excellent properties such as high light efficiency, high brightness, low power consumption, and long life, and are widely used. From the first appearance of red light-emitting diodes to the present, with the advancement of material growth technology and the development of device technology, the luminous efficiency of red LEDs has continued to improve.
在现有的红光LED外延结构中,设计了电流扩展层,有利于扩展发光面积,提升二极管的外量子效率。电流扩展层要长到一定厚度,才可以有效扩展电流。如若不生长电流扩展层或生长厚度不够,二极管发射的光主要聚集在电极下方,由于电极均为非透明的金属材料,因此发出的光会被反射回来而导致无法进行有效提取,从而导致光提取效果不佳。生长一定厚度的电流扩展层可以将电流扩散到整个二极管芯片,让芯片可以尽可能地均匀发光,提升出光效率。所以,目前的红光LED中,为了达到电流的有效横向扩展,电流扩展层都比较厚,但是,太厚的电流扩展层有几个缺点:①太厚的扩展层将电流一直扩散到LED芯片的边缘,这会导致表面复合增加,降低效率;②对该层材料带隙以下光的吸收随厚度的增加而增加;③生长时间较长,可能导致掺杂源扩散到有源区,降低内量子效率。④生长时间较长,可能影响本层和有源区的生长质量。此外,目前LED n面扩展层原材料Al、In、P均比较昂贵,尤其是In、P,生长能够达到n扩展效果厚度的AlInP:Si,成本很大。In the existing red LED epitaxial structure, a current expansion layer is designed to expand the light-emitting area and improve the external quantum efficiency of the diode. The current expansion layer must grow to a certain thickness to effectively expand the current. If the current expansion layer is not grown or the thickness is not enough, the light emitted by the diode is mainly concentrated under the electrode. Since the electrodes are all non-transparent metal materials, the emitted light will be reflected back and cannot be effectively extracted, resulting in poor light extraction. Growing a current expansion layer of a certain thickness can spread the current to the entire diode chip, allowing the chip to emit light as evenly as possible and improve the light extraction efficiency. Therefore, in the current red LED, in order to achieve effective lateral expansion of the current, the current expansion layer is relatively thick. However, a current expansion layer that is too thick has several disadvantages: ① A too thick expansion layer will spread the current to the edge of the LED chip, which will increase surface recombination and reduce efficiency; ② The absorption of light below the band gap of this layer of material increases with the increase of thickness; ③ The growth time is long, which may cause the doping source to diffuse into the active area and reduce the internal quantum efficiency. ④ The growth time is long, which may affect the growth quality of this layer and the active area. In addition, the raw materials of the LED n-side expansion layer, Al, In, and P, are relatively expensive, especially In and P. Growing AlInP:Si with a thickness that can achieve the n-expansion effect is very costly.
因此,在不降低n面扩展效果的前提下,有必要提供一种减薄电流扩展层的方法。Therefore, it is necessary to provide a method for thinning the current spreading layer without reducing the n-plane spreading effect.
发明内容Contents of the invention
(一)要解决的技术问题1. Technical issues to be resolved
本发明的目的在于提供一种LED结构以及制备方法,将其电流扩展层减薄,在不降低n面扩展效果的前提下,解决现有技术中倒装红光LED的电流扩展层较厚问题。The object of the present invention is to provide an LED structure and a preparation method that thin the current expansion layer and solve the problem of the thick current expansion layer of flip-chip red LEDs in the prior art without reducing the n-plane expansion effect. .
(二)技术方案(2) Technical solutions
为了达到上述目的,本发明的一个方面提出一种LED结构,包括外延叠层和位于外延叠层两侧的金属电极层,所述外延叠层包括沿生长方向堆叠的n型扩展层、n型限制层、有源层、p型限制层和p型导电层;所述n型扩展层是n型AlInP层或n型AlGaInP层;所述n型扩展层中掺杂有Te。In order to achieve the above object, one aspect of the present invention proposes an LED structure, including an epitaxial stack and metal electrode layers located on both sides of the epitaxial stack. The epitaxial stack includes n-type extension layers stacked along the growth direction, n-type A confinement layer, an active layer, a p-type confinement layer and a p-type conductive layer; the n-type extension layer is an n-type AlInP layer or an n-type AlGaInP layer; the n-type extension layer is doped with Te.
作为本发明的优选实施方式,所述n型扩展层中掺杂高浓度Te。As a preferred embodiment of the present invention, the n-type extension layer is doped with a high concentration of Te.
作为本发明的优选实施方式,所述金属电极层包括直接设置在所述n型扩展层表面的n面金属电极层。As a preferred embodiment of the present invention, the metal electrode layer includes an n-face metal electrode layer directly disposed on the surface of the n-type extension layer.
作为本发明的优选实施方式,所述n型扩展层中掺杂的Te的浓度大于或等于1×1019/cm3。As a preferred embodiment of the present invention, the concentration of Te doped in the n-type extension layer is greater than or equal to 1×10 19 /cm 3 .
作为本发明的优选实施方式,所述掺杂高浓度Te采用非原位高温扩散方式进行Te掺杂。As a preferred embodiment of the present invention, the high-concentration Te doping is performed using an ex-situ high-temperature diffusion method for Te doping.
作为本发明的优选实施方式,所述n型扩展层中掺杂有Si,Si的掺杂浓度位于0.5×1017/cm3和5×1017/cm3之间。As a preferred embodiment of the present invention, the n-type extension layer is doped with Si, and the doping concentration of Si is between 0.5×10 17 /cm 3 and 5×10 17 /cm 3 .
作为本发明的优选实施方式,所述n型扩展层的厚度在400nm和2000nm之间。As a preferred embodiment of the present invention, the thickness of the n-type extension layer is between 400nm and 2000nm.
本发明的另一个方面提出一种LED结构的制造方法,包括如下步骤:通过外延生长工艺制作外延叠层,所述外延叠层包括沿生长方向依次堆叠的n型扩展层、n型限制层、有源层、p型限制层和p型导电层,其中,所述n型扩展层是n型AlInP层或n型AlGaInP层;在所述n型扩展层上形成含Te薄膜层,并对所述含Te薄膜层进行非原位生长,以使所述含Te薄膜层中的Te进入所述n型扩展层;在所述外延叠层的两侧形成金属电极层。Another aspect of the present invention provides a method for manufacturing an LED structure, which includes the following steps: producing an epitaxial stack through an epitaxial growth process. The epitaxial stack includes an n-type extension layer, an n-type confinement layer, and an n-type extension layer sequentially stacked along the growth direction. An active layer, a p-type confinement layer and a p-type conductive layer, wherein the n-type extension layer is an n-type AlInP layer or an n-type AlGaInP layer; a Te-containing thin film layer is formed on the n-type extension layer, and the The Te-containing thin film layer is grown ex-situ so that Te in the Te-containing thin film layer enters the n-type extension layer; metal electrode layers are formed on both sides of the epitaxial stack.
作为本发明的优选实施方式,在所述n型扩展层表面直接形成n面金属电极层。As a preferred embodiment of the present invention, an n-side metal electrode layer is directly formed on the surface of the n-type extension layer.
作为本发明的优选实施方式,所述含Te薄膜层中的Te扩散进入所述n型扩展层的步骤采用高温扩散方式进行As a preferred embodiment of the present invention, the step of diffusing Te in the Te-containing thin film layer into the n-type extension layer is performed by high temperature diffusion.
作为本发明的优选实施方式,在对所述Te薄膜层进行退火步骤之后,清除所述n型扩展层上残余的含Te成分。As a preferred embodiment of the present invention, after performing an annealing step on the Te thin film layer, residual Te-containing components on the n-type extension layer are removed.
作为本发明的优选实施方式,使用氢氧化钾或硝酸清洗所述残余的含Te成分。As a preferred embodiment of the present invention, potassium hydroxide or nitric acid is used to clean the remaining Te-containing components.
作为本发明的优选实施方式,所述含Te薄膜层为Te薄膜层或CdTe薄膜层。As a preferred embodiment of the present invention, the Te-containing thin film layer is a Te thin film layer or a CdTe thin film layer.
作为本发明的优选实施方式,在所述n型扩展层上形成含Te薄膜层的步骤中:当含Te薄膜层为Te薄膜层时,该Te薄膜层的厚度至少为所述n型扩展层厚度的0.03%;当含Te薄膜层为CdTe薄膜层时,该CdTe薄膜层的厚度至少为所述n型扩展层厚度的0.07%。As a preferred embodiment of the present invention, in the step of forming a Te-containing thin film layer on the n-type extension layer: when the Te-containing thin film layer is a Te thin film layer, the thickness of the Te thin film layer is at least the thickness of the n-type extension layer. 0.03% of the thickness; when the Te-containing thin film layer is a CdTe thin film layer, the thickness of the CdTe thin film layer is at least 0.07% of the thickness of the n-type extension layer.
作为本发明的优选实施方式,所述高温扩散的温度为300℃到500℃,时间为1min~10min。As a preferred embodiment of the present invention, the temperature of the high-temperature diffusion is 300°C to 500°C, and the time is 1 min to 10 min.
作为本发明的优选实施方式,在所述n型扩展层侧形成的金属电极层材料为Au。As a preferred embodiment of the present invention, the material of the metal electrode layer formed on the n-type extension layer side is Au.
本发明的第三方面提出一种LED芯片,包括上述提出的LED结构。A third aspect of the present invention provides an LED chip, including the LED structure proposed above.
本发明的第四方面提出一种LED芯片,包括由上述的LED结构的制造方法所制得的LE结构。A fourth aspect of the present invention provides an LED chip, including an LE structure produced by the above-mentioned manufacturing method of an LED structure.
(三)有益效果(3) Beneficial effects
本发明在实现同样的横向导电能力的情况下,能够减薄n型扩展层的外延厚度,降低外延时间,提高材料生长的质量,减少外延成本。Under the condition of achieving the same lateral conductivity, the present invention can reduce the epitaxial thickness of the n-type extension layer, shorten the epitaxial time, improve the quality of material growth, and reduce the epitaxial cost.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是对比实施例的LED结构的制造方法中生成的外延叠层的结构示意图。FIG. 1 is a schematic structural diagram of an epitaxial stack produced in a method for manufacturing an LED structure according to a comparative embodiment.
图2是对比实施例的LED结构的制造方法中在外延叠层上形成p面金层电极层的结构示意图。FIG. 2 is a schematic structural diagram of forming a p-plane gold electrode layer on an epitaxial stack in the manufacturing method of the LED structure of the comparative embodiment.
图3是对比实施例的LED结构的制造方法中在n型扩展层侧形成金属电极层的结构示意图。3 is a schematic structural diagram of forming a metal electrode layer on the n-type extension layer side in the manufacturing method of the LED structure of the comparative embodiment.
图4是本发明实施例1的LED结构的制造方法中生成的外延叠层的结构示意图。FIG. 4 is a schematic structural diagram of an epitaxial stack produced in the method for manufacturing an LED structure in Embodiment 1 of the present invention.
图5是本发明实施例1的LED结构的制造方法中在外延叠层上形成p面金层电极层的结构示意图。FIG. 5 is a schematic structural diagram of forming a p-plane gold electrode layer on an epitaxial stack in the method for manufacturing an LED structure in Embodiment 1 of the present invention.
图6是本发明实施例1的LED结构的制造方法中在n型扩展层中掺杂Te的结构示意图。6 is a schematic structural diagram of Te doping in the n-type extension layer in the manufacturing method of the LED structure in Embodiment 1 of the present invention.
图7是本发明实施例1的LED结构的制造方法中在n型扩展层侧形成金属电极层的结构示意图。7 is a schematic structural diagram of forming a metal electrode layer on the n-type extension layer side in the manufacturing method of the LED structure according to Embodiment 1 of the present invention.
具体实施方式Detailed ways
如前所述,在红光LED中,为了达到电流的有效横向扩展,电流扩展层都比较厚。本发明的目的在于提供一种LED结构以及制备方法,将其电流扩展层减薄,在不降低n面扩展效果的前提下,解决现有技术中上述问题。As mentioned before, in red LEDs, in order to achieve effective lateral expansion of current, the current expansion layer is relatively thick. The purpose of the present invention is to provide an LED structure and a preparation method that can thin the current expansion layer and solve the above-mentioned problems in the prior art without reducing the n-plane expansion effect.
在不降低n面扩展效果的前提下,减薄n面电流扩展层则需要考虑该面的电导问题。根据电阻公式R=ρL/S(R:电阻;ρ:电阻率;L:电流扩散长度;S电流通过的横截面积)。不考虑L变化,有两种减小电阻的方法:①减小电阻率ρ;②增大电流通过的横截面积S。Without reducing the n-side expansion effect, thinning the n-side current spreading layer requires considering the conductivity of this side. According to the resistance formula R=ρL/S (R: resistance; ρ: resistivity; L: current diffusion length; S cross-sectional area through which current passes). Regardless of the change in L, there are two ways to reduce resistance: ① Reduce the resistivity ρ; ② Increase the cross-sectional area S through which the current passes.
在方法②中,增大电流通过的横截面积S需要增加n面电流扩展层的厚度,不符合减薄目的。在方法①中,根据公式ρ=1/nqμn(n:载流子浓度,q:单位电荷,μn:迁移率),一般情况下迁移率改变较小,可以通过增加掺杂浓度来减小电阻率。In method ②, increasing the cross-sectional area S through which the current passes requires increasing the thickness of the n-side current expansion layer, which does not meet the purpose of thinning. In method ①, according to the formula ρ = 1/nqμ n (n: carrier concentration, q: unit charge, μ n : mobility), the change in mobility is generally small and can be reduced by increasing the doping concentration. Small resistivity.
LED结构的n面扩展层材料一般是Si掺杂的Al(Ga)InP(表示为AlInP:Si或AlGaInP:Si),Si在Al(Ga)InP中的掺杂浓度较低,故可以更换掺杂源来达到高掺杂减小电阻的目的。Te在Al(Ga)InP中可以达到较高的掺杂浓度,符合要求。Te在Al(Ga)InP中的掺杂可以也有两种方法:The n-side extension layer material of the LED structure is generally Si-doped Al(Ga)InP (expressed as AlInP:Si or AlGaInP:Si). The doping concentration of Si in Al(Ga)InP is low, so the doping can be replaced. Impurity sources are used to achieve the purpose of high doping and reduced resistance. Te can reach a higher doping concentration in Al(Ga)InP, which meets the requirements. Te doping in Al(Ga)InP can be done in two ways:
第一种是原位掺杂,在外延生长Al(Ga)InP时直接掺杂生长Te。但是该方法有两个限制因素或缺点,一是当前使用MOCVD方法外延生长高质量的高Te掺杂AlInP材料难度较高,材料生长质量很难保障,进而有可能影响后续有源区的生长质量;二是Te在Al(Ga)InP等III-V族半导体材料中的扩散系数很高,在高掺杂浓度的高温生长条件下,或在后续芯片长时间高温工作的情况下,Te原子有可能扩散至有源区,进而降低内量子效率,影响芯片性能。The first is in-situ doping, which directly dopes and grows Te during the epitaxial growth of Al(Ga)InP. However, this method has two limiting factors or shortcomings. First, it is difficult to epitaxially grow high-quality, high-Te-doped AlInP materials using the MOCVD method. The quality of material growth is difficult to guarantee, which may affect the subsequent growth quality of the active area. Second, the diffusion coefficient of Te in III-V semiconductor materials such as Al(Ga)InP is very high. Under high-temperature growth conditions with high doping concentrations, or when subsequent chips operate at high temperatures for a long time, Te atoms have It may diffuse into the active area, thereby reducing the internal quantum efficiency and affecting chip performance.
第二种是非原位掺杂,在芯片工艺过程中,在低Si掺杂的Al(Ga)InP上蒸镀一层Te,通过RTP退火,将Te通过热扩散至Al(Ga)InP:Si中,达到提高掺杂浓度,降低n面扩展层电阻,减薄n面扩展层的目的。The second method is non-in-situ doping. During the chip process, a layer of Te is evaporated on the low-Si-doped Al(Ga)InP. Through RTP annealing, Te is thermally diffused into Al(Ga)InP:Si to increase the doping concentration, reduce the resistance of the n-side extension layer, and thin the n-side extension layer.
根据文献报道,高Si掺杂会影响Al(Ga)InP材料的生长质量,这种后续Te扩散还有一个好处,就是MOCVD外延生长Si掺杂Al(Ga)InP材料层时,可以降低Si的掺杂浓度,提高该层的生长质量,从而提升或保证后续有源区的材料质量。同时该方法还能控制Te的扩散深度,使其不扩散至有源区,不影响内量子效率。According to literature reports, high Si doping will affect the growth quality of Al(Ga)InP materials. This subsequent Te diffusion also has the advantage that when MOCVD epitaxial growth of Si-doped Al(Ga)InP material layers, it can reduce the Si The doping concentration improves the growth quality of this layer, thereby improving or ensuring the material quality of the subsequent active area. At the same time, this method can also control the diffusion depth of Te so that it does not diffuse into the active area and does not affect the internal quantum efficiency.
为了实现上述目的,本发明采用的技术方案如下:In order to achieve the above objects, the technical solutions adopted by the present invention are as follows:
LED结构包括外延叠层和位于外延叠层两侧的金属电极层,外延叠层至少包括沿生长方向依次堆叠的n型扩展层、n型限制层、有源层、p型限制层和p型导电层,其中n型扩展层是n型AlInP层或n型AlGaInP层,且在该n型扩展层中掺杂Te。The LED structure includes an epitaxial stack and metal electrode layers located on both sides of the epitaxial stack. The epitaxial stack at least includes an n-type extension layer, an n-type confinement layer, an active layer, a p-type confinement layer and a p-type layer sequentially stacked along the growth direction. A conductive layer, wherein the n-type extension layer is an n-type AlInP layer or an n-type AlGaInP layer, and the n-type extension layer is doped with Te.
n型扩展层中掺杂的Te是通过本发明的高温扩散工艺而使Te扩散到n型扩展层中的,并可以通过控制Te薄膜层的厚度、工艺时间和温度,使之在n型扩展层中的浓度大于或等于1×1019/cm3。同时,为了提高n型AlInP层或n型AlGaInP层的生长质量,本发明可以降低n型AlInP层或n型AlGaInP层中的Si的掺杂浓度,例如,本发明可以使之位于0.5×1017/cm3和5×1017/cm3之间,大大低于Te的掺杂浓度。Te doped in the n-type expansion layer is diffused into the n-type expansion layer through the high-temperature diffusion process of the present invention, and can be expanded in the n-type by controlling the thickness, process time and temperature of the Te film layer The concentration in the layer is greater than or equal to 1×10 19 /cm 3 . At the same time, in order to improve the growth quality of the n-type AlInP layer or n-type AlGaInP layer, the present invention can reduce the Si doping concentration in the n-type AlInP layer or n-type AlGaInP layer. For example, the present invention can make it be at 0.5×10 17 /cm 3 and 5 × 10 17 /cm 3 , which is much lower than the doping concentration of Te.
所述高温扩散工艺包括退火工艺。The high-temperature diffusion process includes an annealing process.
采用上述方案后,实现了n型扩散层的高掺杂浓度,进而降低了电阻。因此,在实现同样的横向导电能力的同时,可以减薄n型扩散层的厚度,同时提高n型层的生长质量,减少外延时间和成本。可选地,n型扩展层可以减薄至不掺杂Te时n型扩展层的1/4至1/6,例如为原来的1/5。After adopting the above solution, a high doping concentration of the n-type diffusion layer is achieved, thereby reducing the resistance. Therefore, while achieving the same lateral conductivity, the thickness of the n-type diffusion layer can be thinned, while improving the growth quality of the n-type layer and reducing epitaxy time and cost. Alternatively, the n-type extension layer can be thinned to 1/4 to 1/6 of the n-type extension layer without Te doping, for example, to 1/5 of the original thickness.
本发明并不严格限定外延叠层的构成,但通常来说,LED的外延叠层结构包括沿生长方向依次堆叠的n型扩展层、n型限制层、有源层、p型限制层和p型导电层。但是应当注意的是,在外延叠层中也可能出现其他的层,例如欧姆接触层,其均应视为在本发明的保护范围内。并且,在我延叠层的形成工艺中也可能出现临时的结构,例如临时衬底和临时的功能层,包括缓冲层、腐蚀层等。The present invention does not strictly limit the composition of the epitaxial stack, but generally speaking, the epitaxial stack structure of the LED includes an n-type extension layer, an n-type confinement layer, an active layer, a p-type confinement layer and a p-type confinement layer that are stacked sequentially along the growth direction. conductive layer. However, it should be noted that other layers, such as ohmic contact layers, may also appear in the epitaxial stack, which should be considered to be within the scope of the present invention. In addition, temporary structures may also appear during the formation process of the deposition layer, such as temporary substrates and temporary functional layers, including buffer layers, corrosion layers, etc.
但是,由于GaAs的带隙比较小,可以吸收部分有源层发出的光,会降低LED的外量子效率,考虑到这点,本发明优选为不设置n型GaAs欧姆接触层。However, since the band gap of GaAs is relatively small, it can absorb part of the light emitted by the active layer, which will reduce the external quantum efficiency of the LED. Considering this, the present invention preferably does not provide an n-type GaAs ohmic contact layer.
作为具体的实施方式,临时衬底可以是GaAs衬底。例如,一种实施方式是在GaAs衬底上生长外延叠层,所述外延叠层包括沿生长方向依次堆叠的n型缓冲层、n型腐蚀层、n型扩展层、n型限制层、有源层、p型限制层、p型导电层。As a specific implementation, the temporary substrate may be a GaAs substrate. For example, one embodiment is to grow an epitaxial stack on a GaAs substrate. The epitaxial stack includes an n-type buffer layer, an n-type etching layer, an n-type extension layer, an n-type confinement layer, and an n-type buffer layer. Source layer, p-type confinement layer, p-type conductive layer.
作为具体实施方式,为了在n型扩展层中掺杂Te,本发明制造工艺中,在n型扩展层上蒸镀一层Te薄膜层或CdTe薄膜层。As a specific implementation manner, in order to dope the n-type extension layer with Te, in the manufacturing process of the present invention, a Te thin film layer or a CdTe thin film layer is evaporated on the n-type extension layer.
Te薄膜层或CdTe薄膜层厚度依据n型扩展层的厚度来定,根据本发明的模拟和实际测量显示,Te薄膜层的厚度优选为大于或等于n型扩展层的厚度的0.03%,CdTe薄膜层的厚度优选为大于或等于n型扩展层的厚度的0.07%;进一步地,清洗残余的Te薄膜层或CdTe薄膜层,可选用硝酸或氢氧化钾。The thickness of the Te thin film layer or the CdTe thin film layer is determined based on the thickness of the n-type expansion layer. According to simulations and actual measurements of the present invention, the thickness of the Te thin film layer is preferably greater than or equal to 0.03% of the thickness of the n-type expansion layer. The CdTe film layer The thickness of the layer is preferably greater than or equal to 0.07% of the thickness of the n-type expansion layer; further, to clean the remaining Te thin film layer or CdTe thin film layer, nitric acid or potassium hydroxide can be used.
通过高温扩散工艺使得Te进入n型扩展层,RTP退火温度在300℃~500℃,实现n型扩展层的高掺杂,工艺时间1min~10min。一种可选的工艺是RTP退火工艺。Te is introduced into the n-type extension layer through a high temperature diffusion process, and the RTP annealing temperature is between 300°C and 500°C to achieve high doping of the n-type extension layer, and the process time is between 1 minute and 10 minutes. An optional process is the RTP annealing process.
根据本发明,高温扩散工艺步骤后n型扩展层的掺杂浓度能够提高至1×1019/cm3及以上。同时,与常规Si掺杂浓度为1018/cm3数量级的扩展层相比,本发明可将Si掺杂浓度降低至1017/cm3数量级。作为具体实施方式,本发明的金属电极层中优选为采用的是n金属半导体接触结构,例如n型AlInP:Si层/n金属结构。其中n金属优选为Au。According to the present invention, the doping concentration of the n-type extension layer can be increased to 1×10 19 /cm 3 and above after the high-temperature diffusion process step. At the same time, compared with the conventional expansion layer whose Si doping concentration is on the order of 10 18 /cm 3 , the present invention can reduce the Si doping concentration to the order of 10 17 /cm 3 . As a specific embodiment, the metal electrode layer of the present invention preferably adopts an n-metal semiconductor contact structure, such as an n-type AlInP:Si layer/n metal structure. The n metal is preferably Au.
可见,本发明通过在制造工艺的工序中形成了Te/CdTe薄膜层并退火,实现了n型扩展层的高掺杂浓度,进而降低了电阻。在实现同样的横向导电能力的同时,可以减薄n型扩展层的厚度,提高n型扩展层的生长质量,减少外延时间和成本。It can be seen that the present invention achieves a high doping concentration of the n-type extension layer by forming and annealing the Te/CdTe thin film layer in the manufacturing process, thereby reducing the resistance. While achieving the same lateral conductivity, the thickness of the n-type extension layer can be thinned, the growth quality of the n-type extension layer can be improved, and the epitaxy time and cost can be reduced.
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明作进一步的详细说明。In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
为了体现本发明相对于现有技术的特点和优点,在此首先描述一个对比实施例来进行对照,该对比实施例采用常规的LED结构,即n型扩展层中不掺Te。In order to reflect the characteristics and advantages of the present invention over the prior art, a comparative example is first described herein for comparison. The comparative example adopts a conventional LED structure, that is, Te is not doped in the n-type extension layer.
图1是对比实施例的LED结构的制造方法中生成的外延叠层的结构示意图。如图1所示,该对比实施例采用金属有机气相外延法在GaAs衬底1上从下至上依次生长n型GaAs:Si缓冲层2(200nm)、n型GaInP:Si腐蚀层3(150nm)、n型AlInP:Si扩展层4(3μm)、n型AlInP:Si限制层5(500nm)、有源层6(依次生长Al0.6GaInP阻挡层、GaInP、Al0.55GaInP、Al0.6GaInP阻挡层)、p型AlInP:Mg限制层7(500nm和p型GaP:Mg导电层8(3μm)。FIG. 1 is a schematic structural diagram of an epitaxial stack produced in a method for manufacturing an LED structure according to a comparative embodiment. As shown in Figure 1, this comparative example uses the metal organic vapor phase epitaxy method to sequentially grow an n-type GaAs:Si buffer layer 2 (200nm) and an n-type GaInP:Si corrosion layer 3 (150nm) on the GaAs substrate 1 from bottom to top. , n-type AlInP:Si extension layer 4 (3μm), n-type AlInP:Si confinement layer 5 (500nm), active layer 6 (sequential growth of Al 0.6 GaInP barrier layer, GaInP, Al 0.55 GaInP, Al 0.6 GaInP barrier layer) , p-type AlInP:Mg confinement layer 7 (500nm) and p-type GaP:Mg conductive layer 8 (3μm).
其中n型AlInP:Si扩展层4的厚度为3μm,Si掺杂浓度为2ⅹ1018/cm3。The thickness of the n-type AlInP:Si extension layer 4 is 3 μm, and the Si doping concentration is 2ⅹ10 18 /cm 3 .
图2是对比实施例的LED结构的制造方法中在外延叠层上形成p面金层电极层的结构示意图。图2的方向是图1上下翻转后的方向,如图2所示,在形成了外延叠层之后,在p型导电层8一侧生长p面金属电极层9。并且,将GaAs衬底1、GaAs:Si缓冲层2、n型GaInP:Si腐蚀层3通过腐蚀去降,露出n型AlInP:Si扩展层4。FIG2 is a schematic diagram of the structure of forming a p-side gold electrode layer on the epitaxial stack in the manufacturing method of the LED structure of the comparative embodiment. The direction of FIG2 is the direction of FIG1 after being turned upside down. As shown in FIG2, after the epitaxial stack is formed, a p-side metal electrode layer 9 is grown on one side of the p-type conductive layer 8. In addition, the GaAs substrate 1, the GaAs:Si buffer layer 2, and the n-type GaInP:Si etching layer 3 are removed by etching to expose the n-type AlInP:Si extension layer 4.
图3是对比实施例的LED结构的制造方法中在n型扩展层一侧形成金属电极层的结构示意图。如图3所示,该对比实施例在n型AlInP:Si扩展层4上进行n面金属电极层10的蒸镀工艺,在此采用Au。3 is a schematic structural diagram of forming a metal electrode layer on one side of the n-type extension layer in the manufacturing method of the LED structure of the comparative embodiment. As shown in FIG. 3 , in this comparative example, an evaporation process of the n-surface metal electrode layer 10 is performed on the n-type AlInP:Si extension layer 4, and Au is used here.
本发明实施例1:Embodiment 1 of the present invention:
图4是本发明实施例1的LED结构的制造方法中生成的外延叠层的结构示意图。如图4所示,该对比实施例本发明实施例1与上面描述的对比实施例具有类似的结构,其也是采用金属有机气相外延法在GaAs衬底1上从下至上依次生长n型GaAs:Si缓冲层2、n型GaInP:Si腐蚀层3、n型AlInP:Si扩展层4、n型AlInP:Si限制层5、有源层6(依次生长Al0.6GaInP阻挡层、GaInP、Al0.55GaInP、Al0.6GaInP阻挡层)、p型AlInP:Mg限制层7和p型GaP:Mg导电层8。FIG. 4 is a schematic structural diagram of an epitaxial stack produced in the method for manufacturing an LED structure in Embodiment 1 of the present invention. As shown in Figure 4, the comparative example Embodiment 1 of the present invention has a similar structure to the comparative example described above. It also uses the metal organic vapor phase epitaxy method to grow n-type GaAs sequentially from bottom to top on the GaAs substrate 1: Si buffer layer 2, n-type GaInP:Si corrosion layer 3, n-type AlInP:Si extension layer 4, n-type AlInP:Si confinement layer 5, active layer 6 (sequentially grow Al 0.6 GaInP barrier layer, GaInP, Al 0.55 GaInP , Al 0.6 GaInP barrier layer), p-type AlInP:Mg confinement layer 7 and p-type GaP:Mg conductive layer 8.
但是,与对比实施例不同的是,本发明实用例1中n型AlInP:Si扩展层的厚度可以降至400nm~2000nm,例如600nm。同时,Si的掺杂浓度可降至0.5ⅹ1017/cm3~5ⅹ1017/cm3,例如1ⅹ1017/cm31ⅹ1017/cm3。However, unlike the comparative example, the thickness of the n-type AlInP:Si extension layer in Practical Example 1 of the present invention can be reduced to 400 nm to 2000 nm, such as 600 nm. At the same time, the doping concentration of Si can be reduced to 0.5ⅹ10 17 /cm 3 ~ 5ⅹ10 17 /cm 3 , such as 1ⅹ10 17 /cm 3 1ⅹ10 17 /cm 3 .
图5是本发明实施例1的LED结构的制造方法中在外延叠层上形成p面金层电极层的结构示意图。接着,如图5所示,类似对比实施例,在形成了外延叠层之后,在p型导电层8一侧生长p面金属电极层9。并且,将GaAs衬底1、GaAs:Si缓冲层2、n型GaInP:Si腐蚀层3通过腐蚀去降,露出n型AlInP:Si扩展层4。FIG. 5 is a schematic structural diagram of forming a p-plane gold electrode layer on an epitaxial stack in the manufacturing method of an LED structure in Embodiment 1 of the present invention. Next, as shown in FIG. 5 , similar to the comparative embodiment, after forming the epitaxial stack, a p-plane metal electrode layer 9 is grown on the side of the p-type conductive layer 8 . Furthermore, the GaAs substrate 1, the GaAs:Si buffer layer 2, and the n-type GaInP:Si corrosion layer 3 are removed by etching to expose the n-type AlInP:Si expansion layer 4.
图6是本发明的实施例1的LED结构的制造方法中在n型扩展层中掺杂Te和在该侧形成金属电极层的结构示意图。如图6所示,在n型AlInP:Si扩展层4上蒸镀一层Te薄膜41,厚度为1nm,然后进行400℃RTP退火1min,使得Te进入n型AlInP:Si扩展层4(图中箭头方向),实现n型AlInP:Si扩展层4的高掺杂,然后用氢氧化钾清洗残余的Te薄膜层41。6 is a schematic structural diagram of doping Te in the n-type extension layer and forming a metal electrode layer on this side in the manufacturing method of the LED structure in Embodiment 1 of the present invention. As shown in Figure 6, a Te film 41 is evaporated on the n-type AlInP:Si extension layer 4, with a thickness of 1 nm, and then RTP annealed at 400°C for 1 minute, so that Te enters the n-type AlInP:Si extension layer 4 (in the figure arrow direction), to achieve high doping of the n-type AlInP:Si extension layer 4, and then use potassium hydroxide to clean the remaining Te thin film layer 41.
图7是本发明的实施例1的LED结构的制造方法中在n型扩展层侧形成金属电极层的结构示意图。与对比实施例为似,在n型AlInP:Si扩展层4上进行n面金属电极层10的蒸镀工艺,在此采用Au。7 is a schematic diagram of the structure of forming a metal electrode layer on the n-type extension layer side in the manufacturing method of the LED structure of Example 1 of the present invention. Similar to the comparative example, the n-side metal electrode layer 10 is evaporated on the n-type AlInP:Si extension layer 4, and Au is used here.
实施例2:Embodiment 2:
实施例2与实施例1类似,所不同的是实施例1中采用的Te薄膜层采用CdTe薄膜层代替。由于CdTe薄膜层中的Te含量少于Te薄膜层,因此要达到相同的Te掺杂浓度,需要更厚的CdTe薄膜层。Embodiment 2 is similar to Embodiment 1, except that the Te thin film layer used in Embodiment 1 is replaced by a CdTe thin film layer. Since the Te content in the CdTe film layer is less than that of the Te film layer, a thicker CdTe film layer is required to achieve the same Te doping concentration.
在实施例2中,同样的,首先采用金属有机气相外延法在GaAs衬底1上从下至上依次生长n型GaAs:Si缓冲层2、n型GaInP:Si腐蚀层3、n型AlInP:Si扩展层4、n型AlInP:Si限制层5、有源层6(依次生长Al0.6GaInP阻挡层、GaInP、Al0.55GaInP、Al0.6GaInP阻挡层)、p型AlInP:Mg限制层7、p型GaP:Mg导电层8。接着,生长p面金属电极层9,腐蚀衬底1、GaAs:Si缓冲层2、n型GaInP:Si腐蚀层3。然后,在n型AlInP:Si扩展层4上蒸镀一层CdTe薄膜41,厚度为2nm,然后进行400℃RTP退火1min,使得Te进入n型AlInP:Si扩展层4,由此实现n型AlInP:Si扩展层4的Te高掺杂。然后用硝酸清洗残余的CdTe薄膜,之后再进行n面金属电极层9的蒸镀工艺,在此采用Au。In Embodiment 2, similarly, first, the metal organic vapor phase epitaxy method is used to grow n-type GaAs:Si buffer layer 2, n-type GaInP:Si corrosion layer 3, and n-type AlInP:Si on the GaAs substrate 1 from bottom to top. Extension layer 4, n-type AlInP:Si confinement layer 5, active layer 6 (sequential growth of Al 0.6 GaInP barrier layer, GaInP, Al 0.55 GaInP, Al 0.6 GaInP barrier layer), p-type AlInP:Mg confinement layer 7, p-type GaP:Mg conductive layer 8. Next, the p-plane metal electrode layer 9 is grown, and the substrate 1, GaAs:Si buffer layer 2, and n-type GaInP:Si etching layer 3 are etched. Then, a layer of CdTe film 41 is evaporated on the n-type AlInP:Si extension layer 4 with a thickness of 2 nm, and then RTP annealing is performed at 400°C for 1 minute, so that Te enters the n-type AlInP:Si extension layer 4, thereby realizing n-type AlInP :Si extension layer 4 is highly doped with Te. Then, the remaining CdTe film is cleaned with nitric acid, and then the n-side metal electrode layer 9 is evaporated, and Au is used here.
在该实施例2中,同样的,n型AlInP:Si扩展层4的厚度可以为400nm~2000nm,例如600nm,同时Si的掺杂浓度降至0.5ⅹ1017/cm3~5ⅹ1017/cm3,例如1ⅹ1017/cm3。In this Embodiment 2, similarly, the thickness of the n-type AlInP:Si extension layer 4 can be 400nm~2000nm, such as 600nm, while the Si doping concentration is reduced to 0.5ⅹ10 17 /cm 3 ~ 5ⅹ10 17 /cm 3 , For example, 1ⅹ10 17 /cm 3 .
在上述实施例1和实施例2中,n型AlInP:Si扩展层可由n型AlGaInP:Si扩展层代替。In the above-described Embodiment 1 and Embodiment 2, the n-type AlInP:Si extension layer may be replaced by an n-type AlGaInP:Si extension layer.
本发明上述提出的LED结构,以及通过上述制造方法制造的LED结构可以通过倒装封装工艺等制造形成LED芯片。The LED structure proposed above in the present invention and the LED structure manufactured by the above manufacturing method can be manufactured to form LED chips through a flip-chip packaging process or the like.
综上所述,在上述实施例1和实施例2中,由于在n型扩展层中通过退火工艺掺杂了Te,增强了n型扩展层的导电能力。因此,相比于现有技术,在实现同样的横向导电能力的情况下,能够减薄n型扩展层的厚度,降低外延时间。同时,由于可以降低n型扩展层中的Si的掺杂浓度,因此本发明还有利于提高扩展层材料的生长质量,减少外延成本。To sum up, in the above-mentioned Embodiment 1 and Embodiment 2, since the n-type extension layer is doped with Te through the annealing process, the conductivity of the n-type extension layer is enhanced. Therefore, compared with the existing technology, the thickness of the n-type extension layer can be thinned and the epitaxy time can be reduced while achieving the same lateral conductivity. At the same time, since the doping concentration of Si in the n-type extension layer can be reduced, the present invention is also beneficial to improving the growth quality of the extension layer material and reducing the cost of epitaxy.
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent substitutions, improvements, etc. shall be included in the protection scope of the present invention.
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