CN117795494A - 处理器以及字节序转换方法 - Google Patents
处理器以及字节序转换方法 Download PDFInfo
- Publication number
- CN117795494A CN117795494A CN202280053523.5A CN202280053523A CN117795494A CN 117795494 A CN117795494 A CN 117795494A CN 202280053523 A CN202280053523 A CN 202280053523A CN 117795494 A CN117795494 A CN 117795494A
- Authority
- CN
- China
- Prior art keywords
- byte
- data
- circuit
- conversion circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 145
- 238000000034 method Methods 0.000 title claims description 19
- 230000002093 peripheral effect Effects 0.000 claims abstract description 89
- 230000001934 delay Effects 0.000 claims description 8
- 230000006870 function Effects 0.000 claims description 5
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 20
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 15
- 230000003111 delayed effect Effects 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021-153025 | 2021-09-21 | ||
| JP2021153025A JP2023044909A (ja) | 2021-09-21 | 2021-09-21 | プロセッサおよびエンディアン変換方法 |
| PCT/JP2022/026785 WO2023047762A1 (ja) | 2021-09-21 | 2022-07-06 | プロセッサおよびエンディアン変換方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117795494A true CN117795494A (zh) | 2024-03-29 |
Family
ID=85720442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280053523.5A Pending CN117795494A (zh) | 2021-09-21 | 2022-07-06 | 处理器以及字节序转换方法 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2023044909A (ja) |
| CN (1) | CN117795494A (ja) |
| GB (1) | GB202401725D0 (ja) |
| WO (1) | WO2023047762A1 (ja) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08202646A (ja) * | 1995-01-25 | 1996-08-09 | Nec Corp | Ｉ／ｏコントローラ |
| JP2000003304A (ja) * | 1998-06-12 | 2000-01-07 | Nec Corp | データ処理装置とデータアライン装置 |
| WO2010029794A1 (ja) * | 2008-09-12 | 2010-03-18 | 株式会社ルネサステクノロジ | データ処理装置及び半導体集積回路装置 |
-
2021
- 2021-09-21 JP JP2021153025A patent/JP2023044909A/ja active Pending
-
2022
- 2022-07-06 WO PCT/JP2022/026785 patent/WO2023047762A1/ja active Application Filing
- 2022-07-06 GB GBGB2401725.3A patent/GB202401725D0/en active Pending
- 2022-07-06 CN CN202280053523.5A patent/CN117795494A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB202401725D0 (en) | 2024-03-27 |
| JP2023044909A (ja) | 2023-04-03 |
| WO2023047762A1 (ja) | 2023-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE36482E (en) | Data processor and data processing system and method for accessing a dynamic type memory using an address multiplexing system | |
| JPS5855528B2 (ja) | アドレス発生装置 | |
| US11409679B2 (en) | System component and use of a system component | |
| US5634013A (en) | Bus bridge address translator | |
| US6691179B2 (en) | Direct memory access controller for converting a transfer mode flexibly in accordance with a data transfer counter value | |
| US6684267B2 (en) | Direct memory access controller, and direct memory access control method | |
| US6272583B1 (en) | Microprocessor having built-in DRAM and internal data transfer paths wider and faster than independent external transfer paths | |
| JP2001084229A (ja) | Ｓｉｍｄ型プロセッサ | |
| EP0910014B1 (en) | Program loading method and apparatus | |
| US5497466A (en) | Universal address generator | |
| US9116783B2 (en) | Bus connection circuit, semiconductor device and operation method of bus connection circuit for making procedure for switching between a 1-cycle transfer and a 2-cycle transfer unnecessary | |
| JP4855864B2 (ja) | ダイレクトメモリアクセスコントローラ | |
| KR100306548B1 (ko) | 컴퓨터시스템메모리콘트롤러및버스트데이터순서변환방법 | |
| EP0338564B1 (en) | Microprogram branching method and microsequencer employing the method | |
| CN117795494A (zh) | 处理器以及字节序转换方法 | |
| US7783804B2 (en) | Bus relay device and bus control system including plurality of bus masters, bus slave, interconnect section, and bridge section | |
| US4964037A (en) | Memory addressing arrangement | |
| US6725369B1 (en) | Circuit for allowing data return in dual-data formats | |
| US7240144B2 (en) | Arbitration of data transfer requests | |
| CN110647355B (zh) | 数据处理器和数据处理方法 | |
| JPH11259417A (ja) | バスアクセス方式およびバスアクセス制御装置 | |
| JP4642398B2 (ja) | 共有バス調停システム | |
| JP5361773B2 (ja) | データアクセス制御装置 | |
| JPH0721121A (ja) | 通信制御ｌｓｉ | |
| JP2001109709A (ja) | バス拡張回路とその制御方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |