CN117691999A - Dynamic parameter testing method for ADC in DSP - Google Patents
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Abstract
The invention discloses a dynamic parameter testing method for an ADC (analog to digital converter) in a DSP (digital signal processor), which relates to the technical field of signal processing, wherein an ADC module, a data speed matching module, a data storage module, a data processing module and a communication interface are arranged in a DSP chip; the sine wave signal generator is used as a signal source to generate a sine wave signal; generating a digital signal according to the sine wave signal through an ADC module; the data speed matching module obtains a reading speed according to the speed of the ADC module for generating the digital signal, and carries the digital signal to the data storage module according to the reading speed; the data processing module performs abnormal number clearing processing on the digital signals in the data storage module and then performs weight reduction processing; the data processing module generates a dynamic data segment according to the digital signal after weight reduction, submits the dynamic data segment to the communication interface, the communication interface integrates the dynamic data segment to generate a dynamic factor, the dynamic factor is submitted to the PC end, and the PC end calculates dynamic parameters according to the dynamic factor through a MATLAB program.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a dynamic parameter testing method for an ADC (analog-to-digital converter) in a DSP (digital signal processor).
Background
An ADC (analog-to-digital converter) is an electronic device that converts an analog signal into a digital signal. In Digital Signal Processors (DSP), dynamic parametric testing of ADCs is an important task for evaluating the performance and accuracy of ADCs. The dynamic parameters include signal accuracy, signal distortion, signal-to-noise ratio, etc. The high-precision test of the ADC in the DSP is greatly related to the test environment, and the larger the test network is, the larger the environmental interference which is easy to introduce is, so that the high-precision test of the ADC is more difficult to carry out.
How to reduce the cost of storing conversion data and how to accurately acquire ADC conversion data on time, and how to avoid the problem that a high-speed communication interface acquires conversion data to generate a large amount of repeated data are considered.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a dynamic parameter testing method for an ADC in a DSP.
The aim of the invention can be achieved by the following technical scheme: a method for dynamic parameter testing of an ADC within a DSP, comprising the steps of:
step S1: setting an ADC module, a data speed matching module, a data storage module, a data processing module and a communication interface in a DSP chip;
step S2: the sine wave signal generator is used as a signal source to generate a sine wave signal; acquiring a sine wave signal through an ADC module, and generating a digital signal according to the sine wave signal by the ADC module;
step S3: the data speed matching module obtains a reading speed according to the speed of the ADC module for generating the digital signal, and carries the digital signal to the data storage module for storage according to the reading speed;
step S4: the data processing module performs abnormal number clearing processing on the digital signals in the data storage module and then performs weight reduction processing;
step S5: the data processing module generates a dynamic data segment according to the digital signal after weight reduction, submits the dynamic data segment to the communication interface, the communication interface integrates the dynamic data segment to generate a dynamic factor, the dynamic factor is submitted to the PC end, and the PC end calculates dynamic parameters according to the dynamic factor through a MATLAB program.
Further, the ADC module comprises a timer, a counter and a plurality of analog-to-digital converters;
the timer is used for setting the sampling frequency of the analog-to-digital converter and acquiring a sampling period according to the inverse of the sampling frequency;
the analog-to-digital converter acquires sine wave signals at fixed time according to the sampling period and converts the acquired sine wave signals into digital signals which can be identified by the DSP;
the counter is used for counting the number of digital signals generated by the analog-to-digital converters, and simultaneously, when counting the number of the digital signals, generating a time stamp according to the counting time and the MAC address of the analog-to-digital converters.
Further, the number of analog-to-digital converters and the number of digital signals counted by a timer are obtained;
if the number of the analog-to-digital converters is not equal to the number of the digital signals counted by the timer, generating a first-level early warning signal, informing a user that the analog-to-digital converters are damaged, and detecting damaged parts of the analog-to-digital converters;
after the analog-to-digital converter generates a digital signal, the counter counts the digital signal and generates a time stamp according to the counting time and the MAC address of the analog-to-digital converter;
acquiring a statistical period and a time increment value corresponding to the analog-to-digital converter according to the time stamp;
setting a time change interval and a period change interval;
if the time increment value belongs to the time change interval, acquiring the MAC address of the analog-to-digital converter, generating a secondary early warning signal according to the MAC address, and informing a user that the analog-to-digital converter has abnormal communication, wherein corresponding measures are needed to be taken by the user;
and acquiring the period difference according to the statistical period, if the period difference belongs to the period change interval, generating a three-level early warning signal to inform a user that the ADC module is abnormal in communication delay, and taking corresponding measures by the user.
Further, the process of the data speed matching module for carrying the digital signal to the data storage module for storage according to the reading speed includes:
generating a data carrying program according to the reading speed, and carrying the digital signal to a data storage module;
the design thought of the data handling program is to design a delay statement, the number of system clock cycles of the delay statement is adjusted according to the reading speed, and the stepping precision can reach 1 system clock cycle;
and the speed of generating the digital signal by the ADC is matched through a delay statement, so that the digital signal generated by the ADC module is carried to the data storage module.
Further, the process of performing the abnormal number clearing processing on the digital signal by the data processing module includes:
generating a receiving moment according to the time of the digital signal received by the data storage module;
setting a receiving time threshold;
randomly acquiring the receiving time of a certain digital signal, and marking the receiving time as the origin time;
acquiring a same-domain signal time interval according to the origin time and the receiving time threshold;
the digital signals received in the same domain signal time interval are digital signals converted by a plurality of analog-to-digital converters in the ADC module at the same time;
setting an abnormal number threshold;
converting a digital signal received in a signal time region of the same domain into a binary value;
comparing binary values of the digital signals to obtain different numbers of digits;
the mode of the abnormal number is obtained and used as a standard abnormal value, and an abnormal number interval is generated according to the standard abnormal value and an abnormal number threshold;
if the number of the abnormal digits of the digital signal belongs to the abnormal number interval, the digital signal is a normal signal;
if the abnormal number of the digital signals does not belong to the abnormal number interval, marking the digital signals as abnormal signals, generating four-level early warning signals according to the abnormal signals, informing a user that the analog-digital converter has abnormal conditions, and making corresponding measures by the user.
Further, the process of the data processing module for performing the de-duplication processing on the digital signal includes:
randomly marking a digital signal received in a certain same domain signal time interval as a quasi-value signal of the same domain signal time interval;
setting a data weight reduction period; performing de-duplication processing on the quasi-value signal in the data de-duplication period:
and acquiring the quasi-value signals of different same-domain signal time intervals, sequentially comparing binary values of the quasi-value signals according to a time sequence, generating continuous quasi-value signals according to the binary values if the binary values are completely consistent, merging the same-domain signal time intervals, and taking the continuous quasi-value signals as the quasi-value signals of the merged same-domain signal time intervals.
Further, the process of generating the dynamic data segment according to the digital signal after weight reduction includes:
acquiring the baud rate of the DSP; setting a transmission limiting coefficient;
generating maximum transmission data bits according to the baud rate and the transmission limiting coefficient;
acquiring binary values of the quasi-value signals in the same weight reduction period, and recording the binary values as dynamic data;
splitting and combining the dynamic data according to the maximum transmission data bit to generate a dynamic data segment;
taking the maximum transmission data bit as the size of single transmission data, wherein the single transmission data comprises a 1-bit starting bit, a 1-bit marking bit, a plurality of data bits and a 1-bit stopping bit; namely, the dynamic data segment comprises a 1-bit start bit, a 1-bit mark bit, a plurality of data bits and a 1-bit stop bit;
setting the binary value of one quasi-value signal as w bits, wherein e quasi-value signals exist in the weight reduction period; setting the size of a data bit to be r bits;
if w is larger than or equal to r, splitting binary values of the quasi-value signals, filling the binary values into data bits, and filling the more w-r bit data into data bits of the next dynamic data segment;
if w is less than r, binary data of the quasi-value signal are subjected to combination processing, binary values are filled into data bits, the binary value of the next quasi-value signal is obtained, the binary values are filled into the data bits, and then the excessive 2w-r bit data are filled into the data bits of the next dynamic data segment;
if the data bit of the last dynamic data segment has data, no operation is needed, and if the data bit is NULL, 0 is filled.
Further, the process of integrating the dynamic data segment by the communication interface and generating the dynamic factor includes:
setting an idle time threshold T over ；
When the communication interface receives the dynamic data segment, starting timing, and if a new dynamic data segment is received, emptying the timing; when the timing is greater than or equal to the idle time threshold T over And when the dynamic factor is generated, the data bit data of all the dynamic data segments acquired by the communication interface are sequenced and integrated according to the marking bit data of the dynamic data segments, and the dynamic factor is submitted to the PC end.
Compared with the prior art, the invention has the beneficial effects that:
1. the traditional ADC dynamic parameter testing method needs to use an external memory to store conversion data, so that the complexity and the cost of the system are increased; the method stores the conversion data through the data storage module in the DSP, namely stores the conversion data into the on-chip memory of the DSP, thereby simplifying the system design and reducing the cost.
2. In the traditional method, the sending speed of the high-speed communication interface cannot be consistent with the refreshing speed of the converted data in the ADC result register, the control accuracy of the sending speed is poor, the converted data can be sent at a higher speed only to ensure that the data is not lost, and the additional data weight reduction work is needed in the later period; according to the method, the reading speed is obtained by generating the digital signal according to the ADC module, the corresponding data carrying program is generated according to the reading speed, and the digital signal is carried to the data storage module through the data carrying program, so that the real-time performance of the data is ensured, and high-speed communication interface hardware is not needed.
Drawings
FIG. 1 is a flow chart of the present invention.
Detailed Description
As shown in fig. 1, a dynamic parameter testing method for an ADC in a DSP includes the following steps:
step S1: setting an ADC module, a data speed matching module, a data storage module, a data processing module and a communication interface in a DSP chip;
step S2: the sine wave signal generator is used as a signal source to generate a sine wave signal; acquiring a sine wave signal through an ADC module, and generating a digital signal according to the sine wave signal by the ADC module;
step S3: the data speed matching module obtains a reading speed according to the speed of the ADC module for generating the digital signal, and carries the digital signal to the data storage module for storage according to the reading speed;
step S4: the data processing module performs abnormal number clearing processing on the digital signals in the data storage module and then performs weight reduction processing;
step S5: the data processing module generates a dynamic data segment according to the digital signal after weight reduction, submits the dynamic data segment to the communication interface, the communication interface integrates the dynamic data segment to generate a dynamic factor, the dynamic factor is submitted to the PC end, and the PC end calculates dynamic parameters according to the dynamic factor through a MATLAB program.
Setting an ADC module, a data speed matching module, a data storage module, a data processing module and a communication interface in a DSP chip;
the ADC module comprises a timer, a counter and a plurality of analog-to-digital converters;
the timer is used for setting the sampling frequency of the analog-to-digital converter and acquiring a sampling period according to the inverse of the sampling frequency;
the analog-to-digital converter acquires sine wave signals at fixed time according to the sampling period and converts the acquired sine wave signals into digital signals which can be identified by the DSP;
the counter is used for counting the number of digital signals generated by the analog-to-digital converters, and generating a time stamp according to the counting time and the MAC address of the analog-to-digital converters when counting the number of the digital signals;
the number of a plurality of analog-digital converters is obtained and is recorded as i;
acquiring the number of digital signals counted by a timer and recording the number as j;
if i is not equal to j, generating a first-level early warning signal to inform a user that the analog-to-digital converter is damaged, and detecting damaged components of the analog-to-digital converter;
acquiring a statistical period and a time increment value corresponding to the analog-to-digital converter according to the time stamp;
after the analog-to-digital converter receives the sine wave signal, converting the sine wave signal into a digital signal; after the analog-to-digital converter generates a digital signal, the counter counts the digital signal and generates a time stamp according to the counting time and the MAC address of the analog-to-digital converter;
setting a time stamp of an analog-to-digital converter as TX 1 The next time is time stamped as TX 2 Thereby, several time stamps TX can be obtained 1 ，TX 2 ，……，TX n ；
Acquiring a statistical period from the time stamp
The time increment value is
Setting a time change interval t and a period change interval z;
if the time increment value TXvg is smaller than the time change interval t, the MAC address of the analog-to-digital converter is obtained, a secondary early warning signal is generated according to the MAC address, a user is informed that the analog-to-digital converter has abnormal communication, and the user needs to take corresponding measures;
acquiring a period difference TXtg according to the statistical period, if the period difference TXtg is in a period change interval z, generating a three-level early warning signal to inform a user that the ADC module is abnormal in communication delay, and taking corresponding measures by the user;
wherein the period difference is
The data speed matching module is used for acquiring a reading clock according to the speed of the ADC module for generating the digital signal, and carrying the digital signal generated by the ADC module to the data storage module for storage according to the reading clock;
the data storage module comprises an on-chip memory and is used for storing the digital signals generated by the analog-to-digital converter in the ADC module;
the data processing module is used for carrying out weight reduction processing on the digital signals stored by the data storage module, generating dynamic data segments according to the weight-reduced digital signals and submitting the dynamic data segments to the communication interface; meanwhile, a high-voltage interval and a low-voltage interval are obtained according to the digital signals after weight reduction, and if the digital signals received by the data storage module are positioned in the high-voltage interval or the low-voltage interval, corresponding early warning signals are generated;
the communication interface is used for carrying out integration processing on the dynamic data segments to generate dynamic factors, submitting the dynamic factors to the PC end, and calculating dynamic parameters by the PC end according to the dynamic factors through a MATLAB program;
specifically, the process that the data speed matching module carries the digital signal to the data storage module for storage according to the reading speed includes:
generating a data carrying program according to the reading speed, and carrying the digital signal to a data storage module;
the design idea of the data handling program is as follows:
generating a delay statement, adjusting the number of system clock cycles of the delay statement according to the reading speed, and setting the stepping precision to be 1 system clock cycle;
matching the speed of the ADC to generate a digital signal through a delay statement, so that the digital signal generated by the ADC module is carried to a data storage module;
the key statements of the data handling program and their description are as follows:
LOOP_SIMPLE; loop sentence
RPT#WAIT_CLK_NUM ；
||nop; delay (wait_clk_num+1) system clock cycles (delay m system clock cycles)
Moval, @ adc_result 0; moving digital signals to AL variables
MOV xar7++, AL; moving the value of the AL variable into the memory XAR7 array
BANZ LOOP_SIMPLE, XAR 0-; judgment statement, judge number of times of having circulated XAR0 internal stored variable value (judge whether having circulated N times)
In general, the time for converting the sine wave signal into the digital signal by the analog-digital converter is more than 10 system clock cycles of the DSP;
calculating the number of system clock cycles required by each assembler instruction, and then counting the number of system clock cycles required by the whole data handling program, wherein the number of system clock cycles required by the whole data handling program is smaller than 10 under normal conditions, so that the data handling program has feasibility;
specifically, the process of performing the abnormal number clearing processing on the digital signal by the data processing module includes:
generating a receiving moment according to the time of the digital signal received by the data storage module;
setting a receiving time threshold tmin;
randomly acquiring the receiving time of a certain digital signal, and marking the receiving time as the origin time t 0 ；
According to the origin time t 0 And a reception time threshold tmin for acquiring a same-domain signal time interval t 0 -tmin，t 0 +tmin)；
The digital signals received in the same domain signal time interval are digital signals converted by a plurality of analog-to-digital converters in the ADC module at the same time;
it follows that the digital signals received within the same domain signal time interval should be approximately the same, with equivalent effectiveness;
setting an abnormal number threshold g;
converting a digital signal received in a signal time region of the same domain into a binary value;
comparing binary values of the digital signals to obtain different numbers of digits;
obtaining the mode of the abnormal digit number as the standard abnormal digit value g 0 And generating an outlier interval [ g ] according to the standard outlier value and the outlier threshold g 0 -g，g 0 +g]；
If the number of the abnormal digits of the digital signal belongs to the abnormal number interval, the digital signal is a normal signal;
if the abnormal number of the digital signals does not belong to the abnormal number interval, marking the digital signals as abnormal signals, generating four-level early warning signals according to the abnormal signals, informing a user that the analog-digital converter has abnormal conditions, and making corresponding measures by the user;
specifically, the process of performing the de-duplication processing on the digital signal by the data processing module includes:
randomly marking a digital signal received in a certain same domain signal time interval as a quasi-value signal of the same domain signal time interval;
setting a data weight-reduction period JaC;
performing de-duplication processing on the quasi-value signal in the data de-duplication period:
acquiring standard value signals of different same-domain signal time intervals, sequentially comparing binary values of the standard value signals according to a time sequence, generating continuous standard value signals according to the binary values if the binary values are completely consistent, merging the same-domain signal time intervals, and taking the continuous standard value signals as standard value signals of the merged same-domain signal time intervals;
i.e. there is a co-domain signal time interval t i -tmin，t i +tmin) and [ t ] i+1 -tmin，t i+1 +tmin), and t i +tmin＝t i+1 -tmin；
If the same domain signal time interval [ t ] i -tmin，t i +tmin) and [ t ] i+1 -tmin，t i+1 If the binary values of the quasi-valued signals of +tmin) are 01001000100011, 01001000100011 is a continuous quasi-valued signal and the same domain signal time interval t is combined i -tmin，t i +tmin) and [ t ] i+1 -tmin，t i+1 +tmin), i.e. the same-domain signal time interval t i -tmin，t i+1 +tmin) is 01001000100011;
specifically, the process of generating the dynamic data segment according to the digital signal after weight reduction includes:
acquisition of baud rate B of DSP dsp ；
Setting a transmission limiting coefficient k;
according to baud rate B dsp And the transmission limiting coefficient k generates the maximum transmission data bit bps=kxb dsp ；
Acquiring binary values of the quasi-value signals in the same weight reduction period JaC, and recording the binary values as dynamic data;
splitting and combining the dynamic data according to the maximum transmission data bit to generate a dynamic data segment;
taking the maximum transmission data bit Bps as the size of single transmission data, wherein the single transmission data comprises a 1-bit starting bit, a 1-bit marking bit, a plurality of data bits and a 1-bit stopping bit; namely, the dynamic data segment comprises a 1-bit start bit, a 1-bit mark bit, a plurality of data bits and a 1-bit stop bit;
if the maximum transmission data bit Bps is 26 bits, single data transmission is composed of 1-bit start bit, 1-bit mark bit, 23-bit data bit and 1-bit stop bit;
splitting and combining the dynamic data according to the size of the data bit;
setting the binary value of one quasi-value signal as w bits, and setting the dynamic data size as w×e bits when e quasi-value signals exist in the weight reduction period;
setting the size of a data bit to be r bits;
if w is larger than or equal to r, splitting binary values of the quasi-value signals, filling the binary values into data bits, and filling the more w-r bit data into data bits of the next dynamic data segment;
if w is less than r, binary data of the quasi-value signal are subjected to combination processing, binary values are filled into data bits, the binary value of the next quasi-value signal is obtained, the binary values are filled into the data bits, and then the excessive 2w-r bit data are filled into the data bits of the next dynamic data segment;
if the data bit of the last dynamic data segment has data, no operation is needed, and if the data bit is NULL, 0 is filled;
specifically, the process of integrating the dynamic data segments by the communication interface and generating the dynamic factor includes:
setting an idle time threshold T over ；
When the communication interface receives the dynamic data segment, starting timing, and if a new dynamic data segment is received, emptying the timing;
when the timing is greater than or equal to the idle time threshold T over When the dynamic factor is generated, the data bit data of all the dynamic data segments acquired by the communication interface are sequenced and integrated according to the marking bit data of the dynamic data segments, and the dynamic factor is submitted to the PC end;
the above embodiments are only for illustrating the technical method of the present invention and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present invention may be modified or substituted without departing from the spirit and scope of the technical method of the present invention.
Claims (8)
1. A method for testing dynamic parameters of an ADC in a DSP, comprising the steps of:
step S1: setting an ADC module, a data speed matching module, a data storage module, a data processing module and a communication interface in a DSP chip;
step S2: the sine wave signal generator is used as a signal source to generate a sine wave signal; acquiring a sine wave signal through an ADC module, and generating a digital signal according to the sine wave signal by the ADC module;
step S3: the data speed matching module obtains a reading speed according to the speed of the ADC module for generating the digital signal, and carries the digital signal to the data storage module for storage according to the reading speed;
step S4: the data processing module performs abnormal number clearing processing on the digital signals in the data storage module and then performs weight reduction processing;
step S5: the data processing module generates a dynamic data segment according to the digital signal after weight reduction, submits the dynamic data segment to the communication interface, the communication interface integrates the dynamic data segment to generate a dynamic factor, the dynamic factor is submitted to the PC end, and the PC end calculates dynamic parameters according to the dynamic factor through a MATLAB program.
2. The method of claim 1, wherein the ADC module comprises a timer, a counter, and a plurality of analog-to-digital converters;
the timer is used for setting the sampling frequency of the analog-to-digital converter and acquiring a sampling period according to the inverse of the sampling frequency;
the analog-to-digital converter acquires sine wave signals at fixed time according to the sampling period and converts the acquired sine wave signals into digital signals which can be identified by the DSP;
the counter is used for counting the number of digital signals generated by the analog-to-digital converters, and simultaneously, when counting the number of the digital signals, generating a time stamp according to the counting time and the MAC address of the analog-to-digital converters.
3. The method for testing the dynamic parameters of the ADC in the DSP as set forth in claim 2, wherein the number of analog-to-digital converters and the number of digital signals counted by the timer are obtained;
if the number of the analog-to-digital converters is not equal to the number of the digital signals counted by the timer, generating a first-level early warning signal, informing a user that the analog-to-digital converters are damaged, and detecting damaged parts of the analog-to-digital converters;
after the analog-to-digital converter generates a digital signal, the counter counts the digital signal and generates a time stamp according to the counting time and the MAC address of the analog-to-digital converter;
acquiring a statistical period and a time increment value corresponding to the analog-to-digital converter according to the time stamp;
setting a time change interval and a period change interval;
if the time increment value belongs to the time change interval, acquiring the MAC address of the analog-to-digital converter, generating a secondary early warning signal according to the MAC address, and informing a user that the analog-to-digital converter has abnormal communication, wherein corresponding measures are needed to be taken by the user;
and acquiring the period difference according to the statistical period, if the period difference belongs to the period change interval, generating a three-level early warning signal to inform a user that the ADC module is abnormal in communication delay, and taking corresponding measures by the user.
4. A method for testing dynamic parameters of an ADC in a DSP according to claim 3, wherein the process of the data speed matching module transferring the digital signal to the data storage module for storage according to the reading speed comprises:
generating a data carrying program according to the reading speed, and carrying the digital signal to a data storage module;
the design thought of the data handling program is to generate a delay statement, the number of system clock cycles of the delay statement is adjusted according to the reading speed, and the stepping precision is set to be up to 1 system clock cycle;
and the speed of generating the digital signal by the ADC is matched through a delay statement, so that the digital signal generated by the ADC module is carried to the data storage module.
5. The method for testing the dynamic parameters of the ADC in the DSP according to claim 4, wherein the process of performing the outlier removal processing on the digital signal by the data processing module comprises:
generating a receiving moment according to the time of the digital signal received by the data storage module;
setting a receiving time threshold;
randomly acquiring the receiving time of a certain digital signal, and marking the receiving time as the origin time;
acquiring a same-domain signal time interval according to the origin time and the receiving time threshold;
the digital signals received in the same domain signal time interval are digital signals converted by a plurality of analog-to-digital converters in the ADC module at the same time;
setting an abnormal number threshold;
converting a digital signal received in a signal time region of the same domain into a binary value;
comparing binary values of the digital signals to obtain different numbers of digits;
the mode of the abnormal number is obtained and used as a standard abnormal value, and an abnormal number interval is generated according to the standard abnormal value and an abnormal number threshold;
if the number of the abnormal digits of the digital signal belongs to the abnormal number interval, the digital signal is a normal signal;
if the abnormal number of the digital signals does not belong to the abnormal number interval, marking the digital signals as abnormal signals, generating four-level early warning signals according to the abnormal signals, informing a user that the analog-digital converter has abnormal conditions, and making corresponding measures by the user.
6. The method for testing the dynamic parameters of the ADC in the DSP according to claim 5, wherein the step of performing the de-duplication processing on the digital signal by the data processing module comprises:
randomly marking a digital signal received in a certain same domain signal time interval as a quasi-value signal of the same domain signal time interval;
setting a data weight reduction period; performing de-duplication processing on the quasi-value signal in the data de-duplication period:
and acquiring the quasi-value signals of different same-domain signal time intervals, sequentially comparing binary values of the quasi-value signals according to a time sequence, generating continuous quasi-value signals according to the binary values if the binary values are completely consistent, merging the same-domain signal time intervals, and taking the continuous quasi-value signals as the quasi-value signals of the merged same-domain signal time intervals.
7. The method of claim 6, wherein generating the dynamic data segment from the de-duplicated digital signal comprises:
acquiring the baud rate of the DSP and setting a transmission limiting coefficient;
generating maximum transmission data bits according to the baud rate and the transmission limiting coefficient;
acquiring binary values of the quasi-value signals in the same weight reduction period, and recording the binary values as dynamic data;
splitting and combining the dynamic data according to the maximum transmission data bit to generate a dynamic data segment;
taking the maximum transmission data bit as the size of single transmission data, wherein the single transmission data comprises a 1-bit starting bit, a 1-bit marking bit, a plurality of data bits and a 1-bit stopping bit; namely, the dynamic data segment comprises a 1-bit start bit, a 1-bit mark bit, a plurality of data bits and a 1-bit stop bit;
setting the binary value of one quasi-value signal as w bits, wherein e quasi-value signals exist in the weight reduction period; setting the size of a data bit to be r bits;
if w is larger than or equal to r, splitting binary values of the quasi-value signals, filling the binary values into data bits, and filling the more w-r bit data into data bits of the next dynamic data segment;
if w is less than r, binary data of the quasi-value signal are subjected to combination processing, binary values are filled into data bits, the binary value of the next quasi-value signal is obtained, the binary values are filled into the data bits, and then the excessive 2w-r bit data are filled into the data bits of the next dynamic data segment;
if the data bit of the last dynamic data segment has data, no operation is needed, and if the data bit is NULL, 0 is filled.
8. The method for testing the dynamic parameters of the ADC in the DSP according to claim 7, wherein the process of integrating the dynamic data segments by the communication interface and generating the dynamic factor comprises:
setting an idle time threshold T over ；
When the communication interface receives the dynamic data segment, starting timing, and if a new dynamic data segment is received, emptying the timing; when the timing is greater than or equal to the idle time threshold T over And when the dynamic factor is generated, the data bit data of all the dynamic data segments acquired by the communication interface are sequenced and integrated according to the marking bit data of the dynamic data segments, and the dynamic factor is submitted to the PC end.
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