CN111565048B - Logic control system of successive approximation type ADC - Google Patents
Logic control system of successive approximation type ADC Download PDFInfo
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- CN111565048B CN111565048B CN202010545499.XA CN202010545499A CN111565048B CN 111565048 B CN111565048 B CN 111565048B CN 202010545499 A CN202010545499 A CN 202010545499A CN 111565048 B CN111565048 B CN 111565048B
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Abstract
A logic control system of a successive approximation type ADC comprises a sampling control module (102), a conversion control module (103) and a data generation module (104); the conversion start signal ADST and the clock signal CLK are input to a logic control system (101) of the successive approximation ADC of the present invention, and ADST is kept high during the whole conversion process; the sampling control module (102) outputs SAMPLE to control the sampling of the DAC module (105), the DAC module (105) SAMPLEs when the SAMPLE is 1, and the sampling control module (102) outputs PULSE with one clock width to be connected to the conversion control module (103); the output B [11:0] of the conversion control module (103) is connected to the data generation module (104), and the output VALID signal is a data conversion completion mark; the data generation module (104) outputs DA [11:0] and is connected to the DAC module (105), the analog voltage output by the DAC and the reference voltage VREF are subjected to successive approximation comparison, the data generation module (104) records the output result CMP of the comparator (106) of the bitwise comparison, and AD [11:0] data closest to the input voltage is obtained.
Description
Technical Field
The invention relates to the technical field of successive approximation type ADC (analog-to-digital converter), in particular to a logic control system of the successive approximation type ADC.
Background
With the development of electronic information technology, digital circuit systems are widely used in various disciplines and daily life. The signals processed by the digital circuit system are digital signals, and the signals of humidity, heat, pressure, sound, light, magnetism and the like in the nature are analog signals. Analog-to-Digital Converter (ADC) converters are required to convert these Analog signals to digital signals for processing by digital circuitry. Successive approximation ADC becomes the mainstream of analog-to-digital converter with its comprehensive advantages in accuracy, speed and power consumption. The successive approximation type ADC samples the input voltage according to the principle of a binary method, and performs bit-by-bit comparison to obtain the DAC output voltage closest to the input voltage. In the prior art, the ADC is configured to be started by software, and fixed sampling time is adopted, so that when the ADC is interrupted in the conversion process, conversion junction errors can be caused.
Disclosure of Invention
The invention aims to solve the technical problems that: the invention realizes a simple and effective logic control system of the successive approximation type ADC, starts sampling of input signals through the enabling of ADC conversion, and can flexibly set sampling time. After the sampling is finished, the data bits of the ADC are set successively, the result of comparison of each comparator is combined and output to the DAC module, and the finally compared ADC data are output and kept until the ADC conversion is closed by the digital circuit system, so that the converted data are effectively collected.
To solve the above technical problems, the present invention proposes the following technical solutions: a logic control system of a successive approximation type ADC comprises a sampling control module (102), a conversion control module (103) and a data generation module (104);
the conversion start signal ADST and the clock signal CLK are input to a logic control system (101) of the successive approximation ADC of the present invention, and ADST is kept high during the whole conversion process;
the sampling control module (102) outputs SAMPLE to control the sampling of the DAC module (105), the DAC module (105) SAMPLEs when the SAMPLE is 1, and the sampling control module (102) outputs PULSE with one clock width to be connected to the conversion control module (103);
the output B [11:0] of the conversion control module (103) is connected to the data generation module (104), and the output VALID signal is a data conversion completion mark;
the data generation module (104) outputs DA [11:0] and is connected to the DAC module (105), the analog voltage output by the DAC and the reference voltage VREF are subjected to successive approximation comparison, the data generation module (104) records the output result CMP of the comparator (106) of the bitwise comparison, and AD [11:0] data closest to the input voltage is obtained.
A further limitation of the above technical solution is that the sampling control module (102) obtains an ADSTB signal from the ADST signal through the inverter (202); an ADSTB controls a counter (201), and when the ADSTB is 1, the counter (201) does not count, and the output signal SRST is 1; when the ADC is started and converted, the ADSTB is 0, a counter (201) starts to count, when the number of CLK clocks corresponding to the SH [5:0] register is counted, SRST becomes 0 and is kept, and only the ADSTB can reset SRST; a trigger (203) in the sampling control module (102), wherein a reset end is connected to the SRST, a clock end is connected to the CLK signal, and a data input end D of the trigger (203) is connected with a negative output end; the positive output Q of the flip-flop (203) acts as one input of a NOR gate (204), the other input of the NOR gate (204) being connected to the output of the NOR gate (205); one input of the nor gate (205) is connected to the output of the nor gate (204), and the other input is connected to the SRST; the output of the nor gate (204) is connected to the input terminal D of the flip-flop (206), the clock terminal of the flip-flop (206) is connected to CLK, and the reset terminal is connected to SRST; the positive end output Q of the trigger (206) is a signal PULSE and is connected to the conversion control module (103); the PULSE signal is a high-level PULSE signal with the width of one CLK clock period after the sampling is finished; PULSE is also one input of nor gate (207), the other input of nor gate (207) being connected to the output of nor gate (208); one input of the nor gate (208) is connected to the output of the nor gate (207), and the other input is connected to the adsbs; the output of the NOR gate (207) is connected to the inverter (202), the output of the inverter (202) and the ADSTB signal are input into the NOR gate (210) to obtain a SAMPLE signal, and the SAMPLE signal is output to the DAC module (105) to control the sampling of the SAMPLE signal; when the transition is turned on, ADST changes from 0 to 1 and SAMPLE changes from low to high, the high level time of the SAMPLE signal remains SH [5:0] +2 clock cycles; when the SAMPLE signal is 1, the DAC module (105) SAMPLEs the input voltage.
The technical scheme is further defined in that the trigger (301) of the conversion control module (103) inputs a PULSE signal, the reset end of the trigger is connected to the ADSTB, the clock end is connected to the CLK, and the positive output end is B11; b11 is used as the data input of the trigger (302), the reset end is connected to ADSTB, the clock end is connected to CLK, and the positive output end is B10; b10 is used as the input signal of the next stage trigger, and the output signal of the previous stage is used as the input signal of the next stage trigger in turn until the trigger 304 outputs B0, thus B11:0 is obtained in turn and is output to the data generating module 104; b0 is used as an input of the trigger (305), the positive end output of the trigger (305) is one input end of the NOR gate (307), and the other input end of the NOR gate (307) is connected to the output of the NOR gate (308); one input of the nor gate (308) is connected to the output of the nor gate (307) and the other input is connected to the adsbs; the output of the inverter (202) is passed through the inverter (202) to convert the completion signal VALID for the ADC.
The technical scheme is further defined in that the data generating module (104), the clock signal CLK is connected with the NOR gate (402) through the inverter (202) and B [11:0], the output of the NOR gate (402) is respectively used as the clock signals corresponding to the high and low bits of the 12 triggers (403); the input of the trigger (403) is the output result CMP of the comparator (106) of the ADC, the reset end of the trigger (403) is connected to the ADSTB, and the output end of the trigger (403) is AD [11:0]; AD [11:0] and B [11:0] are connected to two inputs of the NOR gate (404), and the output of the NOR gate (404) is the signal DA [11:0] as comparison data of the DAC.
Compared with the prior art, the invention has the following beneficial effects: the logic control system of the successive approximation type ADC is simple and effective, sampling of an input signal is started through the enabling of ADC conversion, and sampling time can be flexibly set.
Drawings
Fig. 1 is a block diagram of a logic control system of a successive approximation ADC of the present invention.
Fig. 2 is a circuit configuration diagram of the sampling control module.
Fig. 3 is a circuit configuration diagram of the conversion control module.
Fig. 4 is a circuit configuration diagram of the data generation module.
Description of the embodiments
Fig. 1 is a block diagram of a logic control system of the present invention, and a logic control system 101 of a successive approximation ADC of the present invention includes a sampling control module 102, a conversion control module 103, and a data generation module 104.
The conversion start signal ADST and the clock signal CLK are input to the logic control system 101 of the successive approximation ADC of the present invention, and ADST must be kept high throughout the conversion process.
The output SAMPLE of the SAMPLE control module 102 controls the sampling of the DAC module 105, and when SAMPLE is 1, the DAC module 105 SAMPLEs. The output PULSE of the sampling control block 102 is a high level PULSE of one clock width and is connected to the conversion control block 103.
The output B [11:0] of the conversion control module 103 is connected to the data generation module 104, which outputs a VALID signal as a data conversion completion flag.
The output DA [11:0] of the data generation module 104 is connected to the DAC module 105, the output analog voltage of the DAC is subjected to successive approximation comparison with the reference voltage VREF, and the data generation module 104 records the output result CMP of the comparator 106 subjected to the bitwise comparison, so that the AD [11:0] data closest to the input voltage is obtained.
The circuit configuration of the sampling control module 102 is shown in fig. 2. The adst signal is provided to the ADSTB signal via inverter 202. When the ADSTB controls the counter 201 and the ADSTB is 1, the counter 201 does not count, and the output signal SRST is 1. When ADSTB is 0 when ADC is turned on, counter 201 begins counting, and when the number of CLK clocks corresponding to SH [5:0] registers is counted, SRST becomes 0 and remains, only ADSTB can reset SRST. The flip-flop 203 in the sampling control block 102 has its reset terminal connected to SRST and its clock terminal connected to CLK signal, and its data input terminal D of the flip-flop 203 is connected to the negative output terminal. The positive output Q of the flip-flop 203 is provided as one input of a nor gate 204, the other input of the nor gate 204 being connected to the output of a nor gate 205. One input of nor gate 205 is connected to the output of nor gate 204 and the other input is connected to SRST. The output of nor gate 204 is coupled to input D of flip-flop 206, the clock terminal of flip-flop 206 is coupled to CLK, and the reset terminal is coupled to SRST. The positive output Q of the flip-flop 206 is the signal PULSE and is connected to the conversion control module 103. The PULSE signal is a high level PULSE signal generated by one CLK clock period width after sampling is completed. PULSE is also an input of nor gate 207, the other input of nor gate 207 being connected to the output of nor gate 208. NOR gate 208 has one input connected to the output of NOR gate 207 and another input connected to the ADSTB. The output of nor gate 207 is coupled to inverter 202 and the output of inverter 202 is input to nor gate 210 with the ADSTB signal to provide a SAMPLE signal that is output to DAC module 105 for sampling purposes. When the transition is turned on, ADST goes from 0 to 1 and SAMPLE goes from low to high, the high time of the SAMPLE signal remains SH [5:0] +2 clock cycles. When the SAMPLE signal is 1, DAC module 105 SAMPLEs the input voltage.
As shown in fig. 3, the flip-flop 301 of the switch control module 103 is input as a PULSE signal, its reset terminal is connected to the adsbs, its clock terminal is connected to CLK, and its positive output terminal is B11. B11 is used as the data input to flip-flop 302, and is also connected to ADSTB at its reset terminal, CLK at its clock terminal, and B10 at its positive output terminal. B10 is used as the input signal of the next stage flip-flop, and the output signal of the previous stage is used as the input signal of the next stage flip-flop in turn until the flip-flop 304 outputs B0, thereby obtaining B11:0 in turn, and outputting to the data generation module 104. B0 is taken as input to the flip-flop 305, the positive output of the flip-flop 305 being one input of the NOR gate 307, the other input of the NOR gate 307 being connected to the output of the NOR gate 308. NOR gate 308 has one input connected to the output of NOR gate 307 and another input connected to the ADSTB. The output of the inverter 202 is the ADC complete signal VALID through the inverter 202.
As shown in FIG. 4, the data generating module 104, the clock signal CLK is coupled to the NOR gate 402 through the inverter 202 and B [11:0], and the outputs of the NOR gate 402 are respectively used as the clock signals corresponding to the high and low bits of the 12 flip-flops 403. The inputs of the flip-flop 403 are the result CMP output by the ADC comparator 106, the reset terminals of the flip-flop 403 are all connected to the ADSTB, and the output terminals of the flip-flop 403 are AD [11:0]. AD [11:0] and B [11:0] are connected to two inputs of NOR gate 404, and the output of NOR gate 404 is signal DA [11:0] as the comparison data of the DAC.
In the logic control system 101 of the successive approximation ADC of the present invention, when the VALID signal is 1, AD [11:0] at this time is the analog-to-digital conversion result, and VALID and AD [11:0] continue to be kept until the data is taken away, ADST is set to 0, and VALID and AD [11:0] are cleared.
Claims (3)
1. The logic control system of the successive approximation type ADC is characterized by comprising a sampling control module 102, a conversion control module 103 and a data generation module 104;
the conversion start signal ADST and the clock signal CLK are input to the logic control system 101 of the successive approximation ADC of the present invention, and ADST must be kept high throughout the conversion process;
the sampling control module 102 includes a counter 201, an inverter 202, a flip-flop 203, a nor gate 204, a nor gate 205, a flip-flop 206, a nor gate 207, a nor gate 208, and a nor gate 210, and the adst signal obtains an ADSTB signal through the inverter 202; when ADSTB controls counter 201 and ADSTB is 1, counter 201 does not count, and its output signal SRST is 1; when ADSTB is 0 when ADC is turned on, counter 201 starts counting, SRST becomes 0 and is maintained when the number of CLK clocks corresponding to SH [5:0] registers is counted, and only ADSTB can reset SRST; a trigger 203 in the sampling control module 102, a reset terminal is connected to the SRST, a clock terminal is connected to the CLK signal, and a data input terminal D of the trigger 203 is connected to a negative output terminal; the positive output Q of the flip-flop 203 is taken as one input of the nor gate 204, the other input of the nor gate 204 being connected to the output of the nor gate 205; NOR gate 205 has one input connected to the output of NOR gate 204 and another input connected to SRST; the output of nor gate 204 is connected to input D of flip-flop 206, the clock terminal of flip-flop 206 is connected to CLK, and the reset terminal is connected to SRST; the positive end output Q of the trigger 206 is a signal PULSE and is connected to the conversion control module 103; the PULSE signal is a high-level PULSE signal with the width of one CLK clock period after the sampling is finished; PULSE is also an input of nor gate 207, the other input of nor gate 207 being connected to the output of nor gate 208; NOR gate 208 has one input connected to the output of NOR gate 207 and another input connected to ADSTB; the output of the nor gate 207 is connected to the inverter 202, and the output of the inverter 202 and the ADSTB signal are input to the nor gate 210 to obtain a SAMPLE signal, which is output to the DAC module 105 to control sampling thereof; when the transition is turned on, ADST changes from 0 to 1 and SAMPLE changes from low to high, the high level time of the SAMPLE signal remains SH [5:0] +2 clock cycles; when the SAMPLE signal is 1, DAC module 105 SAMPLEs the input voltage;
the output SAMPLE of the sampling control module 102 controls the sampling of the DAC module 105, and when SAMPLE is 1, the DAC module 105 SAMPLEs, and the output PULSE of the sampling control module 102 is a high-level PULSE with one clock width and is connected to the conversion control module 103;
the output B [11:0] of the conversion control module 103 is connected to the data generation module 104, and the output VALID signal is a data conversion completion mark;
the output DA [11:0] of the data generation module 104 is connected to the DAC module 105, the output analog voltage of the DAC is subjected to successive approximation comparison with the reference voltage VREF, and the data generation module 104 records the output result CMP of the comparator 106 subjected to the bitwise comparison, so that the AD [11:0] data closest to the input voltage is obtained.
2. The logic control system of a successive approximation ADC of claim 1 wherein the flip-flop 301 input of the conversion control module 103 is a PULSE signal, its reset terminal is connected to the ADSTB, its clock terminal is connected to the CLK, and its positive output terminal is B11; b11 is used as the data input of the flip-flop 302, and the reset end is connected to the ADSTB, the clock end is connected to CLK, and the positive output end is B10; b10 is used as the input signal of the next stage trigger, and the output signal of the previous stage is used as the input signal of the next stage trigger in turn until the trigger 304 outputs B0, thus obtaining B11:0 in turn, and outputting to the data generation module 104; b0 is taken as an input of the flip-flop 305, the positive output of the flip-flop 305 is one input of the NOR gate 307, and the other input of the NOR gate 307 is connected to the output of the NOR gate 308; NOR gate 308 has one input connected to the output of NOR gate 307 and another input connected to the ADSTB; the output of the inverter 202 is the ADC complete signal VALID via the first and second inverters 202.
3. The logic control system of a successive approximation ADC of claim 1 wherein the data generating module 104 comprises a nor gate 402 and flip-flops 403, the clock signal CLK is coupled to the nor gate 402 via the inverter 202 and B [11:0], and the outputs of the nor gate 402 are respectively used as the clock signals corresponding to the high and low bits of the 12 flip-flops 403; the input of the trigger 403 is the result CMP output by the comparator 106 of the ADC, the reset end of the trigger 403 is connected to the ADSTB, and the output end of the trigger 403 is AD [11:0]; AD [11:0] and B [11:0] are connected to two inputs of NOR gate 404, and the output of NOR gate 404 is signal DA [11:0] as the comparison data of the DAC.
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| US8754800B2 (en) * | 2012-09-29 | 2014-06-17 | Intel Corporation | Methods and arrangements for high-speed analog-to-digital conversion |
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