KR19980030755A - Sequential Scan Converter of Projection Image Display System - Google Patents

Abstract

According to the present invention, in the projection type image display system using the AMA element, the interlaced image signal is converted into a sequential scan type signal format to reproduce the image, thereby reducing the flicker attenuation and vertical resolution generated in the projection image. Provided is a sequential scan conversion device of a projection type image display system that can prevent degradation.

Accordingly, the present invention provides data conversion means 10 for synchronously sampling and digitally converting an interlaced video signal at the sampling rate of the first clock signal CLK1, and the first clock signal CLK1. First memory means (12) for storing the digitally converted image data synchronously at a recording speed and for reading the image data stored synchronously at a read speed by a second clock signal (CLK2) in a double speed conversion state; Second memory means 14 for delaying and storing the video signal in the double speed conversion state from the first memory means 12 by one field, and a first clock signal CLK1 synchronized with a synchronization signal separated from the video signal; First clock generating means (16) for generating a second clock generating means (16) for generating a second clock signal (CLK2) having a faster clock speed than the first clock signal (CLK1) so that the 18), the first memo Switching selection of the double-speed converted image data of one field read from the means 12 and the double-converted image data of the other field delayed by one field from the second memory means 14 by the select control signal SEL A multiplexer means 20 for converting into a sequential scan form, data inverse converting means 22 for converting image data converted into a sequential scan form through the multiplexer means 20 into an analog signal form, and horizontal in the video signal The multiplexer means 20 includes a control means 26 for generating a select control signal SEL based on a result of counting a period during which the synchronization signal H SYNC is generated.

Description

Sequential Scan Converter of Projection Image Display System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential scan conversion apparatus of a projection image display system, and more particularly, to sequentially scan interlaced image signals in a projection image display system which reproduces an image by driving a pixel through an AMA element. The present invention relates to a sequential scan converting apparatus of a projection type image display system which converts to a non-interlace format to enable high quality image reproduction.

As is well known, the image display system is roughly divided into a direct view type image display system employing a CRT device and a projection type image display system employing an LCD device, among which a direct view image display system has a RGB fluorescent mark on a fluorescent panel. Since a plurality of electron beams are formed at the RGB fluorescent point to form a color image on the CRT, high quality is ensured, but the screen is limited in size and the manufacturing process is complicated. .

In addition, in the case of the LCD device employed in the projection type image display system, the image to be reproduced is displayed by applying a voltage corresponding to the image signal from the uniform arrangement of the liquid crystal as the liquid crystal driving voltage to adjust the arrangement direction of the liquid crystal by the polarizing plate. Because of this, relatively light weight can be reduced, but there is a disadvantage in that the light loss due to the polarizing plate for adjusting the amount of light emission for the entire incident light is increased.

In view of this, in recent years, a projection type image display system using AMA (Actuated Mirror Array) has been proposed and adopted to reproduce color images. In the projection type image display system using the AMA, the AMA is arranged in one dimension. Is a two-dimensional structure representing an image having an array of MxN pixels by projecting Mx1 light beams or by projecting MxN light beams using a scanning mirror.

In such a projection image display system, an AMA member having a plurality of AMAs is driven by introducing a television broadcast signal having a broadcasting method such as an NTSC system from an external source or a video signal reproduced from an image recording medium such as a video tape or a video disc. The image is formed on the screen.

The video signal from the outside is composed of two fields per one screen (one frame), and is composed of a video signal in which interlaced scanning of scan lines constituting each field is performed on a CRT (Cathode Ray Tube) screen. The scanning line of the 263 scan period (H) is scanned on the CRT screen as an odd field, but a part of the scan line of the 263 scanning period is deleted by 1/2 the scanning period (1 / 2H) by the vertical blanking period. It is received and erased by oblique scanning at the bottom of the CRT screen, and scan lines of 283 to 525 scanning periods (H) except the vertical blanking periods containing vertical synchronization signals of about 21 scanning periods (H) are excellent fields (Even). As a field), an interlaced scan is performed on the scanned CRT screen, but a part of the scanning line of the 283 scanning period is received by half scanning period (1 / 2H) by the vertical blanking period and is inclined at the top of the CRT screen. Deleted by injection.

Accordingly, the projection type image display system adopts such an interlaced image signal consisting of two fields and converts the speed in order to reproduce the image normally on the projection screen. FIG. 1 illustrates the interlaced scanning method of the conventional projection type image display system. Fig. 1 is a block diagram showing a double speed conversion device for double speed conversion of a video signal.

According to the structure of the conventional double speed converting apparatus shown in FIG. 1, the first clock signal CLK1 generated in synchronization with a synchronous signal separated from an image signal is applied as a sampling clock and interlaced at a sampling rate synchronized with the sampling clock. An analog-to-digital converter (2) for sampling and digitally converting a video signal having a scanning method and the first clock signal CLK1 is applied as a recording clock to synchronize the digitally converted video data with the recording clock. In addition to storing at a recording speed, a read speed in which a second clock signal CLK2 having a clock speed faster than that of the first clock signal CLK1 is applied as a read clock and the stored image data is synchronized with the read clock. And a DAC 6 for converting the image data read out from the line memory 4 into an analog signal in synchronism with the second clock signal CLK2. -Analog Converter).

In the double speed conversion device in the projection type image display system composed of such components, the clock pulse width of the first clock signal CLK1 supplied to the ADC 2 as a sampling clock and supplied as a write clock to the line memory 4 is applied. And a second clock signal CLK2, which has a clock pulse width (i.e. twice the number of clock pulses) of 1/2, for example, to have a faster clock speed, is supplied to the line memory 4 as a read clock. At the same time, by supplying the DAC 6 as a synchronous clock, as shown in Fig. 2, the odd-numbered field consisting of n, n + 2, n + 4, ..., n + 524 and n + 1, In the case of having an even field consisting of n + 3, n + 5, ..., n + 525, the double speed conversion result for the radix field is shown as n, n, n + 2, n + 2, ... , The result of the double speed conversion for the even field is shown as n + 1, n + 1, n + 3, n + 3, ...

Accordingly, when such a double-speed converted video signal is implemented as a single screen consisting of one frame, as shown in FIG. 3, as the double-speed converted radix field and even field are overlapped and scanned, n / n + 1, n / n + 1, n + 2 / n + 3, n + 2 / n + 3, ...

However, when the image signal converted from the interlaced scanning image signal by the double speed conversion device of the projection image display system is projected on the screen, the image scanning lines of the radix field and the even field are overlapped with each other to reproduce the image vertically. As the degradation of the resolution appears, the degradation of the image quality as a whole is caused.

Accordingly, the present invention has been made in view of the above circumstances, and the projection is performed by converting an interlaced image signal into a sequential scanning signal format and reproducing the image in a projection type image display system that reproduces an image using an AMA element. It is an object of the present invention to provide a sequential scan converting apparatus of a projection type image display system which can prevent attenuation of flicker and degradation of vertical resolution generated in an image.

According to the sequential scanning conversion apparatus of the projection type image display system according to the present invention, the data conversion means for sampling and digitally converting an interlaced scanning video signal synchronously with the sampling rate by the first clock signal. And a first image storing the digitally converted image data synchronously with the recording speed of the first clock signal and reading the image data stored synchronously with the reading speed of the second clock signal in a double speed conversion state. Memory means, second memory means for delaying and storing a video signal in a double speed conversion state from the first memory means by one field, and a first clock for generating a first clock signal synchronized with a synchronization signal separated from the video signal Generating means, generating a second clock signal having a faster clock speed than the first clock signal to enable double-speed conversion of the video signal; Switching selection of the double-speed conversion image data of one field read from the second clock generating means, the first memory means and the double-converted image data of the other field delayed by one field from the second memory means by the select control signal. A multiplexer means for converting the progressive data into a sequential scan form, a data inverse converting means for converting the image data converted into the sequential scan form through the multiplexer means into an analog signal, and counting a period during which a horizontal synchronous signal is generated from the video signal. A sequential scan conversion apparatus of a projection type image display system comprising a control means for generating a select control signal on the multiplexer means based on a result.

According to the present invention configured as described above, in the projection type image display system which reproduces the projection image on the screen through the pixel drive of the AMA panel consisting of a plurality of AMA elements, the double speed conversion for each field is performed for the interlaced scanning image signal. After performing the data, the field of one side is delayed by field unit so that the image scanning line of the other side field and the field of the field delayed side of the double-speed converted image data can be switched in a sequential scanning manner. do.

1 is a block diagram showing a double speed conversion device for double speed converting an interlaced scanning video signal in a conventional projection type image display system;

FIG. 2 is a timing chart illustrating a state in which the interlaced scanning video signal is double speed converted according to the double speed conversion function of FIG. 1;

3 is a diagram illustrating an example in which a video signal is scanned on the screen according to the speed conversion state of the video signal shown in FIG. 2;

4 is a blur configuration diagram showing a sequential scan conversion apparatus of a projection image display system according to the present invention;

5 is a timing chart showing a state in which an interlaced scanning video signal is converted into a sequential scanning method according to a preferred embodiment of the present invention;

6 is a diagram illustrating a state in which a format of a video signal converted by a sequential scanning method is implemented by two fields according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: ADC, 12: line memory,

14: field memory, 16: 1 PLC circuit portion,

18: second PLL circuit section, 20: multiplexer,

22: DAC, 24: Counter,

26: Microcomputer.

Hereinafter, the present invention configured as described above will be described in detail with reference to the accompanying drawings.

4 is a blur configuration diagram showing a sequential scan converting apparatus of a projection type image display system according to the present invention. In the apparatus of the present invention, reference numeral 10 denotes an interlaced scanning video signal consisting of two fields per frame. An ADC for sampling and digitally converting at a sampling rate synchronized with the first clock signal CLK1 from the first PLL circuit unit 16 is shown. 12 denotes a first write enable signal W ENA1 from the microcomputer 26, which will be described later. Recording operation is enabled to record and store the digitally converted image data in image scan line units at a recording speed synchronized with the first clock signal CLK1, and from the microcomputer 26 to be described later. The read operation is enabled by the first read enable signal R ENA1, and the image data stored at the read speed synchronized with the second clock signal CLK2 from the second PLL circuit unit 18 described later is read. It represents a line memory which takes a dock in the conversion state.

Further, reference numeral 14 denotes a second clock signal CLK2 from the second PLL circuit section 18 described later, since the recording operation is enabled by the second write enable signal W ENA2 from the microcomputer 26 described later. A second read enable signal (R ENA2) from the microcomputer 26, which will be described later, stores the image data through the line memory 12 in units of one field at a recording speed synchronous to the data field, and delays data by one field. Indicates a field memory that reads the image data of a predetermined field stored with the read operation enabled at a read speed synchronized with the second clock signal CLK2.

Further, reference numeral 16 denotes a first clock signal by PLL operation of a synchronization signal separated from the video signal by an operation enabled by an enable signal ENA from the microcomputer 26 to be described later with a predetermined division ratio. A first PLL circuit portion generating CLK1, 18 denotes a first synchronous signal separated from the video signal after operation is enabled by an enable signal ENA from the microcomputer 26 described later; A second PLL circuit portion for generating a second clock signal CLK2 by performing PLL operation at a division ratio having a 1/2 clock pulse period with respect to CLK1.

Reference numeral 20 is applied to the first input terminal A to receive the image data read out from the line memory 12 in the double speed conversion state, and to the second input terminal B from the field memory 14 to 1. Switching selection of the first input terminal A or the second input terminal B so that the image data delayed by the field is applied and converted into a sequential scanning method by the select control signal SEL from the microcomputer 26 described later. 22 shows a DAC for converting the image data converted in the sequential scanning method through the multiplexer 20 into an analog signal in synchronism with the second clock signal CLK2.

Reference numeral 24 denotes a counter that counts a predetermined clock signal (i.e., a clock signal having 640 clock pulses) and is reset by the horizontal synchronous signal H SYNC of the video signal.

Further, reference numeral 26 generates an enable signal ENA for enabling the first and second PLL circuit units 16 and 18, and write / read of the line memory 12 and the field memory 14, respectively. Generating first and second write enable signals W ENA1 and W ENA2 and first and second read enable signals R ENA1 and R ENA2 for enabling the operation; A microcomputer for generating a select control signal SEL for converting the video signal converted into the multiplexer 20 into a sequential scanning method based on a counting signal.

Here, the first write enable signal W ENA1 and the first read enable signal R ENA1 generated by the microcomputer 26 are synchronized with the horizontal scan period of each image scan line of the interlaced video signal. The second write enable signal W ENA2 and the second read enable signal R ENA2 are generated with a period synchronized with the vertical scanning period by each field of the video signal.

Then, the microcomputer 26 generates a select control signal SEL in which the signal level is inverted every half of the period by dividing the interval between the syringes of one video scanning line of the video signal by the counting signal from the counter 24. However, in the preceding 1/2 period, the multiplexer 20 is switched to the second input terminal B side and the other field for the image data of the double speed conversion state delayed by the field unit through the field memory 14 ( That is, the image scanning line of the radix field) is selected, and the multiplexer 20 is switched to the first input terminal A side in a half of the following period so that the double speed conversion of the one side from the line memory 12 is performed. Control to select an image scan line according to a field (ie, even field).

Next, the operation of the present invention made as described above will be described in detail with reference to the accompanying drawings.

First, in the case of reproducing an interlaced scanning video signal such as an NTSC system through a projection type image display system employing an AMA element, the ADC 10 outputs the interlaced scanning video signal from the first PLL circuit unit 16. The first clock signal CLK1 is sampled at a synchronous sampling rate and digitally converted. The write operation of the line memory 12 is enabled by the first write enable signal W ENA1 from the microcomputer 26. In addition, the digitally converted image data is recorded and stored in the unit of image scanning line at the recording speed synchronized with the first clock signal CLK1 from the first PLL circuit unit 16, and the first data from the microcomputer 26 is stored. The read operation is enabled by the single read enable signal R ENA1 and then read at a read speed synchronous with the second clock signal CLK2 from the second PLL circuit section 18, as shown in FIG. As the original video signal is n, n + 2, n If a radix field such as +4, n + 6, ... and an even field such as n + 1, n + 3, n + 5, n + 7, ..., the radix field is n, n, n + 2, n + 2, n + 4, n + 4, n + 6, n + 6, ... double-speed conversion, and even field is n + 1, n + 1, n + 3, n + 3 , n + 5, n + 5, n + 7, n + 7, ...

Next, in the field memory 14, the write operation is enabled by the second write enable signal W ENA2 from the microcomputer 26, and the video data converted by the line memory 12 is doubled. The data is delayed by one field by recording and storing at a recording speed synchronized with the second clock signal CLK2 from the second PLL circuit unit 18, and the second read enable signal R from the microcomputer 26. The read operation is enabled by the ENA2, and the image data stored at the read speed synchronized with the second clock signal CLK2 is read.

At this time, the microcomputer 26 resets the counting operation by the horizontal synchronizing signal H SYNC by the counter 24, and based on the counting signal according to the counting signal according to the counting result of the clock signal CLK. By supplying the multiplexer 20 with a select control signal SEL for dividing the signal level by half of one image scanning line of the signal, the multiplexer 20 is connected to the second input terminal in the preceding 1/2 period. (B) is selected to switch so that the image scan line of the radix field delayed by one field by the field memory 14 passes, and the first input terminal A is switched to select the second input period in the following 1/2 period. The image scanning line corresponding to the even field of the image data double speed converted from the line memory 12 is passed.

As a result, the image data analog converted by the DAC 22 is n, n + 1, n + 2, n + 3, n + 4, n + 5, n + 6, n as shown in FIG. As shown in FIG. 6, the video signal converted to the sequential scanning method as shown in FIG. 6 is converted to the sequential scanning method in the same manner as the radix field and the even field as shown in FIG. Scanning is superimposed on one another such as n + 1 / n + 1, n + 2 / n + 2, n + 3 / n + 3, n + 4 / n + 4, n + 5 / n + 5, ...

The present invention having the above-described embodiments can be implemented in various ways without departing from the gist of the invention, for example, for converting an interlaced scanning video signal into a sequential scanning method. Although the technology has been described as being limited to a projection type image display system employing an AMA element, it is, of course, applicable to a direct view type image display system such as a television.

According to the present invention made as described above, by converting the interlaced image signal to the sequential scanning method in the projection type image display system to reproduce the image, it is possible to reduce the flicker compared to the conventional double speed conversion method and vertical This has the advantage that the resolution can be improved.

Claims (2)

Data conversion means (10) for digitally sampling the interlaced scanning video signal synchronously at a sampling rate by the first clock signal (CLK1); In addition to storing the digitally converted image data synchronously with the recording speed of the first clock signal CLK1, the image data stored synchronously with the reading speed of the second clock signal CLK2 is converted into a double speed conversion state. First memory means 12 for reading out, Second memory means 14 for delaying and storing the video signal in the double speed conversion state from the first memory means 12 by one field; First clock generation means (16) for generating a first clock signal (CLK1) in synchronization with a synchronization signal separated from the video signal; Second clock generation means (18) for generating a second clock signal (CLK2) having a faster clock speed than the first clock signal (CLK1) so that the video signal can be double-speed converted; The double speed converted video data of one field read from the first memory means 12 and the double speed converted video data of another field delayed by one field from the second memory means 14 are added to the select control signal SEL. Multiplexer means (20) for switching to a sequential scan type by switching selection; Data inverse conversion means (22) for converting image data converted into a sequential scan form through the multiplexer means (20) into an analog signal form; And a control means (26) for generating a select control signal (SEL) in the multiplexer means (20) based on a result of counting a period during which the horizontal synchronization signal (H SYNC) is generated from the video signal. A sequential scan conversion device of a projection type image display system. The multiplexer means (20) according to claim 1, wherein the control means (26) controls the multiplexer means (20) in a second half of the preceding half of the one video scanning period between the horizontal synchronization signals (H SYNC) of the video signal. Switching switching the image scanning line of the other field of the image data delayed by one field from the memory means 14, and converting the double-speed converted image data from the first memory means 12 And a select control signal (SEL) for controlling switching of the image scanning line.