CN117632815A

CN117632815A - Circuit board compatible with signal reconstruction chip and enhancement chip and electronic equipment

Info

Publication number: CN117632815A
Application number: CN202311412042.1A
Authority: CN
Inventors: 谢超凡
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-10-27
Filing date: 2023-10-27
Publication date: 2024-03-01

Abstract

The invention provides a circuit board compatible with a signal reconstruction chip and a signal enhancement chip and electronic equipment, and relates to the field of integrated circuits. The complex programmable logic device is respectively connected with the configuration module and the selection module and is used for generating a voltage signal and a selection signal according to the mode signal sent by the configuration module. The power module is respectively connected with the complex programmable logic device and the chip port and is used for generating different voltages according to the voltage signals and supplying the different voltages to the chip port; the selection module is connected with the chip port and the read-only memory and is used for determining the connection relation between the pins of the chip port and the pins of the read-only memory according to the selection signals. The invention is compatible with the signal reconstruction chip and the signal enhancement chip, so that whether the signal reconstruction chip or the signal enhancement chip is arranged on the circuit board can be determined according to actual use requirements, the cost is reduced, the advantages of the signal reconstruction chip and the signal enhancement chip are achieved, the defects of the signal reconstruction chip and the signal enhancement chip are overcome to a certain extent, and the signal reconstruction chip and the signal enhancement chip are high in practicability.

Description

Circuit board compatible with signal reconstruction chip and enhancement chip and electronic equipment

Technical Field

The invention relates to the field of integrated circuits, in particular to a circuit board compatible with a signal reconstruction chip and a signal enhancement chip and electronic equipment.

Background

Currently, PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) devices have become an indispensable component in servers, where the PCIe devices are related to performance, computation, functions, etc. of the servers, and related to computation, storage, network, etc. of the servers, but there is a non-negligible signal attenuation problem.

The scheme for solving the signal attenuation problem is that PCIe signal enhancement chips are added in PCIe links to reduce loss and ensure equipment performance. There are two main types of PCIe signal enhancement chips, namely PCIe driver chips and PCIe timer chips. Because the two are different in structure, the two are not compatible in design, each chip is a single board card, the cost is high, and the two chips cannot have the advantages and overcome the disadvantages.

Disclosure of Invention

In view of the above problems, the present invention provides a circuit board and an electronic device compatible with a signal reconstruction chip and a signal enhancement chip.

The embodiment of the invention provides a circuit board compatible with a signal reconstruction chip and a signal enhancement chip, which comprises: the device comprises a power module, a read-only memory, a complex programmable logic device, a chip port, a selection module and a configuration module;

the complex programmable logic device is respectively connected with the configuration module and the selection module and is used for generating a voltage signal and a selection signal according to the mode signal sent by the configuration module;

the power module is respectively connected with the complex programmable logic device and the chip port, and is used for generating different voltages according to the voltage signals and supplying the different voltages to the chip port;

the selection module is connected with the chip port and the read-only memory and is used for determining the connection relation between the pins of the chip port and the pins of the read-only memory according to the selection signals;

the chip port is configured to be a layout signal reconstruction chip or a layout signal enhancement chip, and receives the configuration information sent by the configuration module and transmits the configuration information to the layout chip.

Optionally, the configuration module includes: a first configuration unit or a second configuration unit;

when the signal reconstruction chip is arranged at the chip port, the configuration module determines the first configuration unit, and the first configuration unit is used for sending a first mode signal to the complex programmable logic device;

when the signal enhancement chip is arranged at the chip port, the configuration module determines that the signal enhancement chip is the second configuration unit, and the second configuration unit is used for sending a second mode signal to the complex programmable logic device.

Optionally, when the configuration module determines that the configuration module is the first configuration unit, the first mode signal is generated by the configuration module through a pull-down process;

when the configuration module determines that the configuration module is the second configuration unit, the second mode signal is generated by the configuration module through a pull-up process.

Optionally, the circuit board further includes: a pluggable interface;

the configuration module is respectively connected with the complex programmable logic device and the chip port through the pluggable interface.

Optionally, when the signal reconstruction chip is disposed at the chip port, the complex programmable logic device generates a first voltage signal according to the first mode signal, where the first voltage signal is used to enable the power module to generate a first voltage, and the first voltage is a required voltage of the signal reconstruction chip;

when the signal enhancement chip is arranged at the chip port, the complex programmable logic device generates a second voltage signal according to the second mode signal, wherein the second voltage signal is used for enabling the power supply module to generate a second voltage which is the required voltage of the signal enhancement chip;

when the signal reconstruction chip is arranged at the chip port, the complex programmable logic device generates the first selection signal according to the first mode signal, wherein the first selection signal is used for enabling the selection module to determine the connection relation between the pins of the signal reconstruction chip and the pins of the read-only memory;

when the signal enhancement chip is arranged at the chip port, the complex programmable logic device generates the second selection signal according to the second mode signal, and the second selection signal is used for enabling the selection module to determine the connection relation between the pins of the signal enhancement chip and the pins of the read-only memory.

Optionally, the power module includes: the voltage conversion module, the transistor, the first resistor, the second resistor, the third resistor and the capacitor;

the voltage conversion module is respectively connected with the first end of the first resistor and the first end of the capacitor through a voltage output pin of the voltage conversion module;

the voltage conversion module is respectively connected with the first end of the transistor, the second end of the first resistor and the first end of the second resistor through feedback pins of the voltage conversion module;

the second end of the transistor receives the voltage signal, and the third end of the transistor is connected with the first end of the third resistor;

the second end of the third resistor is connected with the second end of the second resistor and grounded;

the second end of the capacitor is grounded;

when the signal reconstruction chip is arranged at the chip port, the transistor is controlled to be turned off by the voltage signal;

when the signal enhancement chip is arranged at the chip port, the transistor is controlled by the voltage signal to be conducted.

Optionally, when the signal reconstruction chip is disposed at the chip port, the signal reconstruction chip is connected to the rom through a first pin and a second pin of the signal reconstruction chip, and is connected to the baseboard management controller through a third pin and a fourth pin of the signal reconstruction chip;

when the signal enhancement chip is arranged at the chip port, the signal enhancement chip is grounded through a first pin and a second pin of the signal enhancement chip and is connected with the read-only memory through a third pin and a fourth pin of the signal enhancement chip;

the first pin and the second pin of the signal reconstruction chip and the first pin and the second pin of the signal enhancement chip are pins with the same pin number;

and the third pin and the fourth pin of the signal reconstruction chip and the third pin and the fourth pin of the signal enhancement chip are pins with the same pin number.

Optionally, the circuit board further includes: a connector;

the selection module receives bus signals from the baseboard management controller through the connector, and the selection module is grounded through a grounding pin of the selection module.

Optionally, when the current clock jitter meets a preset condition, the signal enhancement chip is arranged at the chip port;

when the clock jitter does not meet the preset condition, the signal reconstruction chip is arranged at the chip port.

Optionally, the circuit board further includes: a first connector and a second connector;

the chip port is connected with uplink equipment through the first connector and receives signals from the uplink equipment;

the chip port is connected with the downlink equipment through the second connector, and signals processed by the signal enhancement chip or the signal reconstruction chip are sent to the downlink equipment.

In a second aspect, an embodiment of the present invention provides an electronic device, including: a circuit board compatible with a signal reconstruction chip and a signal enhancement chip as in any one of the first aspects.

The invention provides a circuit board compatible with a signal reconstruction chip and a signal enhancement chip, which comprises: the device comprises a power module, a read-only memory, a complex programmable logic device, a chip port, a selection module and a configuration module. The complex programmable logic device is respectively connected with the configuration module and the selection module and is used for generating a voltage signal and a selection signal according to the mode signal sent by the configuration module.

The power module is respectively connected with the complex programmable logic device and the chip port and is used for generating different voltages according to the voltage signals and supplying the different voltages to the chip port; the selection module is connected with the chip port and the read-only memory and is used for determining the connection relation between the pins of the chip port and the pins of the read-only memory according to the selection signals. The chip port is configured as a layout signal reconstruction chip or a layout signal enhancement chip, and receives the configuration information sent by the configuration module and transmits the configuration information to the layout chip.

The invention provides a circuit board compatible with a signal reconstruction chip and a signal enhancement chip, and creatively provides a new circuit board which can be compatible with the signal reconstruction chip and the signal enhancement chip. The original configuration module is utilized to send a mode signal to the original complex programmable logic device, and the complex programmable logic device generates a voltage signal and a selection signal, so that the power supply module generates corresponding voltages according to different required voltages of the signal reconstruction chip or the signal enhancement chip, and the power supply requirement of the signal reconstruction chip or the signal enhancement chip is ensured.

Meanwhile, the selection module determines the corresponding pin connection relation according to different pin definitions of the signal reconstruction chip or the signal enhancement chip, so that the normal realization of the respective functions of the signal reconstruction chip or the signal enhancement chip is ensured.

In addition, because the signal reconstruction chip and the signal enhancement chip are compatible, whether the signal reconstruction chip or the signal enhancement chip is arranged on the circuit board can be determined according to actual use requirements, so that the cost is reduced, the advantages of the signal reconstruction chip and the signal enhancement chip are achieved, the defects of the signal reconstruction chip and the signal enhancement chip are overcome to a certain extent, and the signal reconstruction chip and the signal enhancement chip are high in practicability.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a circuit board structure of a conventional PCIE Retimer chip;

FIG. 2 is a schematic diagram of a circuit board compatible with a signal reconstruction chip and a signal enhancement chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a circuit board compatible with a signal reconstruction chip and a signal enhancement chip in an embodiment of the present invention;

FIG. 4 is a diagram of a power module output voltage circuit in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram of the connection between different chips and EEPROM in the embodiment of the invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The inventor finds that with the high-speed development of the fields of big data, artificial intelligence, cloud computing and the like, the high-speed hardware data interaction requirement in a server becomes more urgent. Today, the PCIe 5.0 era has come, the speed of information interaction between server hardware has risen again, the PCIe protocol at high speed has become a mainstream solution for server buses, PCIe devices have become an indispensable component in servers, and the performance, computation, functions, etc. of the servers are related to PCIe devices, and involve computation, storage, network, etc. of the servers, but with the consequent non-negligible signal attenuation problem. There are three main solutions currently in use:

1) Lower loss circuit boards (generally referred to as PCB boards: printed Circuit Board printed wiring board);

2) Adopting a PCIe driver chip;

3) PCIE repeater chips are used.

The latter two solutions are to add PCIe signal enhancement chips in PCIe links to reduce loss and guarantee device performance.

The inventor further researches and discovers that the upgrade of the data transmission rate can be accelerated by selecting a circuit board with lower loss, but the upgrade of the circuit board is difficult to have cost performance. Based on the results of a large number of tests, PCIE3.0 and the previous versions, the circuit board mostly adopts FR4 (code of a flame-retardant material grade) material, and the material can better support the data transmission rate of 8 Gbps.

But after pcie4.0 version, the bandwidth speed increases to 16Gbps, at which time the performance of FR4 material has not met the high speed transmission requirements, requiring lower loss boards, but at the same time bringing a cost-intensive rise.

And after PCIe is upgraded to 5.0 times, the bandwidth reaches 32Gbps, and higher requirements are put on the material of the circuit board. In practice, when the bandwidth speed is increased once, the marginal cost brought by adopting a mode of replacing the circuit board is increased, and the application scene of the multi-split air conditioner cannot be effectively covered. The option of using lower loss circuit boards is therefore essentially omitted.

At present, the most adopted is to arrange PCIe signal enhancement chips, and two types of existing PCIe signal enhancement chips are mainly, namely a PCIe driver chip and a PCIE timer chip. Compared with a PCIE (peripheral component interconnect express) timer chip, the PCIe (peripheral component interconnect express) timer chip has simpler circuit structure and signal processing mode, and re-enhances and re-transmits signals through signal equalization, pre-enhancing and other technologies. The pcie driver chip is essentially equivalent to a signal amplifier, and aims to boost the high-frequency part of the signal to counteract the frequency-dependent attenuation caused by interconnection, and supplement line loss through an equalizer at the transmitting end. The circuit board with PCIEREdriver chip is relatively simple and low in cost compared with a link, and is relatively simple to check when the link fails because only signals are re-reinforced.

The PCIE Retimer chip is relatively complex, and is sent out after being recovered by reconstructing signals through an internal clock. PCIE Retimer chips are essentially mixed signal analog/digital chips that use internal clock recovery circuitry to retime the input signal to eliminate clock skew and jitter and correct the phase and time offset (jitter) of the signal. It can delay the transmission distance of the interface and improve the signal quality. The PCIE Retimer chip mainly solves the problems that when a data center and a server transmit data at a high speed and a long distance through a PCIE protocol, signal timing is uneven, loss is large, integrity is poor and the like.

The PCIE driver chip and the PCIE timer chip are different in that the PCIE driver chip only enhances the original signal and supplements energy in the physical layer; the PCIE Retimer chip reconstructs the signal of the previous stage and then sends out the signal, so as to generate a clock and recover the data. In the invention, a PCIE driver chip is defined as a signal enhancement chip, a PCIE Retimer chip is defined as a signal reconstruction chip, the signal reconstruction chip is represented by Retimer in the drawing of the specification, and the signal enhancement chip is represented by the Retimer.

Taking the circuit board structure schematic diagram of the conventional PCIE Retimer chip shown in fig. 1 as an example, PCIE X16 signals of an upstream device (not shown in fig. 1) are connected to Retimer2 by a connector 1, and after the signals are processed by Retimer2, the signals are connected to a downstream device (not shown in fig. 1) by a connector 3. The upstream device 1, the Retimer2 and the downstream device 3 use a homologous clock architecture, and the clock signal (100 mclk) is provided by the upstream device board card.

Baseboard management controller Baseboard Management Controller, commonly referred to simply as BMC (not shown in FIG. 1), is connected by connector 1 to Retimer2 via the I2C bus; the power module 5 provides two direct current power supplies P1V8 and P0V9 for the Retimer2; CPLD (Complex ProgrammableLogic Device complex programmable logic device) 4 controls the power-up timing of Retimer2, the P1V8 EN and P0V9 EN signals enable control of P1V8 and P0V9 of Retimer2, respectively, and the PERST N and RESET N signals control PCIe global RESET and Retimer2 RESET, respectively.

Pin configuration module 6 provides simple configuration information for Retimer2, including I2C address and EEPROM (Electrically Erasable Programmable read only memory charged erasable programmable read Only memory) 7 mode, etc.; more detailed configuration is written into the EEPROM7, and the Retimer2 communicates with the EEPROM7 through an I2C bus signal to complete the configuration.

In general, if the system has low requirements for clock jitter, a circuit board with a r is used, and if the system has high requirements for clock jitter, a circuit board with a r is needed.

However, the cost of the circuit board carrying the retmer is higher, meanwhile, the complexity of the PCIe link is obviously increased, and when an error occurs in the PCIe link, the structure of the retmer is complex, the working principle is also complex, and the processing such as reconstruction recovery needs to be performed on PCIe signals, so that a specific failure cause is difficult to find in the process of troubleshooting.

When the circuit board with the repeater is applied to a system with low clock jitter requirement, the circuit board with the repeater can well meet the clock jitter requirement, but has higher cost, complex link structure, difficult fault detection and difficult replacement of the circuit board with the repeater. Similarly, when the circuit board with the r is applied to a system with higher clock jitter requirement, although the link structure is simple and the troubleshooting is simple, the circuit board with the r can not meet the clock jitter requirement, and the circuit board with the r is difficult to replace.

In order to solve the problems, the inventor creatively provides a circuit board and electronic equipment compatible with the signal reconstruction chip and the signal enhancement chip through a great deal of researches and actual measurement. The circuit board compatible with the signal reconstruction chip and the signal enhancement chip provided by the invention and the electronic equipment are explained and described in detail below.

Referring to fig. 2, a schematic diagram of a circuit board compatible with a signal reconstruction chip and a signal enhancement chip provided by the present invention is shown, which includes: power module 10, read only memory 60, complex programmable logic device 20, chip port 30, selection module 50, and configuration module 40. The complex programmable logic device 20 is respectively connected with the configuration module 40 and the selection module 50, and is used for generating a voltage signal and a selection signal according to the mode signal sent by the configuration module 40.

The power module 10 is respectively connected with the complex programmable logic device 20 and the chip port 30, and is used for generating different voltages according to the voltage signals and supplying the different voltages to the chip port 30; the selection module 50 is connected to the chip port 30 and the rom 60, and is configured to determine a connection relationship between a pin of the chip port 30 and a pin of the rom 60 according to the selection signal. The chip port 30 is configured as a layout signal reconstruction chip or a layout signal enhancement chip, and receives the configuration information sent by the configuration module 40 and transmits the configuration information to the laid out chips.

In order to realize a compatible signal reconstruction chip and a signal enhancement chip, the improvement is mainly carried out in three aspects:

1) The traditional PIN configuration module is improved;

2) The traditional power supply module is improved;

3) The pin connection relation between the traditional chip and the read-only memory is improved.

Firstly, aiming at the traditional PIN configuration module, because the PIN definition and the design requirements of the PIN PINs of the peripheral functions of the signal reconstruction chip and the signal enhancement chip are completely different, a new configuration module is creatively provided, which comprises: a first configuration unit or a second configuration unit.

When the signal reconstruction chip is arranged at the chip port, the configuration module is determined to be a first configuration unit, and the first configuration unit is used for sending a first mode signal to the complex programmable logic device; when the signal enhancement chip is arranged at the chip port, the configuration module is determined to be a second configuration unit, and the second configuration unit is used for sending a second mode signal to the complex programmable logic device. Thus, the compatibility problem among different chips can be simply solved.

In some possible embodiments, considering that both configuration units need to send mode signals to the complex programmable logic device, it is necessary to distinguish between the two mode signals, when the configuration module determines as the first configuration unit, the first mode signal is generated by the configuration module performing a pull-down process (i.e. the first mode signal=0); when the configuration module determines that the configuration module is the second configuration unit, the second mode signal is generated by the configuration module performing a pull-up process (i.e., the second mode signal=1).

In addition, considering that if the configuration module is directly soldered to the circuit board, it is inconvenient to replace the two configuration units, a preferred option is: the circuit board further includes: a pluggable interface; the configuration module is respectively connected with the complex programmable logic device and the chip port through pluggable interfaces. In this way, the configuration unit is very convenient to replace, and plug and play is realized. And because the circuit board does not need to be welded with a configuration module, the size of the circuit board is indirectly reduced, and the cost of the circuit board is reduced as a whole.

For the conventional power module, the required voltages of the two chips are different, the required voltages of the signal reconstruction chip are generally 1.8V and 0.9V, and the required voltages of the signal enhancement chip are generally 3.3V. Thus, by means of two different mode signals, the complex programmable logic device is enabled to determine whether a signal reconstruction chip or a signal enhancement chip is currently arranged on the chip port.

When the signal reconstruction chip is arranged at the chip port, the complex programmable logic device receives a first mode signal, and generates a first voltage signal according to the first mode signal, wherein the first voltage signal is used for enabling the power supply module to generate a first voltage, and the first voltage is the required voltage of the signal reconstruction chip.

When the signal enhancement chip is arranged at the chip port, the complex programmable logic device receives a second mode signal, and generates a second voltage signal according to the second mode signal, wherein the second voltage signal is used for enabling the power supply module to generate a second voltage, and the second voltage is the required voltage of the signal enhancement chip.

For the pin connection relationship between the traditional chip and the read-only memory, since the pin connection relationship between the two chips and the read-only memory is also different, for example: the current PCIe Gen5x16 driver chip cannot be set to be in a Pin configuration mode, and is usually set to be in an EEPROM configuration mode.

The invention therefore also proposes to generate different selection signals depending on the different mode signals: when the signal reconstruction chip is arranged at the chip port, the complex programmable logic device generates a first selection signal according to the first mode signal, and the first selection signal is used for enabling the selection module to determine the connection relation between the pins of the signal reconstruction chip and the pins of the read-only memory.

When the signal enhancement chip is arranged at the chip port, the complex programmable logic device generates a second selection signal according to the second mode signal, and the second selection signal is used for enabling the selection module to determine the connection relation between the pins of the signal enhancement chip and the pins of the read-only memory.

For a better explanation and understanding of the circuit board according to the present invention, reference is made to the schematic structural diagram of a circuit board with a preferred compatible signal reconstruction chip and signal enhancement chip shown in fig. 3. In addition to the power module 10, the rom 60, the complex programmable logic device 20, the chip port 30, the selection module 50, and the configuration module 40, the circuit board needs to be connected to an upstream device and a downstream device, so that the circuit board also has a first connector 70 connected to the upstream device and a second connector 80 connected to the downstream device, that is, the chip port 30 is connected to the upstream device (not shown in fig. 3) through the first connector 70, so as to receive signals from the upstream device; the chip port 30 is connected to a downstream device (not shown in fig. 3) through a second connector 80, and transmits a signal processed by the signal enhancement chip or the signal reconstruction chip to the downstream device.

In the link structure, the signals P3V3_P1V8_VR_FB and P3V3_P0V9_VR_FB are added between the complex programmable logic device 20 and the power module 10 in addition to the signals P1V8_EN and P0V9_EN to control the power module 10 to output 3.3V.

A selection module 50 is added to the conventional signal reconstruction chip circuit board, and the complex programmable logic device 20 also transmits a selection signal to the selection module 50, so that a SEL signal is added between the complex programmable logic device 20 and the selection module 50.

The selection module 50 also receives a bus signal (i.e., I2C in fig. 3) from a baseboard management controller (not shown in fig. 3) via the first connector 70, and the selection module 50 is grounded via its own ground pin (shown in fig. 3 by way of example as 3 (4) _2). Pins 1 (2), 3 (4) of selection module 50 are shown in fig. 3 as pins connected to chip port 30, and pins 1 (2) _2, 3 (4) _1 of selection module 50 are shown as pins connected to EEPEOM. Specific connection pins and connection patterns are shown with reference to fig. 5 below.

The mode signal sent by the configuration module 40 to the complex programmable logic device 20 is shown in fig. 3 by ID, when id=0, it indicates that the chip port 30 is configured with a signal reconstruction chip, and when id=1, it indicates that the chip port 30 is configured with a signal enhancement chip, and the states of the respective signals are shown in the following table:

for the control of the output voltage of the power supply module 10, a preferred structure is: the power module includes: the voltage conversion module, the transistor, the first resistor, the second resistor, the third resistor and the capacitor. Referring to the power module output voltage circuit configuration diagram shown in fig. 4. VR in fig. 4 represents a voltage conversion module, M represents a transistor, and the exemplary embodiment of fig. 4 is shown by taking an NMOS transistor as an example, which does not represent a specific limitation of the transistor, and any other device or circuit structure that can implement the same function may be replaced.

R1 represents a first resistor, R2 represents a second resistor, R3 represents a third resistor, and C represents a capacitance.

The voltage conversion module VR is respectively connected with the first end of the first resistor R1 and the first end of the capacitor C through a voltage output pin VOUT of the voltage conversion module VR; the voltage conversion module VR is connected to the first end (i.e. the drain) of the transistor M, the second end of the first resistor R1, and the first end of the second resistor R2 through its feedback pin FB.

The second terminal (i.e., gate) of the transistor M receives a voltage signal (represented by p3v3_p1v8_vr_fb in fig. 4 as an example), and the third terminal (i.e., source) is connected to the first terminal of the third resistor R3; the second end of the third resistor R3 is connected with the second end of the second resistor R2 and grounded; the second terminal of the capacitor C is also connected to ground.

When the signal reconstruction chip is arranged at the chip port, that is, when p3v3_p1v8_vr_fb=0 (p3v3_p0v9_vr_fb=0), the transistor M is controlled to be turned off by the voltage signal, and at this time, the third resistor R3 is turned off, and the relationship between the resistor and the output voltage is:

VOUT＝VFB＊(R1+R2)/R2

VFB represents the voltage output by feedback pin FB.

When the signal enhancement chip is arranged at the chip port, namely when p3v3_p1v8_vr_fb=1 (p3v3_p0v9_vr_fb=1), the transistor M is controlled to be turned on by the voltage signal, and the third resistor R3 is connected in parallel with the second resistor R2, and the relationship between the resistor and the output voltage is:

VOUT＝VFB＊(R1+R2//R3)/(R2//R3)

the on-off state of the transistor M is controlled through P3V 3_P1V8_VR_FB and P3V 3_P0V9_VR_FB signals output by the complex programmable logic device 20, the voltage division condition of the feedback resistor of the voltage conversion module VR is changed, and the output voltage of the voltage conversion module VR is changed from 1.8V (or 0.9V) to 3.3V.

When the complex programmable logic device 20 detects that the ID of the configuration module 40 is 0, it is recognized that a re chip is arranged on the circuit board, and at this time, p3v3_p1v8_vr_fb=0 and p3v3_p0v9_vr_fb=0 are output, the control transistor M is turned off, and the power supply module 10 outputs voltages of 1.8V and 0.9V.

When the complex programmable logic device 20 detects that the ID of the configuration module 40 is 1, it recognizes as a driver chip disposed on the circuit board, and outputs p3v3_p1v8_vr_fb=1 and p3v3_p0v9_vr_fb=1, controls the transistor M to be turned on, and the power module 10 outputs a voltage of 3.3V.

The selection module 50 is gated by the SEL signal (i.e., select signal) output by the complex programmable logic device 20C to implement different chip and EEPROM configuration designs.

When sel=1, it means that the signal enhancement chip is disposed at the chip port 30; when sel=0, it means that the signal reconstruction chip is disposed at the chip port 30.

When the signal reconstruction chip is arranged at the chip port 30, the signal reconstruction chip is connected with the read-only memory through the first pin and the second pin of the signal reconstruction chip and is connected with the baseboard management controller through the third pin and the fourth pin of the signal reconstruction chip; when the signal enhancement chip is arranged at the chip port 30, the signal enhancement chip is grounded through the first pin and the second pin of the signal enhancement chip, and is connected with the read-only memory through the third pin and the fourth pin of the signal enhancement chip.

Referring to the schematic diagram of the connection mode with the EEPROM at the time of different chips shown in fig. 5, the left diagram in fig. 5 shows: when the circuit board is provided with a driver, the driver is grounded through a first pin FJ3 and a second pin FF5 of the driver, and is connected with the read-only memory EEPROM through a third pin B31 and a fourth pin B28 of the driver.

The right diagram in fig. 5 shows: when the circuit board is provided with a re, the circuit board is connected with the read-only memory EEPROM through a first pin FJ3 and a second pin FF5 of the circuit board, and is connected with the baseboard management controller BMC through a third pin B31 and a fourth pin B28 of the circuit board.

Naturally, it can be understood that the first pin FJ3 and the second pin FF5 of the signal reconstruction chip are pins with the same pin number as the first pin FJ3 and the second pin FF5 of the signal enhancement chip; the third pin B31 and the fourth pin B28 of the signal reconstruction chip and the third pin B31 and the fourth pin B28 of the signal enhancement chip are pins with the same pin number.

In fig. 5, SCL represents the clock of the bus (i.e. I2C), SDA represents the data of the bus; EE_CLK represents the EEPROM clock and EE_DAT represents the EEPROM data.

Through the structure of the circuit board compatible with the signal reconstruction chip and the signal enhancement chip, when the current clock jitter meets the preset condition, the signal enhancement chip is arranged at a chip port; and when the current clock jitter does not meet the preset condition, arranging the signal reconstruction chip at the chip port. Wherein, the preset condition is determined according to the actual working requirement, for example: in actual working demands, when the clock jitter is defined to be more than 20%, a signal reconstruction chip is required, and when the current clock jitter is not more than 20%, only the loss is required to be compensated to a certain extent, the signal enhancement chip is arranged at a chip port; when the current clock jitter is greater than 20%, the signal reconstruction chip is arranged at the chip port.

From the above explanation and description, it is clear that: the circuit board compatible with the signal reconstruction chip and the signal enhancement chip is compatible with the driver chip based on the traditional circuit board of the Retimer chip and the link structure, and is started from the three main inventions because of different voltage requirements, different configuration information and different pin connection relations with the read-only memory. Two configuration units are provided, the layout of different chips corresponds to the different configuration units, and the configuration units send mode signals representing the current layout chip model to the complex programmable logic device, for example, the current layout is represented by a re chip when id=0, and the current layout is represented by a r chip when id=1.

The complex programmable logic device generates different voltage signals according to different mode signals and transmits the different voltage signals to the power module, so that the power module provides voltages meeting respective requirements for a Retimer chip or a Redriver chip arranged at a chip port according to the different voltage signals. For example, the increased p3v3_p1v8_vr_fb=0 and p3v3_p0v9_vr_fb=0 signals described above control the transistor to be turned off or on so that the power module outputs 1.8V and 0.9V or 3.3V.

The complex programmable logic device generates different voltage signals according to different mode signals, and simultaneously generates a selection signal and transmits the selection signal to the selection module. The selection module determines the pin connection relation between different layout chips and the read-only memory according to the selection signals so as to meet the pin connection relation between each of the Retimer chip and the Redriver chip and the read-only memory. And based on the work requirement of the selection module, the I2C bus is used for control, and the ground is connected through one pin, so that the compatibility of a driver chip on the basis of a circuit board of the Retimer chip is finally realized.

In addition, the structure of the circuit board compatible with the signal reconstruction chip and the signal enhancement chip can be widely applied to other similar chips and application environments. In the technical scheme conception disclosed by the invention, the technical scheme compatible with two or more chips under different application environments can be realized by simple reasoning and testing.

Based on the circuit board compatible with the signal reconstruction chip and the signal enhancement chip, the invention also provides electronic equipment, which comprises: the circuit board compatible with the signal reconstruction chip and the signal enhancement chip as set forth in any one of the above.

In summary, the circuit board compatible with the signal reconstruction chip and the signal enhancement chip provided by the invention comprises: the device comprises a power module, a read-only memory, a complex programmable logic device, a chip port, a selection module and a configuration module. The complex programmable logic device is respectively connected with the configuration module and the selection module and is used for generating a voltage signal and a selection signal according to the mode signal sent by the configuration module.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims

1. A circuit board compatible with a signal reconstruction chip and a signal enhancement chip, the circuit board comprising: the device comprises a power module, a read-only memory, a complex programmable logic device, a chip port, a selection module and a configuration module;

2. The circuit board of claim 1, wherein the configuration module comprises: a first configuration unit or a second configuration unit;

3. The circuit board of claim 2, wherein the first mode signal is generated by the configuration module by a pull-down process when the configuration module determines the first configuration unit;

4. A circuit board according to any one of claims 1-3, wherein the circuit board further comprises: a pluggable interface;

5. The circuit board of claim 2, wherein when the signal reconstruction chip is disposed at the chip port, the complex programmable logic device generates a first voltage signal according to the first mode signal, the first voltage signal being used to cause the power module to generate a first voltage, the first voltage being a required voltage of the signal reconstruction chip;

6. The circuit board of claim 1, wherein the power module comprises: the voltage conversion module, the transistor, the first resistor, the second resistor, the third resistor and the capacitor;

the second end of the capacitor is grounded;

7. The circuit board of claim 1, wherein when the signal reconstruction chip is disposed at the chip port, the signal reconstruction chip is connected to the read only memory through its first pin and second pin, and is connected to the baseboard management controller through its third pin and fourth pin;

8. The circuit board of claim 1, wherein the circuit board further comprises: a connector;

9. The circuit board of claim 1, wherein the signal enhancement chip is disposed at the chip port when a current clock jitter satisfies a preset condition;

10. The circuit board of claim 1, wherein the circuit board further comprises: a first connector and a second connector;

11. An electronic device, the electronic device comprising: a circuit board compatible with a signal reconstruction chip and a signal enhancement chip as claimed in any one of claims 1 to 10.