CN116627871A

CN116627871A - Signal transmission circuit, computing equipment and storage backboard

Info

Publication number: CN116627871A
Application number: CN202310403483.9A
Authority: CN
Inventors: 张波
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-04-13
Filing date: 2023-04-13
Publication date: 2023-08-22

Abstract

The embodiment of the application discloses a signal transmission circuit, a computing device and a storage backboard, wherein the signal transmission circuit comprises a first circuit board, a first storage backboard and a second storage backboard, the first circuit board comprises a first expansion interface, the first storage backboard comprises a first upstream interface and a first downstream interface, the first upstream interface is connected with the first downstream interface, the second storage backboard comprises a second upstream interface, and the first upstream interface is connected with the first expansion interface; the second upstream interface is connected with the first downstream interface, or the first circuit board further comprises a second expansion interface, and the second upstream interface is connected with the first downstream interface and the second expansion interface respectively. The embodiment of the application can reduce the wiring difficulty of the main board, save hardware resources and improve the flexibility of expansion of the storage backboard.

Description

Signal transmission circuit, computing equipment and storage backboard

Technical Field

The present application relates to the field of computer technologies, and in particular, to a signal transmission circuit, a computing device, and a storage back plate.

Background

With the progress of computer technology, the functions and performances of the server are continuously improved and perfected, and the server plays an increasingly important role in the fields of cloud computing, data centers, big data and the like. In order to meet the increasing data storage demands, the demands on the storage capacity of the server are also increasing. Meanwhile, in order to meet the storage requirements of different storage capacities, a server is generally required to support flexible expansion of the storage capacities.

Typically, one or more expansion interfaces are reserved on the motherboard of the server, and these expansion interfaces may be used to connect different storage subsystems (e.g., storage backplane) to expand the storage capacity of the server. Because a group of expansion interfaces can be connected with a storage backboard, for a designed motherboard, if the number of reserved expansion interfaces is too small, the expansion requirements of the storage backboard cannot be met. However, if the number of the reserved expansion interfaces is too large, resources are wasted.

Disclosure of Invention

The embodiment of the application discloses a signal transmission circuit, computing equipment and a storage backboard, which can reduce the wiring difficulty of a main board, save hardware resources and improve the flexibility of expansion of the storage backboard.

The first aspect discloses a signal transmission circuit comprising a first circuit board, a first storage back plate and a second storage back plate; the first circuit board comprises a first expansion interface; the first storage backboard comprises a first upstream interface and a first downstream interface, and the first upstream interface is connected with the first downstream interface; the second storage backplane includes a second upstream interface; the first upstream interface is connected with the first expansion interface; the second upstream interface is connected with the first downstream interface, or the first circuit board further comprises a second expansion interface, and the second upstream interface is connected with the first downstream interface and the second expansion interface respectively.

In the embodiment of the application, the first storage backboard can comprise a first upstream interface and a first downstream interface, and the first downstream interface can be connected. Based on the method, the second upstream interface of the second storage backboard can be connected with the first downstream interface of the first storage backboard, and cascading transmission of signals can be achieved, so that expansion interfaces do not need to be reserved for the second storage backboard on the first circuit board independently, the number of reserved expansion interfaces can be reduced, and therefore wiring difficulty of a main board can be reduced, and hardware resources can be saved. In addition, in the mode, the expansion of the storage backboard is not limited by the number of expansion interfaces and the types and the like of reserved connectors, so that more expansion scenes of the storage backboard can be met, and the flexibility of the expansion of the storage backboard can be improved.

As one possible implementation, the signal transmission circuit further includes a third storage backplane, the third storage backplane including a third upstream interface; the second storage backplane further comprises a second downstream interface; the third upstream interface is connected with the second downstream interface, or the first circuit board further comprises a third expansion interface, and the third upstream interface is connected with the second downstream interface and the third expansion interface respectively.

In the embodiment of the application, when the second storage backboard comprises the downstream interface, the third storage backboard can also carry out cascade expansion based on the downstream interface of the second storage backboard, and the expansion interface on the first circuit board is not dependent or partially dependent, so that the flexibility of expansion of the storage backboard can be further improved.

As one possible implementation, the first expansion interface includes a first high-speed signal interface, a first management signal interface, and a first power signal interface; the second expansion interface comprises at least one of a second high-speed signal interface, a second management signal interface and a second power supply signal interface; the first upstream interface and the second upstream interface comprise a high-speed signal interface, a management signal interface and a power signal interface, and the first downstream interface comprises at least one of the high-speed signal interface, the management signal interface and the power signal interface;

the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface are respectively connected with the first high-speed signal interface, the first management signal interface and the first power signal interface of the first expansion interface;

if the first downstream interface comprises a high-speed signal interface, a management signal interface and a power signal interface, the high-speed signal interface, the management signal interface and the power signal interface in the first downstream interface are correspondingly connected with the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface, and the high-speed signal interface, the management signal interface and the power signal interface in the second upstream interface respectively;

If the first downstream interface includes any one or any two interfaces of the high-speed signal interface, the management signal interface and the power signal interface, any one or any two interfaces of the first downstream interface are respectively connected with a corresponding one or two interfaces of the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface and a corresponding one or two interfaces of the high-speed signal interface, the management signal interface and the power signal interface in the second upstream interface, and the other interfaces in the second upstream interface are correspondingly connected with a corresponding interface of the second high-speed signal interface, the second management signal interface and the second power signal interface in the second expansion interface.

In the embodiment of the present application, the downstream interface of the first storage backplane may include at least one of a high-speed signal interface, a management signal interface, and a power signal interface, that is, the first downstream interface may include 7 cases, which are respectively: only high-speed signal interfaces, only management signal interfaces, only power signal interfaces, both high-speed signal interfaces and management signal interfaces, both management signal interfaces and power signal interfaces, both high-speed signal interfaces and power signal interfaces, and both high-speed signal interfaces, management signal interfaces and power signal interfaces. Based on these 7 different cases, the connection of the first downstream interface and the second upstream interface may be different. If the first downstream interface comprises a certain signal interface (e.g. a power signal interface), the signal interface may be connected to a corresponding signal interface in the second upstream interface, and if the first downstream interface does not comprise a certain signal interface (e.g. a high-speed signal interface), the signal interface may be connected to a corresponding signal interface in the second expansion interface. In an actual scene, the setting of the downstream interface of the storage backboard comprises various conditions, and the flexibility is high. In the embodiment of the application, the first downstream interface can simultaneously comprise the management signal interface and the power signal interface, so that reservation of the management signal interface and the power signal interface on the first circuit board can be reduced, and the wiring difficulty of the main board can be reduced. In addition, in the mode, the transmission of the high-speed signal can be based on the second expansion interface on the first circuit board, and the efficiency of the high-speed signal transmission can be ensured.

As a possible implementation manner, the first expansion interface includes a first high-speed signal interface, a first management signal interface and a first power signal interface; the second expansion interface includes at least one of a second high-speed signal interface, a second management signal interface, and a second power signal interface; the first upstream interface and the second upstream interface each comprise a high-speed signal interface, a management signal interface and a power signal interface, and the first downstream interface comprises at least one of the high-speed signal interface, the management signal interface and the power signal interface; the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface are respectively connected with the first high-speed signal interface, the first management signal interface and the first power signal interface of the first expansion interface; if the first downstream interface comprises a high-speed signal interface, the high-speed signal interface in the first downstream interface is connected with the high-speed signal interface in the first upstream interface, and the high-speed signal interface in the first downstream interface is also connected with the high-speed signal interface in the second upstream interface; if the first downstream interface does not comprise a high-speed signal interface, the high-speed signal interface in the second upstream interface is connected with a second high-speed signal interface of the second expansion interface; if the first downstream interface comprises a management signal interface, the management signal interface in the first downstream interface is connected with the management signal interface in the first upstream interface; the management signal interface in the first downstream interface is also connected with the management signal interface in the second upstream interface; if the first downstream interface does not comprise a management signal interface, the management signal interface in the second upstream interface is connected with a second management signal interface of the second expansion interface; if the first downstream interface comprises a power signal interface, the power signal interface in the first downstream interface is connected with the power signal interface in the first upstream interface; the power signal interface in the first downstream interface is also connected with the power signal interface in the second upstream interface; if the first downstream interface does not include a power signal interface, the power signal interface in the second upstream interface is connected with a second power signal interface of the second expansion interface.

In the embodiment of the present application, the downstream interface of the first storage backplane may include at least one of a high-speed signal interface, a management signal interface, and a power signal interface, that is, the first downstream interface may include 7 cases, which are respectively: only high-speed signal interfaces, only management signal interfaces, only power signal interfaces, both high-speed signal interfaces and management signal interfaces, both management signal interfaces and power signal interfaces, both high-speed signal interfaces and power signal interfaces, and both high-speed signal interfaces, management signal interfaces and power signal interfaces. Based on these 7 different cases, the connection of the first downstream interface and the second upstream interface may be different. If the first downstream interface comprises a certain signal interface (e.g. a power signal interface), the signal interface may be connected to a corresponding signal interface in the second upstream interface, and if the first downstream interface does not comprise a certain signal interface (e.g. a high-speed signal interface), the signal interface may be connected to a corresponding signal interface in the second expansion interface. In an actual scene, the setting of the downstream interface of the storage backboard comprises various conditions, and the flexibility is high.

As one possible implementation manner, the first storage backboard further comprises an expansion chip, the expansion chip comprises an upstream interface and a downstream interface, and a high-speed signal interface in the first upstream interface is connected with the upstream interface of the expansion chip; if the first downstream interface comprises a high-speed signal interface, the expansion chip comprises at least two downstream interfaces, one of the downstream interfaces of the expansion chip is connected with the high-speed signal interface in the first downstream interface, and the other downstream interfaces of the expansion chip are connected with the storage interface of the first storage backboard; if the first downstream interface does not comprise a high-speed signal interface, the downstream interface of the expansion chip is connected with the storage interface of the first storage backboard; the storage interface is used for connecting with a storage disk.

In the embodiment of the application, when the number of the high-speed signal channels corresponding to the high-speed signal interfaces in the first upstream interface is insufficient, the number of the high-speed signal channels can be expanded by the expansion chip, so that cascade connection of the storage backboard or the storage disk can be supported.

As a possible implementation manner, the first storage backplane further includes a backplane controller, and if the first downstream interface includes a management signal interface, the backplane controller is connected to the management signal interface in the first upstream interface, and the backplane controller is further connected to the management signal interface in the first downstream interface.

In the embodiment of the application, cascade connection of management signal lines (such as a management bus, a single-ended signal line and the like) or cascade transmission of management signals and normal access of slave devices (such as a hard disk) can be realized through the backboard controller on the storage backboard. In some embodiments, the backplane controller may perform forwarding of data (e.g., forwarding of I2C data, JTAG data, etc.), interaction of upper and lower level backplane information, etc., to ensure cascading communication between storage backplanes.

As a possible implementation manner, the first storage backboard further comprises a voltage adjustment module, the power signal interface in the first upstream interface is connected with the input end of the voltage adjustment module, and the output end of the voltage adjustment module is used for supplying power to the components on the first storage backboard.

In the embodiment of the application, the input end of the voltage adjusting module of the first storage backboard can be connected with the power supply signal interface in the first upstream interface, so that the voltage adjusting module can convert the input voltage into the power supply voltage required by the component on the first storage backboard.

As one possible implementation, the first high-speed signal interface of the first circuit board further includes a peripheral component interconnect express (peripheral component interconnect express, PCIe) interface for connecting to a PCIe device.

In the embodiment of the application, because the PCIe device may include a high-speed signal interface and the first circuit board may be provided with a PCIe interface, in some cases, when the PCIe device is connected to the PCIe interface provided on the first circuit board, the high-speed signal interface of the first circuit board may be the high-speed signal interface of the PCIe device. It can be seen that PCIe interface and PCIe-based devices can further improve flexibility of storage backplane expansion.

As one possible implementation, the PCIe device is a redundant array of independent disks card.

As one possible implementation, the second downstream interface includes at least one of a high-speed signal interface, a management signal interface, and a power signal interface; if the second downstream interface comprises a high-speed signal interface, the high-speed signal interface in the second downstream interface is connected with the high-speed signal interface in the second upstream interface; if the second downstream interface comprises a management signal interface, the management signal interface in the second downstream interface is connected with the management signal interface in the second upstream interface; if the second downstream interface includes a power signal interface, the power signal interface in the second downstream interface is connected with the power signal interface in the second upstream interface.

A second aspect discloses a computing device comprising the signal transmission circuit provided in the first aspect and any one of the possible implementations of the first aspect.

A third aspect discloses a storage backplane comprising an upstream interface comprising a high-speed signal interface, a management signal interface, and a power signal interface, and a downstream interface comprising at least one of the high-speed signal interface, the management signal interface, and the power signal interface; if the downstream interface of the storage backboard comprises a high-speed signal interface, the high-speed signal interface in the downstream interface is connected with the high-speed signal interface in the upstream interface; if the downstream interface of the storage backboard comprises a management signal interface, the management signal interface in the downstream interface is connected with the management signal interface in the upstream interface; if the downstream interface of the storage backboard comprises a power signal interface, the power signal interface in the downstream interface is connected with the power signal interface in the upstream interface.

A fourth aspect discloses a computing device comprising a storage backplane as provided in the third aspect above.

It should be appreciated that the implementation and benefits of the various aspects of the application described above, or any of the possible embodiments, may be referenced with respect to one another.

Drawings

The drawings in the following description will be presented to more clearly illustrate the technical solution of the embodiments of the present application, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a related art computing device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another related art computing device in accordance with an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a storage backplane according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating transmission of a power signal according to an embodiment of the present application;

FIG. 5 is a schematic diagram illustrating transmission of another power signal according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 7 is a schematic diagram of another storage backplane according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a high-speed signal transmission according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 10 is a schematic diagram of a further memory backplane according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 12A is a schematic diagram of an I2C bus cascade as disclosed in an embodiment of the application;

FIG. 12B is a schematic diagram illustrating signal transmission of an I2C bus cascade according to an embodiment of the present application;

FIG. 12C is a schematic diagram illustrating signal transmission of a URAT bus cascade according to an embodiment of the present application;

FIG. 13A is a schematic diagram of an SGPIO bus cascade disclosed by embodiments of the present application;

fig. 13B is a schematic diagram illustrating signal transmission of an SGPIO bus cascade according to an embodiment of the present application;

FIG. 14A is a schematic diagram of a JTAG bus cascade according to an embodiment of the present application;

FIG. 14B is a schematic diagram of signal transmission of a JTAG bus cascade according to an embodiment of the present application;

FIG. 14C is a schematic diagram of a PRESENT signal line cascade disclosed in an embodiment of the PRESENT application;

FIG. 14D is a schematic diagram of a Board_ID signal line cascade according to an embodiment of the present application;

FIG. 15 is a schematic diagram of a further memory backplane according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 17 is a schematic diagram of a further memory backplane according to an embodiment of the present disclosure;

FIG. 18 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 19 is a schematic diagram of a further memory backplane according to an embodiment of the present disclosure;

FIG. 20 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 21 is a schematic diagram of a further memory backplane according to an embodiment of the present disclosure;

FIG. 22 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the application;

FIG. 23 is a schematic diagram of a signal transmission circuit according to an embodiment of the present application;

fig. 24 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application.

Detailed Description

The embodiment of the application discloses a signal transmission circuit, computing equipment and a storage backboard, which can reduce the wiring difficulty of a main board, save hardware resources and improve the flexibility of expansion of the storage backboard. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

In order to better understand the embodiments of the present application, the following describes application scenarios of the embodiments of the present application.

The signal transmission circuit and the computing device provided by the embodiment of the application can be applied to the storage backboard expansion scene in the field of servers, can improve the flexibility of storage backboard expansion of the servers, and can save hardware resources and the like.

By way of example, the servers may be heterogeneous servers, rack servers, high-density servers, etc., of various configurations and types, and the embodiments of the present application are not limited in this regard.

In order to better understand the embodiments of the present application, the related art of the embodiments of the present application will be described first.

Peripheral component interconnect express (peripheral component interconnect express, PCIe) technology has evolved from PCIe version 1.0 to PCIe version 5.0 (generation 5 PCIe technology). Currently, the data link speed of PCIe 5.0 can reach 32 gigabit transmission/second (giga transmission per second, GT/s), twice that of PCIe 4.0, and has downward compatibility.

PCIe is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices allocate exclusive channel bandwidths and do not share bus bandwidths. To meet the transmission requirements of different devices, PCIe data transmissions include different specifications of X1, X4, X8, X16, and the like. X1 represents 1 Lane, including both transmit and receive directions, each direction including 1 pair of differential signals, and thus 1 Lane can transmit 2 pairs of differential signals. Similarly, X2 represents 2 Lane, 4 pairs of differential signals may be transmitted, X8 represents 8 Lane, 16 pairs of differential signals may be transmitted, X16 represents 16 Lane, and 32 pairs of differential signals may be transmitted. Wherein, the more Lane number, the faster the data transmission rate can be.

A redundant array of independent disks (redundant arrays of independent disks, RAID) card may combine multiple hard disks to form a hard disk group (logical hard disk) to provide higher storage performance than a single hard disk, and may also provide a data backup function to improve reliability of data storage.

Typically, one or more expansion interfaces are reserved on the host system (motherboard) of the server, and these one or more expansion interfaces may be used to connect to different storage subsystems (e.g., storage backplane) to expand the storage capacity of the server. Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of a computing device in the related art according to an embodiment of the present application. As shown in fig. 1, computing device 100 may include a motherboard 101, and 4 sets of expansion interfaces, expansion interface 1011-expansion interface 1014, may be included on motherboard 101. Each set of expansion interfaces can comprise a power signal interface, a management signal interface and a high-speed signal interface, and can be connected with one storage backboard, so that 4 sets of expansion interfaces can expand 4 storage backboard at most. The power signal interface may be used to output power on the motherboard 101 to a storage backplane to power components on the storage backplane (e.g., a backplane controller, hard disk, etc.). The management signal interface may be used to transmit management signals (control signals) to enable management of components (e.g., hard disk) on the storage backplane, such as firmware upgrades, lighting storage disk indicators on the storage backplane, etc. The high-speed signal interface may be used to transmit high-speed signals such as peripheral component interconnect express (peripheral component interconnect express, PCIe) signals, serial attached small computer system interface (serial attached small computer system interface, SAS) signals, SATA (serial advanced technology attachment) signals, etc. for reading and writing data to and from a hard disk on the storage backplane.

The expansion interface on the motherboard 101 may be connected to the storage backplane according to actual needs, may be partially connected to the storage backplane, or may be fully connected to the storage backplane. For example, in the case where all the storage backplanes are connected, the power signal interface, the management signal interface, and the high-speed signal interface of the expansion interface 1011 may be connected to the power signal interface, the management signal interface, and the high-speed signal interface of the storage backplane 1 (102), respectively. The power signal interface, the management signal interface, and the high-speed signal interface of the expansion interface 1012 may be connected to the power signal interface, the management signal interface, and the high-speed signal interface of the storage backplane 2 (103), respectively. The power signal interface, management signal interface, and high-speed signal interface of the expansion interface 1013 may be connected to the power signal interface, management signal interface, and high-speed signal interface of the storage backplane 3 (104), respectively. The power signal interface, the management signal interface, and the high-speed signal interface of the expansion interface 1014 may be connected to the power signal interface, the management signal interface, and the high-speed signal interface of the storage backplane 4 (105), respectively.

In the above manner, for one motherboard, when the storage backboard or the storage capacity needs to be expanded, multiple storage backboard can be connected in parallel through the expansion interface reserved on the motherboard, so as to realize expansion. However, this approach is not flexible and is limited in the number of expansion interfaces on the motherboard during expansion.

It should be understood that interfaces in embodiments of the present application (e.g., power signal interface, management signal interface, and high speed signal interface) may be connectors or other conductive terminals. The management signal generally belongs to a low-speed signal, and therefore, the management signal interface may be a low-speed signal connector. That is, the management signal may be transmitted through the low-speed signal connector. Similarly, the power signal interface may be a power signal connector (power connector), and the high-speed signal interface may be a high-speed signal connector (e.g., PCIe connector, SAS connector, SATA connector, etc.). It should be further understood that, in the embodiment of the present application, the function of the interface or the connector is mainly to realize signal transmission between each component, and may be selected according to practical situations, which is not limited in the embodiment of the present application.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a computing device in another related art according to an embodiment of the present application. As shown in fig. 2, computing device 200 may include a motherboard 201, and a central processing unit (central processing unit, CPU) 2011, a high-speed signal connector 2012, a power connector 2013, a low-speed signal connector 2014, a PCIe connector (PCIe expansion slot) 2015, a power connector 2018, and a low-speed signal connector 2019 may be included on motherboard 201. When the storage backboard needs to be expanded, expansion can be performed through a high-speed signal connector, a power connector, a low-speed signal connector and the like on the main board. For example, for storage backplane a (202), its high-speed signal connector 2021 may be connected by a cable to the high-speed signal connector 2012 on the motherboard, its power connector 2022 may be connected by a cable to the power connector 2013 on the motherboard, and its low-speed signal connector 2023 may be connected by a cable to the low-speed signal connector 2014 on the motherboard. For another example, for storage backplane b (203), at this time, since no corresponding high-speed signal interface can be connected on the motherboard, RAID card 2016 may be inserted into a slot of PCIe connector 2015 first. Specifically, the RAID card 2016 may be inserted into a slot of the PCIe connector 2015 by its own gold finger, so that the RAID card 2016 is electrically connected to the PCIe connector 2015, so that the central processor 2011 on the motherboard 201 may output a high-speed signal to the RAID card 2016. RAID card 2016 may include high-speed signal connectors 2017, which may be connected by cables between high-speed signal connectors 2017 and high-speed signal connectors 2031 on storage backplane b (203). The power connector 2032 on the storage backplane b (203) and the power connector 2018 on the motherboard may be connected by a cable, and the low-speed signal connector 2033 on the storage backplane b (203) and the low-speed signal connector 2019 on the motherboard may be connected by a cable.

As can be seen from fig. 2, the storage backplane a (202) may include 8 storage connectors (hard disk interfaces), the storage backplane b (203) may include 4 storage connectors, and it is assumed that the central processor 2011 is in communication with the hard disks on the storage backplane a (202) and the storage backplane b (203) via PCIe signals, where each storage connector may correspond to 1 PCIe Lane, thus, the high-speed signal connector 2021 and the high-speed signal connector 2012 may each be a PCIe X8 connector (e.g., a Slimline X8 connector), and the high-speed signal connector 2031 and the high-speed signal connector 2017 may each be a PCIe X4 connector (e.g., a Slimline X4 connector). The storage connector can be used for plugging the hard disk.

As is clear from the corresponding related description of fig. 2, for a motherboard (i.e., a motherboard that has been designed), the number of high-speed signal connectors, the number of power connectors, the number of low-speed signal connectors, and the number of PCIe connectors on the motherboard are fixed, and thus there is a limit to the number of memory backplanes that can support expansion. In addition, since the number of channels (such as PCIe channels) corresponding to the high-speed signal connector on the motherboard is also fixed, the device can generally only adapt to a specific storage backplane, and has a small application range.

For a motherboard in a design, it is generally not possible to determine how many high-speed signal connectors, power connectors, low-speed signal connectors, PCIe connectors, etc. need to be reserved to meet future expansion requirements, if too many types of connectors are reserved, problems such as design redundancy, insufficient space, difficult motherboard wiring, increased cost, etc. will be caused, if too few types of connectors are reserved, the later expansion requirements cannot be met, and the motherboard needs to be redesigned, thereby resulting in a longer development period of server products. Moreover, the form of the reserved connector or the number of corresponding channels cannot be determined, so that various application scenarios may not be satisfied.

Further, because of limited high-speed signal connectors and the like on the motherboard, it may be necessary to develop different storage backplanes generally for different storage requirements, for example, if 4 hard disks need to be supported, a storage backplane including 4 hard disk interfaces generally needs to be developed, if 8 hard disks need to be supported, a storage backplane including 8 hard disk interfaces generally needs to be developed, if 16 hard disks need to be supported, a storage backplane including 16 hard disk interfaces generally needs to be developed. This may result in too many types of storage backplanes for maintenance.

In order to solve the above-mentioned problems, an embodiment of the present application discloses a storage backplane, which may include an upstream interface and a downstream interface, where the upstream interface of one storage backplane may be connected to an expansion interface on a motherboard, or may be connected to the downstream interface of another storage backplane. In this way, cascade connection can be realized among a plurality of storage backplanes, and in some cases, an expansion interface is reserved on the motherboard to meet the expansion requirement of the storage backplanes.

Embodiments of the present application provide a storage backplane (hard disk backplane), which may include an upstream interface and a downstream interface. The upstream interface of the storage backboard may include a high-speed signal interface, a management signal interface and a power signal interface, and the downstream interface of the storage backboard may include at least one of the high-speed signal interface, the management signal interface and the power signal interface, that is, the downstream interface may include 7 different cases, where the 7 cases are specifically: only including high-speed signal interface, only including management signal interface, only including the power signal interface, including high-speed signal interface and management signal interface simultaneously, including high-speed signal interface and power signal interface simultaneously, including management signal interface and power signal interface simultaneously, including high-speed signal interface, management signal interface and power signal interface simultaneously.

It should be noted that the high-speed signal interface in the upstream interface of one storage backplane may be connected to the high-speed signal interface in the expansion interface on the first circuit board, or may be connected to the high-speed signal interface in the downstream interface of another storage backplane. The management signal interface in the upstream interface of one storage backboard can be connected with the management signal interface in the expansion interface on the first circuit board, and also can be connected with the management signal interface in the downstream interface of other storage backboard. The power signal interface in the upstream interface of one storage backboard can be connected with the power signal interface in the expansion interface on the first circuit board, and can also be connected with the power signal interface in the downstream interface of other storage backboard. The first circuit board may be a motherboard, or may be another circuit board including an expansion interface.

When the high-speed signal interface in the upstream interface of the storage backboard is connected with the high-speed signal interface in the expansion interface on the first circuit board, the high-speed signal (such as PCIe signal, SAS signal, SATA signal and the like) can be transmitted between the high-speed signal interface and the first circuit board. When the high-speed signal interface in the upstream interface of one storage backboard is connected with the high-speed signal interface in the downstream interface of the other storage backboard, the board-to-board transmission of high-speed signals can be realized, and the high-speed signal transmission between the storage backboard and the first circuit board can be realized through the storage backboard connected with the first circuit board in the plurality of cascaded storage backboard. Similarly, when the management signal interface in the upstream interface of the storage backboard is connected with the management signal interface in the expansion interface on the first circuit board, management signals can be transmitted between the storage backboard and the first circuit board. When the management signal interface in the upstream interface of one storage backboard is connected with the management signal interface in the downstream interface of the other storage backboard, the board-to-board transmission of the management signal can be realized, and the management signal transmission between the storage backboard and the first circuit board can be realized through the storage backboard connected with the first circuit board in the plurality of cascaded storage backboard. When the power signal interface in the upstream interface of the storage backboard is connected with the power signal interface in the expansion interface on the first circuit board, the transmission of the power signal can be carried out between the storage backboard and the first circuit board. When the power signal interface in the upstream interface of one storage backboard is connected with the power signal interface in the downstream interface of the other storage backboard, the board-to-board transmission of the power signal can be realized, and the power signal transmission between the storage backboard and the first circuit board can be realized through the storage backboard connected with the first circuit board in the plurality of cascaded storage backboard.

Therefore, the storage backboard can be expanded according to actual requirements by reducing the arrangement of the high-speed connector, the power connector, the low-speed signal connector and the PCIe connector on the first circuit board through the cascade connection mode of the upstream interface and the downstream interface, and the expansion quantity of the storage backboard can be free from the limitation of the quantity of the high-speed connector, the power connector and the like on the first circuit board, so that the flexibility is higher.

The computing device provided by the present application and 7 different types of storage backplanes are illustrated below in connection with fig. 3-24.

Next, a description will be given of a case where the downstream interface of the storage backboard includes only the power signal interface, please refer to fig. 3, fig. 3 is a schematic structural diagram of the storage backboard according to an embodiment of the present application. As shown in fig. 3, the storage backplane 300 may include an upstream interface 301 and a downstream interface 302. The upstream interface 301 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 302 may include a power signal interface.

The power signal interface in the upstream interface 301 of the storage backplane 300 may be connected to the power signal interface in the downstream interface 302 so that transmission of power signals between the upstream and downstream interfaces may be achieved.

It should be appreciated that the high-speed signal interface in the upstream interface 301 of the storage backplane 300 may be connected to a corresponding component (e.g., a hard disk interface) on the storage backplane 300, so as to facilitate transmission of high-speed signals (e.g., PCIe signals, SAS signals, SATA signals, etc.), reading and writing of hard disk data, etc. The management signal interface in the upstream interface 301 of the storage backplane 300 may be connected to a corresponding component (e.g., a storage backplane controller) on the storage backplane 300 to facilitate transmission of management signals (e.g., joint test workgroup signals, inter-integrated circuit signals, etc.) to control the component (e.g., hard disk) on the storage backplane 300, etc. The power signal interface in the upstream interface 301 of the storage backplane 300 may be coupled to corresponding components (e.g., storage backplane controller, hard disk, etc.) on the storage backplane 300 to facilitate the transmission of power signals to power those components.

In the embodiment of the present application, since the power supply voltages required by the various components on the storage backplane 300 may include a plurality of types (e.g. 1.8V, 3.3V, 5V, etc.), the power signal transmission on the storage backplane 300 may also take a plurality of different manners. For example, a power signal interface in the upstream interface of the storage backplane may receive one voltage (e.g., 12V, 24V, etc.), and may then be converted to a different voltage, such as 1.8V, 3.3V, 5V, etc., by a voltage regulation module (voltage regulator module, VRM) on the storage backplane. For another example, the power signals in the upstream interface of the storage backplane may directly receive different voltage signals, such as 1.8V, 3.3V, 5V, etc., which may then be provided to corresponding components on the storage backplane 300, respectively. In the embodiment of the present application, the voltage input by the power signal interface in the upstream interface of the storage backplane 300 and the voltage output by the power signal interface in the downstream interface of the storage backplane 300 are not limited.

Two ways of power signal transmission on the storage backplane are briefly described below in connection with fig. 4 and 5. Referring to fig. 4, fig. 4 is a schematic diagram illustrating transmission of a power signal according to an embodiment of the application. As shown in fig. 4, the power signal input from the power signal interface in the upstream interface 301 of the storage backplane 300 may be 12V, and the 12V power signal may be transferred to the power signal interface in the downstream interface 302 of the storage backplane 300. Storage backplane 300 may include 3 voltage regulation modules, namely VRM1 (303), VRM2 (304), and VRM3 (305), VRM1 (303) may be used to convert 12V of electricity input from a power signal interface in upstream interface 301 to 5V of electricity, VRM2 (304) may be used to convert 5V of electricity output by VRM1 (303) to 1.8V of electricity, and VRM3 (305) may be used to convert 12V of electricity input from a power signal interface in upstream interface 301 to 3.3V of electricity. Thus, 1.8V, 3.3V, 5V of electricity is available for use by the corresponding components on the storage backplane 300. It should be understood that the conversion, transmission, etc. of the power signal shown in fig. 4 are only exemplary and not limiting. In other embodiments of the present application, VRM2 (304) may be a 12V to 1.8V voltage regulator or a 3.3V to 1.8V voltage regulator, and VRM1 (303) may be a 5V to 3.3V voltage regulator. In still other embodiments of the present application, the power signals of 1.8V, 3.3V, and 5V obtained after the conversion of the voltage adjustment module may be directly transferred to the power signal interface in the downstream interface 302 of the storage backplane 300, and the downstream interface 302 may not need to input the 12V power signal.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating transmission of a power signal according to another embodiment of the present application. As shown in fig. 5, the voltage input by the power signal interface in the upstream interface 301 of the storage backplane 300 may be the voltage required by each component on the storage backplane 300, such as 1.8V, 3.3V and 5V, the power signals of 1.8V, 3.3V and 5V may be transferred to the power signal interface in the downstream interface 302 of the storage backplane 300, and the power signal interface of the upstream interface 301 and the power signal interface of the downstream interface 302 have at least three terminals to input the power signals of 1.8V, 3.3V and 5V. And, the 1.8V, 3.3V, 5V power signals may be used by corresponding components on the storage backplane 300. It will be appreciated that the two modes of power signal transmission described above may be used alone or in combination.

The cascade of storage backplanes whose downstream interfaces include only power signal interfaces is exemplified below. Referring to fig. 6, fig. 6 is a schematic structural diagram of another computing device according to an embodiment of the present disclosure. As shown in fig. 6, the computing device 600 may include a first circuit board 601, and an expansion interface 1 (6011), an expansion interface 2 (6012), and an expansion interface 3 (6013) may be included on the first circuit board 601. Among them, the expansion interface 1 (6011) may include a high-speed signal interface, a power signal interface, and a management signal interface, and the expansion interface 2 (6012) and the expansion interface 3 (6013) may include a high-speed signal interface and a management signal interface. When the storage backplane 1 (602) needs to be expanded for the computing device 600, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 6021 of the storage backplane 1 (602) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the expansion interface 1 (6011) on the first circuit board 601. When the storage backplane 2 (603) also needs to be extended for the computing device 600, the high-speed signal interface and the management signal interface in the upstream interface 6031 of the storage backplane 2 (603) may be respectively connected to the high-speed signal interface and the management signal interface in the extension interface 2 (6012) on the first circuit board 601, and the power signal interface in the upstream interface 6031 of the storage backplane 2 (603) may be respectively connected to the power signal interface in the downstream interface 6022 of the storage backplane 1 (602). When the storage backplane 3 (604) also needs to be extended for the computing device 600, the high-speed signal interface and the management signal interface in the upstream interface 6041 of the storage backplane 3 (604) may be respectively connected to the high-speed signal interface and the management signal interface in the extension interface 3 (6013) on the first circuit board 601, and the power signal interface in the upstream interface 6041 of the storage backplane 3 (604) may be respectively connected to the power signal interface in the downstream interface 6032 of the storage backplane 2 (603). It should be understood that the storage backplane cascade shown in fig. 6 is merely illustrative and not limiting, and that in other embodiments of the present application, more or fewer storage backplanes as described in fig. 3 may be included, and that the cascade may be performed as appropriate.

Therefore, the power signal interface can be reserved on the first circuit board, and the power signal interface is not required to be reserved for each storage backboard, so that the number of the power signal interfaces on the first circuit board can be reduced, and the wiring difficulty of the first circuit board can be further reduced.

It can be appreciated that, when the first power transmission mode is adopted, the first circuit board 601 may output a voltage (e.g. 12V) to the storage backboard 1 (602), the number of pins (pins) of the power connector may be 2Pin pins of the power connector, and a voltage adjustment module needs to be set on each storage backboard. When the above second power transmission mode is adopted, the first circuit board 601 needs to be provided with a plurality of voltage adjustment modules, and a plurality of voltages (such as 1.8V, 3.3V, 5V, etc.) can be output to the storage backboard 1 (602) through the plurality of voltage adjustment modules, at this time, the Pin number of the power connector can be 8Pin of the power connector for outputting the above three different voltage signals, and the voltage adjustment modules do not need to be set on each storage backboard, so that the setting number of the voltage adjustment modules can be reduced, and the overall cost can be reduced. Under the actual scene, different transmission modes can be flexibly selected and used according to the actual situation.

It should be understood that the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 6021 of the storage backplane 1 (602) in fig. 6 are all connected to the corresponding high-speed signal interface, the power signal interface, and the management signal interface in the expansion interface 1 (6011) on the first circuit board 601, but in other embodiments of the present application, different interfaces in the upstream interface of a storage backplane may be connected to corresponding interfaces on different circuit boards. For example, assuming that the computing device includes circuit board 1 and circuit board 2, where circuit board 1 (e.g., a motherboard) includes a high-speed signal interface and a management signal interface thereon, and circuit board 2 (e.g., a power backplane) includes a power signal interface thereon, then the high-speed signal interface and the management signal interface in the upstream interface of storage backplane 1 may be connected to corresponding high-speed signal interface and management signal interface on circuit board 1, respectively, and the power signal interface of storage backplane 1 may be connected to corresponding power signal interface on circuit board 2.

It should be noted that the computing device may include a power supply unit (power supply unit, PSU), which may convert 220V, 380V, etc. to 48V/12V, and the 48V/12V obtained after conversion may be provided to the first circuit board, and may be directly provided to the storage back plane through the first circuit board, or may be provided to the storage back plane after conversion through the first circuit board.

In the following, a case where the downstream interface of the storage backplane includes only the high-speed signal interface will be described, referring to fig. 7, fig. 7 is a schematic structural diagram of another storage backplane according to an embodiment of the present disclosure. As shown in fig. 7, the storage backplane 700 may include an upstream interface 701 and a downstream interface 702. The upstream interface 701 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 702 may include a high-speed signal interface.

The high-speed signal interface in the upstream interface 701 of the storage backplane 700 may be connected with the high-speed signal interface in the downstream interface 702 so that transmission of high-speed signals between the upstream interface and the downstream interface may be achieved. It should be understood that the high-speed signal interface in the upstream interface 701 of the storage backplane 700 may also be connected to a corresponding component (e.g., a hard disk interface) on the storage backplane 700, so as to facilitate transmission of high-speed signals (e.g., PCIe signals, SAS signals, SATA signals, etc.), reading and writing hard disk data, etc.

It will be appreciated that the high speed signal interfaces in the upstream interface include a limited number of high speed signal lanes (e.g., PCIe lanes, SAS lanes, etc.), while each of the storage interfaces on the storage backplane and the high speed signal interfaces in the downstream interface need to occupy a certain number of high speed signal lanes. Therefore, when the high-speed signal interface in the upstream interface includes a shortage of high-speed signal channels, the number of high-speed signal channels can be expanded by the expansion chip. For example, PCIe links (PCIe lanes) may be extended through PCIe switch (switch) chips, providing more PCIe interfaces for connecting PCIe devices. For another example, a SAS channel may be expanded by a SAS expander chip. It should be noted that, in the embodiment of the present application, the number of high-speed signal channels included in the high-speed signal interface in the upstream interface of the storage backplane 700 and the number of high-speed signal channels included in the high-speed signal interface in the downstream interface of the storage backplane 700 are not limited.

The manner in which high-speed signals are transmitted on the storage backplane is illustrated in connection with fig. 8. Referring to fig. 8, fig. 8 is a schematic diagram illustrating transmission of a high-speed signal according to an embodiment of the application. As shown in fig. 8, the memory backplane 700 may further include an expansion chip 703 and a plurality of memory interfaces (four are illustrated). The extension chip 703 may include an upstream interface (UP) 7031 and a plurality of downstream interfaces (DP), a downstream interface 7032 and a downstream interface 7033. The upstream interface of the expansion chip 703 and the high-speed signal interface in the upstream interface 701 of the storage backplane 700 may be connected to expand the high-speed signal channels included in the high-speed signal interface in the upstream interface 701. The downstream interfaces of the expansion chip 703 are expanded interfaces, and these expanded interfaces can be connected with other high-speed signal devices (such as PCIe devices) or can be connected with the upstream interfaces of other expansion chips to expand to obtain more high-speed signal channels. For example, the downstream interface 7033 of the expansion chip 703 and the storage interface 704 may be connected, and the storage interface 704 may be connected to a hard disk, so that reading and writing of hard disk data may be realized. The downstream interface 7032 of the expansion chip 703 may be connected to a high-speed signal interface in the downstream interface 702 of the storage backplane 700 to provide a high-speed signal path to other cascaded storage backplanes.

The cascade of storage backplanes whose downstream interfaces include only high-speed signal interfaces is exemplified below. Referring to fig. 9, fig. 9 is a schematic structural diagram of another computing device according to an embodiment of the present application. As shown in fig. 9, the computing device 900 may include a first circuit board 901, and an expansion interface 1 (9011), an expansion interface 2 (9012), and an expansion interface 3 (9013) may be included on the first circuit board 901. Among them, the expansion interface 1 (9011) may include a high-speed signal interface, a power signal interface, and a management signal interface, and the expansion interface 2 (9012) and the expansion interface 3 (9013) may include a power signal interface and a management signal interface. When the storage backplane 1 (902) needs to be expanded for the computing device 900, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 9021 of the storage backplane 1 (902) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the expansion interface 1 (9011) on the first circuit board 901. When it is also desired to extend the storage backplane 2 (903) for the computing device 900, the power signal interface and the management signal interface in the upstream interface 9031 of the storage backplane 2 (903) may be correspondingly connected to the power signal interface and the management signal interface in the extension interface 2 (9012) on the first circuit board 901, respectively, and the high-speed signal interface in the upstream interface 9031 of the storage backplane 2 (903) may be correspondingly connected to the high-speed signal interface in the downstream interface 9022 of the storage backplane 1 (902). When the storage backplane 3 (904) also needs to be expanded for the computing device 900, the power signal interface and the management signal interface in the upstream interface 9041 of the storage backplane 3 (904) may be respectively connected to the power signal interface and the management signal interface in the expansion interface 3 (9013) on the first circuit board 901, and the high-speed signal interface in the upstream interface 9041 of the storage backplane 3 (904) may be respectively connected to the high-speed signal interface in the downstream interface 9032 of the storage backplane 2 (903). It should be understood that the storage backplane cascade shown in fig. 9 is merely illustrative and not limiting, and that in other embodiments of the present application, more or fewer storage backplanes as described in fig. 7 or 8 may be included, and that the cascade may be performed as appropriate.

Therefore, a high-speed signal interface can be reserved on the first circuit board, and the high-speed signal interface is not required to be reserved for each storage backboard, so that the number of the high-speed signal interfaces on the first circuit board can be reduced, and the wiring difficulty of the first circuit board can be further reduced.

It should be noted that, the high-speed channel may be extended by using an extension chip on the storage back plane, but when a plurality of storage back planes are cascaded in multiple stages, there is a cascade of a plurality of extension chips. When a plurality of expansion chips are cascaded, the higher the data transmission efficiency of the higher hierarchy is, the lower the transmission efficiency of the lower hierarchy is, so in order to avoid the data transmission efficiency being too low, the number of cascaded memory backplanes can be controlled to be smaller than a certain threshold (e.g. 3 or 4). For example, as shown in fig. 9, a cascade connection between the storage backplane 1 (902), the storage backplane 2 (903), and the storage backplane 3 (904), the storage backplane 1, the storage backplane 2, and the storage backplane 3 may include an expansion chip 1, an expansion chip 2, and an expansion chip 3 thereon, respectively, for expanding high-speed signal channels for high-speed signal interface transmission in upstream interfaces of the storage backplane 1, the storage backplane 2, and the storage backplane 3, respectively. The upstream interface of the expansion chip 2 and the storage interface on the storage backboard 1 (902) can be respectively connected with the downstream interface of the expansion chip 1, the upstream interface of the expansion chip 3 and the storage interface on the storage backboard 2 (903) can be respectively connected with the downstream interface of the expansion chip 2, and the storage interface on the storage backboard 3 (904) can be connected with the downstream interface of the expansion chip 3. When the downstream interface of one expansion chip performs data transmission, the number of high-speed signal channels included in the upstream interface is fixed, which is equivalent to the number of high-speed signal channels included in the upstream interface that a plurality of devices (such as a plurality of hard disks) connected with the downstream interface can share. Therefore, the transfer efficiency of the storage disk (e.g., hard disk) on the storage backplane 1 (902) of the higher hierarchy is higher than the transfer efficiency of the storage disk (e.g., hard disk) on the storage backplane 2 (903) and the storage backplane 3 (904) of the lower hierarchy. And, forwarding links are longer with lower hierarchy, which also results in lower transmission efficiency.

It is understood that the computing device may include a CPU, a south bridge chip (platform controller hub, PCH), etc. that may transmit high-speed signals (e.g., PCIe signals, SAS signals, SATA signals, etc.), and the high-speed signal interface on the first circuit board may be connected to pins of the CPU, PCH chip that may transmit high-speed signals.

In some embodiments, the first circuit board may have one or more PCIe interfaces disposed thereon, which may be used to connect PCIe devices. Also, some PCIe devices (e.g., RAID cards) may provide a high speed signal interface, and thus, in some embodiments, the high speed signal interface of the first circuit board may be a high speed signal interface on a PCIe device.

In the following, a case where the downstream interface of the storage backplane includes only the management signal interface will be described, referring to fig. 10, fig. 10 is a schematic structural diagram of another storage backplane according to an embodiment of the present disclosure. As shown in fig. 10, storage backplane 1000 may include an upstream interface 1001 and a downstream interface 1002. The upstream interface 1001 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1002 may include a management signal interface.

The management signal interface in the upstream interface 1001 of the storage backplane 1000 may be connected with the management signal interface in the downstream interface 1002 so that transmission of management signals between the upstream interface and the downstream interface may be achieved. It should be appreciated that the management signal interface in the upstream interface 1001 of the storage backplane 1000 may also be connected to a corresponding component (e.g., a hard disk interface, a storage backplane controller) on the storage backplane 1000 to facilitate the transmission of management signals to manage the component (e.g., a hard disk) on the storage backplane.

The following illustrates a cascade of storage backplanes where the downstream interface of the storage backplanes comprises only management signal interfaces. Referring to fig. 11, fig. 11 is a schematic structural diagram of another computing device according to an embodiment of the present application. As shown in fig. 11, the computing device 1100 may include a first circuit board 1101, and the first circuit board 1101 may include an expansion interface 1 (11011), an expansion interface 2 (11012), and an expansion interface 3 (11013) thereon. Among them, the expansion interface 1 (11011) may include a high-speed signal interface, a power signal interface, and a management signal interface, and the expansion interface 2 (11012) and the expansion interface 3 (11013) may include a power signal interface and a high-speed signal interface. When it is desired to extend the storage backplane 1 (1102) for the computing device 1100, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 11021 of the storage backplane 1 (1102) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the extension interface 1 (11011) on the first circuit board 1101. When the storage backplane 2 (1103) also needs to be expanded for the computing device 1100, the power signal interface and the high-speed signal interface in the upstream interface 11031 of the storage backplane 2 (1103) may be respectively connected to the power signal interface and the high-speed signal interface in the expansion interface 2 (11012) on the first circuit board 1101, and the management signal interface in the upstream interface 11031 of the storage backplane 2 (1103) may be respectively connected to the management signal interface in the downstream interface 11022 of the storage backplane 1 (1102). When the storage backplane 3 (1104) also needs to be expanded for the computing device 1100, the power signal interface and the high-speed signal interface in the upstream interface 11041 of the storage backplane 3 (1104) may be respectively connected to the power signal interface and the high-speed signal interface in the expansion interface 3 (11013) on the first circuit board 1101, and the management signal interface in the upstream interface 11041 of the storage backplane 3 (1104) may be respectively connected to the management signal interface in the downstream interface 11032 of the storage backplane 2 (1103). It should be understood that the storage backplane cascade shown in fig. 11 is merely illustrative and not limiting, and that in other embodiments of the present application, more or fewer storage backplanes as described in fig. 10 may be included, and that the cascade may be performed as appropriate.

Therefore, the management signal interface can be reserved on the first circuit board, and the management signal interface is not required to be reserved for each storage backboard, so that the number of the management signal interfaces on the first circuit board can be reduced, and the wiring difficulty of the first circuit board can be further reduced.

It will be appreciated that the management bus on the memory backplane may include a variety of types such as JTAG (joint test action group ) buses, SGPIO (serial general-purpose input/output) buses, UART (universal asynchronous receiver/transmitter ) buses, I2C (inter-integrated circuit, inter-integrated circuit) buses, etc., and that the memory backplane may also include single-ended signal lines such as a PRESENT signal line, a Board_ID signal line (identification code signal line of the memory backplane), etc. Accordingly, the management signals on the memory backplane may include a variety of signals such as JTAG signals, SGPIO signals, UART signals, I2C signals, PRESENT signals (e.g., memory backplane bit signals), board_ID signals (e.g., memory backplane identification codes), and the like.

The cascade connection of these management signal lines (e.g., management bus, single-ended signal line, etc.) or cascade transmission of the management signal, and normal access of the slave devices (e.g., hard disk) can be realized by the backplane controller on the storage backplane. The backplane controller may be a processor (e.g., CPU), a complex programmable logic device (complex programmable logic device, CPLD), an application specific integrated circuit, a field programmable gate array, etc., and the backplane controller is described below as a CPLD.

The following exemplary description will be made of the concatenation of buses such as JTAG bus, I2C bus, SGPIO bus, and the like, respectively. The I2C bus is a bidirectional two-wire synchronous serial bus, and can transfer information between devices connected to the bus through two signal lines (a serial data line SDA and a serial clock line SCL). Referring to fig. 12A, fig. 12A is a schematic diagram of an I2C bus cascade according to an embodiment of the application. As shown in fig. 12A, the computing device 1200 may include a first circuit board 1201 and a plurality of cascaded memory backplanes, such as memory backplane 1 (1202), memory backplane 2 (1203), and memory backplane 3 (1204). The transmission of I2C signals may be performed between the first circuit board 1201 and a plurality of cascaded memory backplanes. Specifically, the baseboard management controller (baseboard management controller, BMC) 12011 on the first circuit board 1201 may be connected to the management signal interface 12012, the management signal interface 12012 may be connected to the management signal interface 12022 in the upstream interface on the storage backplane 1 (1202), the management signal interface 12022 may be connected to the CPLD (12021) on the storage backplane 1 (1202), and the CPLD (12021) may be connected to the management signal interface 12023 in the other I2C devices (e.g., hard disk, temperature sensor, etc.) on the storage backplane 1 (1202) and the downstream interface. The management signal interface 12032 in the upstream interface on the storage backplane 2 (1203) may be connected to the management signal interface 12023 in the downstream interface on the storage backplane 1 (1202), the management signal interface 12032 may be connected to the CPLD (12031) on the storage backplane 2 (1203), and the CPLD (12031) may be connected to other I2C devices on the storage backplane 2 (1203) and the management signal interface 12033 in the downstream interface. The management signal interface 12042 in the upstream interface on the storage backplane 3 (1204) may be connected to the management signal interface 12033 in the downstream interface on the storage backplane 2 (1203), the management signal interface 12042 may be connected to the CPLD (12041) on the storage backplane 3 (1204), and the CPLD (12041) may be connected to other I2C devices on the storage backplane 3 (1204) and the management signal interface 12043 in the downstream interface. It should be understood that the manner in which the I2C bus is cascaded as shown in fig. 12A is merely illustrative and not limiting.

For a clearer understanding of the I2C bus cascade shown in fig. 12A, reference may be made to fig. 12B, and fig. 12B is a schematic diagram illustrating signal transmission of an I2C bus cascade according to an embodiment of the present application. As shown in fig. 12B, two I2C pins of the BMC (12011) may be connected with two I2C pins of the CPLD (12021) through a signal management interface (not shown in fig. 12B) to enable transmission of SCL signals and SDL signals between the BMC (12011) and the CPLD (12021). The other two I2C pins of the CPLD (12021) may be connected with the two I2C pins of the CPLD (12031) through a signal management interface (not shown in fig. 12B) to implement transmission of SCL signals and SDL signals between the CPLD (12021) and the CPLD (12031). The other two I2C pins of the CPLD (12031) may be connected with the two I2C pins of the CPLD (12041) through a signal management interface (not shown in fig. 12B) to implement transmission of SCL signals and SDL signals between the CPLD (12031) and the CPLD (12041). It should be understood that the CPLDs on the respective storage backplanes may also be connected to other I2C devices on the storage backplanes (not shown in FIG. 12B). The I2C pin may be a GPIO (general-purpose input/output) pin of the CPLD.

It should be noted that, in the embodiment of the present application, the CPLD on the storage backplane may play a role in forwarding in the I2C link. For example, when communication is performed between the BMC on the first circuit board and the I2C device on the subsequent storage backplane, the CPLD on the previous one or more stages of storage backplane may forward data transmitted between the I2C device and the BMC on the subsequent storage backplane. And, CPLD on a storage backboard can forward data transmitted between other I2C devices and BMC on the local storage backboard. Specifically, in one possible implementation, since there may be a conflict between the I2C addresses of the I2C devices on different storage backplanes in the cascade, when the BMC on the first circuit Board performs I2C communication with the I2C devices on the storage backplanes, the board_id of the storage backplanes and the addresses of the corresponding I2 cs may be indicated, and the conflict between the I2C addresses may be avoided by the board_id. For example, assuming that the board_id of the storage backplane 1 (1202) is 01, the board_id of the storage backplane 2 (1203) is 10, and the board_id of the storage backplane 3 (1204) is 11 in fig. 12B, when the BMC (12011) needs to perform I2C communication with the temperature sensor on the storage backplane 3 (1204), the BMC (12011) may send relevant data to the CPLD (12021) and indicate that the corresponding board_id is 11, and the corresponding I2C device address is the address of the temperature sensor, e.g. 010. After the CPLD (12021) receives the data sent by the BMC (12011), the CPLD (12021) may determine that the indicated board_id is 11, and may forward the data to the CPLD (12031) unlike the own board_id 01. After the CPLD (12031) receives the data transmitted by the CPLD (12021), the CPLD (12031) may determine that the indicated board_id is 11, and may continue forwarding the data to the CPLD (12041) unlike the own board_id 10. After the CPLD (12041) receives the data sent by the CPLD (12031), the CPLD (12041) can determine that the indicated board_id11 is the same as the board_id of the storage backboard where the CPLD is located, and can send the data to the temperature sensor on the storage backboard 3 (1204) according to the indicated I2C address 010. It should be understood that the above description of I2C communications is merely exemplary and not limiting.

The UART bus is similar to the cascade of I2C buses, and reference is made to the description above with respect to fig. 12A. The UART bus includes a Transmit (TX) signal line and a Receive (RX) signal line, and an equivalent signal transmission schematic diagram thereof may be seen in fig. 12C. As shown in fig. 12C, the two UART pins of the BMC (12011) may be connected with the two UART pins of the CPLD (12021) through a signal management interface (not shown in fig. 12C) to implement transmission of TX signals and RX signals between the BMC (12011) and the CPLD (12021). The other two UART pins of the CPLD (12021) may be connected with the two UART pins of the CPLD (12031) through a signal management interface (not shown in fig. 12C) to implement transmission of TX signals and RX signals between the CPLD (12021) and the CPLD (12031). The other two UART pins of the CPLD (12031) may be connected with the two UART pins of the CPLD (12041) through a signal management interface (not shown in fig. 12C) to enable transmission of TX signals and RX signals between the CPLD (12031) and the CPLD (12041). It should be appreciated that the CPLD on the memory backplane may forward both the TX and RX signals. For example, the CPLD (12021) on the storage backplane 1 (1202) may forward the TX signal transmitted by the BMC (12011) to the CPLD (12031), or may forward the RX signal transmitted by the CPLD (12031) to the BMC (12011).

The SGPIO bus is a serial bus that can be used by a controller (e.g., CPLD, RAID card, etc.) to output the status of a storage disk (e.g., solid state disk). Referring to fig. 13A, fig. 13A is a schematic diagram of an SGPIO bus cascade according to an embodiment of the present application. As shown in fig. 13A, a computing device 1300 may include a first circuit board 1301 and multiple cascaded memory backplanes, such as memory backplane 1 (1302), memory backplane 2 (1303), and memory backplane 3 (1304). The transmission of SGPIO signals may be performed between the first circuit board 1301 and a plurality of cascaded memory backplanes. Specifically, the CPLD or south bridge chip (platform controller hub, PCH) 13011 on the first circuit board 1301 may be connected to a management signal interface 13012, the management signal interface 13012 may be connected to a management signal interface 13022 in an upstream interface on the storage backplane 1 (1302), the management signal interface 13022 may be connected to a CPLD (13021) on the storage backplane 1 (1302), and the CPLD (13021) may be connected to other I2C devices on the storage backplane 1 (1302) and a management signal interface 13023 in a downstream interface. The connection relation of the storage backboard 2 (1303) and the storage backboard 3 (1304) is similar to that shown in fig. 12A, and reference is made to the corresponding description of fig. 12A. It should be understood that the manner in which the SGPIO bus is cascaded as shown in fig. 13A is merely illustrative and not limiting.

For a clearer understanding of the SGPIO bus cascade shown in fig. 13A, reference may be made to fig. 13B, and fig. 13B is a schematic signal transmission diagram of the SGPIO bus cascade according to an embodiment of the present application. As shown in fig. 13B, the SGPIO bus may include Sclok, sload, sdataout, sdatain four signal lines, the Sdatain signal line being optional. Wherein, sclok may be a clock signal line, sload may be an end signal line of the current bit stream, sdataout may be a data output signal line, and Sdatain may be a data input signal line. Four SGPIO pins of the CPLD/PCH (13011) may be connected to four SGPIO pins of the CPLD (13021) to enable transmission of the Sclok signal, the Sload signal, the Sdataout signal, and the Sdatain signal between the CPLD/PCH (13011) and the CPLD (13021). The other four SGPIO pins of the CPLD (13021) may be connected with the four SGPIO pins of the CPLD (13031) to enable transmission of the Sclok signal, the Sload signal, the Sdataout signal, and the Sdatain signal between the CPLD (13021) and the CPLD (13031). The other four SGPIO pins of the CPLD (13031) may be connected with the four SGPIO pins of the CPLD (13041) to realize transmission of the Sclok signal, the Sload signal, the Sdataout signal, and the Sdatain signal between the CPLD (13031) and the CPLD (13041). It should be appreciated that the CPLDs on the respective storage backplanes may also be connected to a storage disk indicator light (not shown in FIG. 13B) on the storage backplanes. The SGPIO pin may be a GPIO pin of the CPLD.

It should be noted that in the embodiment of the present application, the CPLD on the storage backplane may play a role in forwarding in the SGPIO link. For example, the CPLD (13021) may forward to the CPLD (13031) the Sclok signal, the Sload signal, and the Sdataout signal sent by the CPLD/PCH (13011) on the first circuit board. And, CPLDs on the respective storage backplanes may illuminate storage disk indicators on the storage backplanes based on the received Sdataout signals. Specifically, in one possible implementation manner, the CPLD/PCH (13011) may send lighting signals of all storage disks to the CPLD (13021) in order of the storage backplane, and it is assumed that 4 hard disks are inserted on the storage backplane 1 (1302), the storage backplane 2 (1303) and the storage backplane 3 (1304), where the lighting signals sent by the CPLD/PCH (13011) may include lighting data corresponding to 12 hard disks. The first 4 lighting data of the lighting signals transmitted by the CPLD/PCH (13011) may be lighting signals corresponding to 4 hard disks on the storage backplane 1 (1302), the middle 4 lighting data may be lighting signals corresponding to 4 hard disks on the storage backplane 2 (1303), and the last 4 lighting data may be lighting signals corresponding to 4 hard disks on the storage backplane 3 (1304). After the CPLD (13021) on the storage backplane 1 (1302) receives the lighting signal sent by the CPLD/PCH (13011), the first 4 lighting data can be taken to light the indicator lights corresponding to the 4 hard disks on the storage backplane 1 (1302). For example, it is assumed that 4 hard disks are numbered 00, 01, 10, and 11, respectively, and 4 lighting data may correspond to the 4 hard disks in order. Similarly, the CPLD (13031) on the storage back plane 2 (1303) can light up the indicator lamps corresponding to the 4 hard disks on the storage back plane 2 (1303) according to the middle 4 lighting data in the lighting signal. The CPLD (13041) on the storage backplane 3 (1304) may light the indicator lights corresponding to the 4 hard disks on the storage backplane 3 (1304) according to the last 4 lighting data in the lighting signal.

The JTAG bus is generally used for testing chips and the like, upgrading firmware (such as upgrading firmware of CPLD on a storage backboard), and the like, and a plurality of chips can be connected in series through JTAG interfaces to form a JTAG chain, so that the respective tests of the devices can be realized. The JTAG signals generally include TCK (time cycle clock), TMS (test mode selection, test mode select signal), TDI (test data in, test data in signal), and TDO (test data out signal). Referring to fig. 14A, fig. 14A is a schematic diagram of a JTAG bus cascade according to an embodiment of the present application. As shown in fig. 14A, computing device 1400 may include a first circuit board 1401 and multiple cascaded memory backplanes, such as memory backplane 1 (1402), memory backplane 2 (1403), and memory backplane 3 (1404). The transmission of JTAG signals may be performed between the first circuit board 1401 and a plurality of cascaded memory backplanes. Specifically, the BMC (14011) on the first circuit board 1401 may be connected to the management signal interface 14012, and the connection lines thereof may include 4 signal lines in total of the TCK signal line, the TMS signal line, the TDI signal line, and the TDO signal line. The management signal interface 14012 may be connected to a management signal interface 14023 in an upstream interface on the storage backplane 1 (1402), and the management signal interface 14023 may be connected to a JTAG connector (14022) on the storage backplane 1 (1402), which connection may include 3 signal lines for transmitting TDI signals, TCK signals, and TMS signals to the JTAG connector (14022). The management signal interface 14023 may also be connected to a management signal interface 14024 on the storage backplane 1 (1402), which connection may include 3 signal lines for transmitting TCK signals and TMS signals to the management signal interface 14024 and receiving TDO signals from the management signal interface 14024. The management signal interface 14023 may also be connected to the CPLD (14021), which connection may include 2 signal lines for transmitting the TCK signal and the TMS signal to the CPLD (14021). The CPLD (14021) may also be connected with a JTAG connector (14022), which connection may include 1 signal line for receiving a TDO signal from the JTAG connector (14022). The CPLD (14021) may also be connected to the management signal interface 14024, and the connection may include 1 signal line for outputting the TDO signal to the management signal interface 14024. The relevant connections of the storage backplane 2 (1403) and the storage backplane 3 (1404) are similar to the storage backplane 1 (1402), and reference is made to the relevant description of the storage backplane 1. It should be noted that the last board in the cascade, namely the storage backplane 3 (1404), has to be connected together to form a complete data transmission loop to manage the TDI and TDO pins in the signal interface in the downstream interface. It should be understood that the manner in which the JTAG bus cascade shown in FIG. 14A is illustrative only and not limiting.

For a clearer understanding of the JTAG bus cascade shown in fig. 14A, reference may be made to fig. 14B, and fig. 14B is a schematic diagram illustrating signal transmission of the JTAG bus cascade according to an embodiment of the present application. As shown in fig. 14B, TMS pins and TCK pins of BMC (14011) may be connected with TMS pins and TCK pins of JTAG connector 14022, JTAG connector 14032, JTAG connector 14042, CPLD (14021), CPLD (14031) and CPLD (14041), respectively, to output TMS signals and TCK signals to corresponding TMS pins and TCK pins of JTAG connector 14022, JTAG connector 14032, JTAG connector 14042, CPLD (14021), CPLD (14031) and CPLD (14041). The TDI pin of BMC (14011) may be connected to the TDI pin of JTAG connector 14022, the TDO pin of JTAG connector 14022 may be connected to the TDI pin of CPLD (14021), the TDO pin of CPLD (14021) may be connected to the TDI pin of JTAG connector 14032, the TDO pin of JTAG connector 14032 may be connected to the TDI pin of CPLD (14031), the TDO pin of CPLD (14031) may be connected to the TDI pin of JTAG connector 14042, the TDO pin of JTAG connector 14042 may be connected to the TDI pin of CPLD (14041), and the TDO pin of CPLD (14041) may be connected to the TDO pin of BMC (14011), thus a complete data transmission loop may be constructed.

It should be noted that, when the JTAG connector in fig. 14A and 14B is not connected to an external device, the TDI pin and the TDO pin may be shorted to transmit data. Also, it will be appreciated that in some embodiments, the JTAG connector in FIGS. 14A and 14B described above may not be provided, the TDI pin of BMC (14011) may be connected to the TDI pin of CPLD (14021), the TDO pin of CPLD (14021) may be connected to the TDI pin of CPLD (14031), and the TDO pin of CPLD (14031) may be connected to the TDI pin of CPLD (14041).

The PRESENT signal line is mainly used for identifying whether the storage backboard is on line, and generally includes 1 signal line, and fig. 14C may be referred to, and fig. 14C is a schematic diagram of a cascade of PRESENT signal lines according to an embodiment of the PRESENT application. As shown in fig. 14C, the first circuit board 1405 may include a power supply VDD and a resistor R1, when the first circuit board 1405 is not cascaded to the storage back plane 1 (1406), the first end of the resistor R1 is connected to VDD, the second end of the resistor R1 is in a floating state, and the voltage detected by the CPLD (14051) through the PRESENT pin may be VDD, where it may be determined that the first circuit board (1405) is not cascaded to the storage back plane. When the first circuit board 1405 cascades the storage backplane 1 (1406), the first terminal of the resistor R1 is connected to VDD, the second terminal of the resistor R1 may be grounded on the storage backplane 1 (1406), and the voltage detected by the CPLD (14051) through the presence pin may be 0V, at which point it may be determined that the first circuit board (1405) cascades the storage backplane. Similarly, when the storage backplane 1 (1406) cascades the storage backplane 2 (1407), the voltage detected by the CPLD (14061) through the presence pin may be 0V, at which time it may be determined that the storage backplane 1 (1406) cascades another storage backplane. It should be understood that the cascade of presence signal lines shown in fig. 14C is illustrative only and not limiting.

The board_id signal line is mainly used for setting the identification code of the storage backboard by the CPLD on the storage backboard, and generally includes 1 or more signal lines, see fig. 14D, and fig. 14D is a schematic diagram of a cascade of board_id signal lines according to an embodiment of the present application. As shown in fig. 14D, the first circuit board 1405 may include a power supply VDD and a resistor R5 thereon, the storage backplate 1 (1406) may include a resistor R6 thereon, when the first circuit board 1405 cascades the storage backplate 1 (1406), first ends of the resistor R5 and the resistor R6 are connected to VDD, and second ends of the resistor R5 and the resistor R6 are grounded. Wherein, two Board_ID pins of CPLD (14061) can be respectively connected with the second end of resistor R5 and the first end of resistor R6, and the detected voltages can be respectively 0V and VDD.0V is low 0 and VDD is high 1, at which time CPLD (14061) can determine that the Board_ID of the storage backplane where it is located is 01, that is, that of storage backplane 1 (1406) is 01. After the CPLD (14061) determines the board_id of the storage backplane where it is located, the board_id may be sent to the CPLD on the storage backplane of the next cascade, that is, the CPLD (14071) on the storage backplane 2 (1407), and the CPLD (14071) may add 1 as the board_id of the storage backplane where it is located on the basis of the received board_id value, and may determine the board_id of the storage backplane 2 (1407) to be 10. Similarly, the CPLD (14071) may send the board_id of the storage backplane of itself to the CPLD on the next cascaded storage backplane, that is, the CPLD (14081) on the storage backplane 3 (1408), and the CPLD (14081) may add 1 to the received board_id value as the board_id of the storage backplane of itself, so as to determine that the board_id of the storage backplane 3 (1408) is 11. Note that the arrangement of the board_id signal line in fig. 14D is merely illustrative, and is not limited to this configuration. In other embodiments of the application, more or fewer devices may be used, and different connection relationships may be used.

It should be understood that, in the above management bus cascade, the CPLD on the storage backplane needs to perform forwarding of data (such as forwarding of I2C data, JTAG data, etc.), interaction of upper and lower-level backplane information, and the like.

Next, a case where the downstream interface of the storage backplane includes both the high-speed signal interface and the management signal interface will be described, with reference to fig. 15, and fig. 15 is a schematic structural diagram of another storage backplane according to an embodiment of the present disclosure. As shown in fig. 15, the storage backplane 1500 may include an upstream interface 1501 and a downstream interface 1502. The upstream interface 1501 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a management signal interface and a high-speed signal interface.

The management signal interface in the upstream interface 1501 of the storage backplane 1500 may be connected with the management signal interface in the downstream interface 1502 so that transmission of management signals between the upstream and downstream interfaces may be accomplished. Meanwhile, the high-speed signal interface in the upstream interface 1501 of the storage backplane 1500 may be connected with the high-speed signal interface in the downstream interface 1502, so that transmission of high-speed signals between the upstream interface and the downstream interface may be achieved. The specific connection relationship between the high-speed signal interface in the upstream interface 1501 and the high-speed signal interface in the downstream interface 1502 of the storage backplane 1500 is the same as the case that the downstream interface of the storage backplane includes only the high-speed signal interface, and the related description will be referred to and will not be repeated herein. The specific connection relationship between the management signal interface in the upstream interface 1501 and the management signal interface in the downstream interface 1502 of the storage backplane 1500 is the same as the case where the downstream interface of the storage backplane includes only the management signal interface, and the related description is referred to and will not be repeated here.

The cascade of storage backplanes including both high-speed signal interfaces and management signal interfaces at the downstream interface of the storage backplanes is exemplified below. Referring to fig. 16, fig. 16 is a schematic structural diagram of another computing device according to an embodiment of the present application. As shown in fig. 16, the computing device 1600 may include a first circuit board 1601, on which may be included expansion interface 1 (16011), expansion interface 2 (16012), and expansion interface 3 (16013). Among them, the expansion interface 1 (16011) may include a high-speed signal interface, a power signal interface, and a management signal interface, and the expansion interface 2 (16012) and the expansion interface 3 (16013) may include a power signal interface. When the storage backplane 1 (1602) needs to be expanded for the computing device 1600, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 16021 of the storage backplane 1 (1602) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the expansion interface 1 (16011) on the first circuit board 1601. When it is also desired to extend the storage backplane 2 (1603) for the computing device 1600, the power signal interface in the upstream interface 16031 of the storage backplane 2 (1603) may be correspondingly connected to the power signal interface in the extension interface 2 (16012) on the first circuit board 1601, and the management signal interface and the high-speed signal interface in the upstream interface 16031 of the storage backplane 2 (1603) may be correspondingly connected to the management signal interface and the high-speed signal interface in the downstream interface 16022 of the storage backplane 1 (1602). When it is also desired to extend the storage backplane 3 (1604) for the computing device 1600, the power signal interface in the upstream interface 16041 of the storage backplane 3 (1604) may be correspondingly connected to the power signal interface in the extension interface 3 (16013) on the first circuit board 1601, and the management signal interface and the high-speed signal interface in the upstream interface 16041 of the storage backplane 3 (1604) may be correspondingly connected to the management signal interface and the high-speed signal interface in the downstream interface 16032 of the storage backplane 2 (1603).

It should be noted that, in some embodiments, the power signal interfaces in the expansion interface 1 (16011), the expansion interface 2 (16012), and the expansion interface 3 (16013) on the first circuit board may be the same power signal interface. Specifically, since the same output voltage can supply power to multiple loads (such as storage backplanes) connected in parallel, one power signal interface on the first circuit board can supply power to multiple storage backplanes connected in parallel through a plurality of cables.

Therefore, the management signal interface and the high-speed signal interface can be reserved on the first circuit board, and the management signal interface and the high-speed signal interface do not need to be reserved for each storage backboard, so that the number of the management signal interfaces and the high-speed signal interfaces on the first circuit board can be reduced, and the wiring difficulty of the first circuit board can be further reduced.

Next, a case where the downstream interface of the storage backplane includes both a high-speed signal interface and a power signal interface will be described, with reference to fig. 17, and fig. 17 is a schematic structural diagram of another storage backplane according to an embodiment of the present disclosure. As shown in fig. 17, the storage backplane 1700 may include an upstream interface 1701 and a downstream interface 1702. The upstream interface 1701 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a power signal interface and a high-speed signal interface.

The power signal interface in the upstream interface 1701 of the storage backplane 1700 may be connected with the power signal interface in the downstream interface 1702 so that transmission of power signals between the upstream interface and the downstream interface may be accomplished. Meanwhile, a high-speed signal interface in the upstream interface 1701 of the storage backplane 1700 may be connected with a high-speed signal interface in the downstream interface 1702, so that transmission of high-speed signals between the upstream interface and the downstream interface may be achieved. The specific connection relationship between the high-speed signal interface in the upstream interface 1701 and the high-speed signal interface in the downstream interface 1702 of the storage backplane 1700 is the same as the case where the downstream interface of the storage backplane includes only the high-speed signal interface, and the related description will be referred to and will not be repeated herein. The specific connection relationship between the power signal interface in the upstream interface 1701 and the power signal interface in the downstream interface 1702 of the storage backplane 1700 is the same as the case where the downstream interface of the storage backplane includes only the power signal interface, and the description thereof will be referred to above and will not be repeated here.

A cascade of memory backplanes comprising both a high-speed signal interface and a power signal interface at the downstream interface of the memory backplane is exemplarily described below. Referring to fig. 18, fig. 18 is a schematic structural diagram of another computing device according to an embodiment of the present application. As shown in fig. 18, the computing device 1800 may include a first circuit board 1801, and the first circuit board 1801 may include an expansion interface 1 (18011), an expansion interface 2 (18012), and an expansion interface 3 (18013) thereon. Among them, the expansion interface 1 (18011) may include a high-speed signal interface, a power signal interface, and a management signal interface, and the expansion interface 2 (18012) and the expansion interface 3 (18013) may include a management signal interface. When it is desired to extend the storage backplane 1 (1802) for the computing device 1800, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 18021 of the storage backplane 1 (1802) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the extension interface 1 (18011) on the first circuit board 1801. When the storage backplane 2 (1803) also needs to be expanded for the computing device 1800, the management signal interface in the upstream interface 18031 of the storage backplane 2 (1803) may be correspondingly connected to the management signal interface in the expansion interface 2 (18012) on the first circuit board 1801, and the power signal interface and the high-speed signal interface in the upstream interface 18031 of the storage backplane 2 (1803) may be correspondingly connected to the power signal interface and the high-speed signal interface in the downstream interface 18022 of the storage backplane 1 (1802). When it is also desired to extend the storage backplane 3 (1804) for the computing device 1800, the management signal interface in the upstream interface 18041 of the storage backplane 3 (1804) may be correspondingly connected to the management signal interface in the expansion interface 3 (18013) on the first circuit board 1801, and the power signal interface and the high-speed signal interface in the upstream interface 18041 of the storage backplane 3 (1804) may be correspondingly connected to the power signal interface and the high-speed signal interface in the downstream interface 18032 of the storage backplane 2 (1803).

Therefore, the power signal interface and the high-speed signal interface can be reserved on the first circuit board, and the power signal interface and the high-speed signal interface do not need to be reserved for each storage backboard, so that the number of the power signal interfaces and the high-speed signal interfaces on the first circuit board can be reduced, the wiring difficulty of the first circuit board can be reduced, and the cost is saved.

Next, a case where the downstream interface of the storage backplane includes both the management signal interface and the power signal interface will be described, referring to fig. 19, fig. 19 is a schematic structural diagram of another storage backplane according to an embodiment of the present disclosure. As shown in fig. 19, the storage backplane 1900 may include an upstream interface 1901 and a downstream interface 1902. The upstream interface 1901 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a power signal interface and a management signal interface.

The power signal interface in the upstream interface 1901 of the storage backplane 1900 may be connected to the power signal interface in the downstream interface 1902 so that transmission of power signals between the upstream and downstream interfaces may be accomplished. Meanwhile, a management signal interface in the upstream interface 1901 of the storage backplane 1900 may be connected with a management signal interface in the downstream interface 1902, so that transmission of management signals between the upstream interface and the downstream interface may be achieved. The specific connection relationship between the management signal interface in the upstream interface 1901 and the management signal interface in the downstream interface 1902 of the storage backplane 1900 is the same as the case where the downstream interface of the storage backplane includes only the management signal interface, and the related description may be referred to and will not be repeated herein. The specific connection relationship between the power signal interface in the upstream interface 1901 and the power signal interface in the downstream interface 1902 of the storage backplane 1900 is the same as the case where the downstream interface of the storage backplane includes only the power signal interface, and the description thereof will be referred to above and will not be repeated herein.

The cascade of memory backplanes comprising both management signal interfaces and power signal interfaces at the downstream interface of the memory backplane is exemplarily described below. Referring to fig. 20, fig. 20 is a schematic structural diagram of still another computing device according to an embodiment of the present application. As shown in fig. 20, the computing device 2000 may include a first circuit board 2001, and the first circuit board 2001 may include an expansion interface 1 (20011), an expansion interface 2 (20012), and an expansion interface 3 (20013) thereon. Among them, the expansion interface 1 (20011) may include a high-speed signal interface, a power signal interface, and a management signal interface, and the expansion interface 2 (20012) and the expansion interface 3 (20013) may include a high-speed signal interface. When the storage backplane 1 (2002) needs to be extended for the computing device 2000, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 20021 of the storage backplane 1 (2002) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the extension interface 1 (20011) on the first circuit board 2001. When the storage backplane 2 (2003) also needs to be extended for the computing device 2000, the high-speed signal interface in the upstream interface 20031 of the storage backplane 2 (2003) may be correspondingly connected to the high-speed signal interface in the extension interface 2 (20012) on the first circuit board 2001, and the power signal interface and the management signal interface in the upstream interface 20031 of the storage backplane 2 (2003) may be correspondingly connected to the power signal interface and the management signal interface in the downstream interface 20022 of the storage backplane 1 (2002). When it is also desired to extend the storage backplane 3 (2004) for the computing device 2000, the high-speed signal interface in the upstream interface 20041 of the storage backplane 3 (2004) may be correspondingly connected to the high-speed signal interface in the extension interface 3 (20013) on the first circuit board 2001, and the power signal interface and the management signal interface in the upstream interface 20041 of the storage backplane 3 (2004) may be correspondingly connected to the power signal interface and the management signal interface in the downstream interface 20032 of the storage backplane 2 (2003).

Therefore, the power signal interface and the management signal interface can be reserved on the first circuit board, and the power signal interface and the management signal interface do not need to be reserved for each storage backboard, so that the number of the power signal interfaces and the management signal interfaces on the first circuit board can be reduced, the wiring difficulty of the first circuit board can be reduced, and the cost is saved.

Next, a case where the downstream interface of the storage backplane includes a high-speed signal interface, a management signal interface, and a power signal interface is described, referring to fig. 21, fig. 21 is a schematic structural diagram of another storage backplane according to an embodiment of the present disclosure. As shown in fig. 21, the storage backplane 2100 may include an upstream interface 2101 and a downstream interface 2102. The upstream interface 2101 may include a high-speed signal interface, a management signal interface, and a power signal interface, and the downstream interface 1502 may include a high-speed signal interface, a management signal interface, and a power signal interface.

The power signal interface in the upstream interface 2101 of the storage backplane 2100 may be connected with the power signal interface in the downstream interface 2102 so that transmission of power signals between the upstream interface and the downstream interface may be achieved. The high-speed signal interface in the upstream interface 2101 of the storage backplane 2100 may be connected with the high-speed signal interface in the downstream interface 2102 so that transmission of high-speed signals between the upstream interface and the downstream interface may be achieved. The management signal interface in the upstream interface 2101 of the storage backplane 2100 may be connected with the management signal interface in the downstream interface 2102 so that transmission of management signals between the upstream interface and the downstream interface may be achieved. The specific connection relationship between the management signal interface in the upstream interface 2101 and the management signal interface in the downstream interface 2102 of the storage backplane 2100 is the same as the case where the downstream interface of the storage backplane includes only the management signal interface, and the related description is referred to and will not be repeated here. The specific connection relationship between the power signal interface in the upstream interface 2101 and the power signal interface in the downstream interface 2102 of the storage backplane 2100 is the same as the case where the downstream interface of the storage backplane includes only the power signal interface, and the related description is referred to and will not be repeated here. The specific connection relationship between the high-speed signal interface in the upstream interface 2101 and the high-speed signal interface in the downstream interface 2102 of the storage backplane 2100 is the same as the case where the downstream interface of the storage backplane includes only the high-speed signal interface, and the related description is referred to and will not be repeated here.

The cascade of memory backplanes including both a high-speed signal interface, a management signal interface, and a power signal interface is illustrated below as a downstream interface of the memory backplane. Referring to fig. 22, fig. 22 is a schematic structural diagram of another computing device according to an embodiment of the present application. As shown in fig. 22, the computing device 2200 may include a first circuit board 2201, and the first circuit board 2201 may include an expansion interface 1 (22011) thereon, and the expansion interface 1 (22011) may include a high-speed signal interface, a power signal interface, and a management signal interface. When it is desired to extend the storage backplane 1 (2202) for the computing device 2200, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 22021 of the storage backplane 1 (2202) may be respectively connected to the high-speed signal interface, the power signal interface, and the management signal interface in the extension interface 1 (22011) on the first circuit board 2201. When it is also desired to extend storage backplane 2 (2203) for computing device 2200, the high-speed signal interface, power signal interface, and management signal interface in upstream interface 22031 of storage backplane 2 (2203) may be correspondingly connected to the high-speed signal interface, power signal interface, and management signal interface in downstream interface 22022 of storage backplane 1 (2202). When it is also desired to extend the storage backplane 3 (2204) for the computing device 2200, the high-speed signal interface, the power signal interface, and the management signal interface in the upstream interface 22041 of the storage backplane 3 (2204) may be correspondingly connected to the high-speed signal interface, the power signal interface, and the management signal interface in the downstream interface 22032 of the storage backplane 2 (2203).

Therefore, the management signal interface, the power signal interface and the high-speed signal interface can be reserved on the first circuit board, and the management signal interface, the power signal interface and the high-speed signal interface are not required to be reserved for each storage backboard, so that the number of the management signal interface, the power signal interface and the high-speed signal interface on the first circuit board can be reduced, the wiring difficulty of the first circuit board can be further reduced, and the cost is saved.

It should be noted that, the connection of the interfaces between the first circuit board and the storage back board and the connection of the interfaces between the different storage back boards are mainly used for conducting signals, and do not convert the signals. For example, the high-speed signal interface in the downstream interface 9022 of the storage backplane 1 (902) and the high-speed signal interface in the upstream interface 9031 of the storage backplane 2 (903) in fig. 9 may be connected, and the high-speed signal received by the high-speed signal interface in the downstream interface 9022 may be conducted to the high-speed signal interface in the upstream interface 9031, or the high-speed signal received by the high-speed signal interface in the upstream interface 9031 may be conducted to the high-speed signal interface in the downstream interface 9022. For another example, the management signal interface in the downstream interface 11022 of the storage backplane 1 (1102) and the management signal interface in the upstream interface 11031 of the storage backplane 2 (1103) in fig. 11 may be connected, and the management signal received by the management signal interface in the downstream interface 11022 may be transferred to the management signal interface in the upstream interface 11031, or the management signal received by the management signal interface in the upstream interface 11031 may be transferred to the management signal interface in the downstream interface 11022.

It will be appreciated that the high-speed signal interface, the power signal interface, and the management signal interface on the first circuit board are typically connected to the high-speed signal interface, the power signal interface, and the management signal interface on the storage backplane by cables, and in the computing device, the distance between the first circuit board and the storage backplane is typically set to be relatively long, so that a plurality of cables with relatively long lengths are typically required to implement the connection. When multiple storage backplates are cascaded, the distance between the multiple storage backplates is generally relatively short, and even in some embodiments, the storage backplates can be directly spliced together, so that the cable length inside the computing device can be greatly reduced. In the embodiment of the present application, the connection manner between the components is not limited, and various manners such as cable and direct insertion may be used.

In some embodiments, the last storage backplane of the cascade may not include downstream interfaces, which may reduce the number of overall power signal interfaces, high-speed signal interfaces, management signal interfaces. For example, the storage backplane 604 of fig. 6 described above may not include the downstream interface 6042, and the corresponding power signal interface may be reduced. For another example, the storage backplane 904 in fig. 9 described above may not include the downstream interface 9042, and the corresponding high-speed signal interface may be reduced.

It should be understood that, based on the above 7 types of storage backplanes, in practical situations, the use of the storage backplanes is flexible and changeable, and the same type of storage backplanes (such as storage backplanes each including only a power signal interface by using a downstream interface) may be used for cascading, or multiple types of storage backplanes (such as storage backplanes including only a power signal interface by using a downstream interface and storage backplanes including both a high-speed signal interface and a power signal interface by using a downstream interface) may be used for cascading. In addition, the cascade mode is flexible and changeable, for example, the power signal interface in the upstream interface of one storage backboard can be connected with the power signal interface in the downstream interface of the other storage backboard, and also can be connected with the power signal interface on the first circuit board. For another example, the power signal interface, the high-speed signal interface, and the management signal interface in the upstream interface of one storage backplane may be connected to the power signal interface, the high-speed signal interface, and the management signal interface in the downstream interface of 3 different storage backplanes, respectively.

In addition, in an actual scene, the most suitable storage backboard can be selected according to the storage requirement to be cascaded. For example, assume that there are currently 3 types of storage backplanes, storage backplanes a, storage backplanes b, and storage backplanes c, where storage backplane a may support 8 hard disks, storage backplane b may support 4 hard disks, and storage backplane c may support 2 hard disks. If the customer's demand is 16 hard disks, then two storage backplanes a may be selected to be cascaded. If the customer's demand is 12 hard disks, then one storage backplane a and one storage backplane b may be selected for cascading. If the customer's demand is 6 hard disks, then one storage backplane b and one storage backplane c may be selected for cascading. The three modes can meet the requirements of users, new storage back plates do not need to be developed according to the requirements of the users, and expansion can be completed by using the existing storage back plates. And moreover, different storage backplates can be cascaded to be suitable for various different scenes, so that the flexibility and the practicability are high.

An exemplary description of the cascading use of storage backplanes follows. When the system or the computing device requires less storage capacity or storage disk, 1 storage backboard can be selected, and cascading is not performed. As shown in fig. 23, it is assumed that the system is required to support 8 hard disks, at this time, only the storage backplane 1 (2300) may be extended, and its downstream interface may include both a management signal interface and a power signal interface. Specifically, the management signal interface in the upstream interface of the storage backplane 1 (2300) may be a low-speed signal connector 2301, which may connect motherboard management signals, and the power signal interface in the upstream interface of the storage backplane 1 (2300) may be a power connector 2302, which may connect motherboard power signals. The management signal interface in the downstream interface of the storage backplane 1 (2300) may be a low-speed signal connector 2303, which has a corresponding connection relationship (not illustrated in fig. 23) with the low-speed signal connector 2301, and the low-speed signal connector 2301 also has a corresponding connection relationship (not illustrated in fig. 23) with other components (e.g., CPLD, storage interface) on the storage backplane 1 (2300). The power signal interface in the downstream interface of the storage backplane 1 (2300) may be a power connector 2304, which has a corresponding connection relationship (not illustrated in fig. 23) with the power connector 2302, and the power connector 2302 also has a corresponding connection relationship (not illustrated in fig. 23) with other components (such as a CPLD, a storage interface) on the storage backplane 1 (2300) to supply power to the CPLD, a hard disk connected to the storage interface, and the like. The high speed signal interfaces in the upstream interface of the storage backplane 1 (2300) may be an SLM X4 (Slimline X4) connector 2305 and an SLM X4 connector 2306, which may connect motherboard high speed signals (e.g., PCIe signals). SLM X4 (Slimline X4) connector 2305 and SLM X4 connector 2306 may connect to a memory interface on memory backplane 1 (2300), for example, SLM X4 connector 2306 may connect to corresponding high speed signal pins on memory interface 2307.

When the system or computing device requires more storage capacity or storage disk, a 2-level, 3-level, or more storage backplane cascade may be performed to achieve a smooth upgrade of the storage system capacity specification. As shown in fig. 24, assuming that the system is required to support 16 hard disks, the same storage backplane can be cascaded on the basis of fig. 23, and at this time, the storage backplane 1 (2300) and the storage backplane 2 (2400) can be extended. Specifically, the management signal interface in the upstream interface of the storage backplane 2 (2400) may be a low-speed signal connector 2401, which may be connected to a low-speed signal connector 2303 on the storage backplane 1 (2300) to enable inter-board transmission of management signals. Similarly, the power signal interface in the upstream interface of storage backplane 2 (2400) may be power connector 2402, which may be connected to power connector 2304 on storage backplane 1 (2300) to enable inter-board transmission of power signals. There is a corresponding connection relationship (not shown in fig. 24) between the low-speed signal connector 2403 and the low-speed signal connector 2401 on the storage backplane 2 (2400), and there is a corresponding connection relationship (not shown in fig. 24) between the low-speed signal connector 2401 and other components (e.g., CPLD, storage interface) on the storage backplane 2 (2400). There is a corresponding connection relationship (not shown in fig. 24) between the power connector 2404 and the power connector 2402 on the storage back plane 2 (2400), and there is a corresponding connection relationship (not shown in fig. 24) between the power connector 2402 and other components (e.g., CPLD, storage interface) on the storage back plane 2 (2400). The high speed signal interface in the upstream interface of the storage backplane 2 (2400) may be an SLM X4 (Slimline X4) connector 2405 and an SLM X4 connector 2406, which may connect motherboard high speed signals. The SLM X4 (Slimline X4) connector 2405 and SLM X4 connector 2406 may connect to a memory interface on the memory backplane 2 (2400), for example, the SLM X4 connector 2406 may connect to corresponding high speed signal pins on the memory interface 2407. Therefore, when the multiple storage backplanes are cascaded in fig. 24, the requirements for the power connector and the low-speed signal connector on the motherboard are unchanged, the motherboard does not need to be redesigned, and the practicability and the flexibility are high.

It should be noted that fig. 1-24 are only exemplary, and the embodiments of the present application are not limited thereto. Also, it is understood that some of the drawings in fig. 1 to 24 omit some connection relationships for convenience of description, but those skilled in the art can understand complete connection relationships in combination with the related art and the drawings provided by the present application. For example, for fig. 3, the storage backplane 300 may include a storage interface, and the storage interface included in the storage backplane 300 may be correspondingly connected with a high-speed signal interface, a management signal interface, and a power signal interface in the upstream interface 301 (not shown in fig. 3). For another example, for fig. 8, the storage backplane 700 may further include a storage interface that is correspondingly connected to the power signal interface and the management signal interface in the upstream interface 701 (not shown in fig. 8).

In the implementation manner, flexible expansion of a plurality of storage backplanes can be realized through cascading of the upstream interface and the downstream interface between the storage backplanes. In an actual scene, the number of the storage backplates and the types of the storage backplates can be flexibly configured according to the storage capacity of actual needs, the storage backplates do not need to be newly developed according to new storage requirements, the types of the backplates can be reduced, and the maintenance cost of products and systems is reduced. Moreover, by adopting the cascading mode, the numbers of the high-speed signal interfaces, the power signal interfaces, the management signal interfaces and the PCIe expansion interfaces reserved on the first circuit board can be correspondingly reduced, but various storage requirements can be compatible, and the development difficulty of the first circuit board can be reduced.

It should be noted that, the related information (i.e., the same information or similar information) and the related description in the above different embodiments may refer to each other.

It is to be understood that "connected" in the present application may be understood as directly connected (i.e., electrically connected); it is also to be understood that the connection is indirect, i.e., through other devices, elements, modules, means, etc.

The technical terms used in the embodiments of the present application are only used to illustrate specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, as used in the specification, the terms "comprises" and/or "comprising" mean that there is a stated feature, integer, step, operation, element, and/or component, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components.

It should also be understood that in various embodiments of the present application, "at least one", "one or more" means one, two or more. The term "and/or" is used to describe an association relationship of associated objects, meaning that there may be three relationships; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other specifically claimed elements. The description of the present application has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the application in the form disclosed.

The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present application in further detail, and are not to be construed as limiting the scope of the application, but are merely intended to cover any modifications, equivalents, improvements, etc. based on the teachings of the application.

Claims

1. The signal transmission circuit is characterized by comprising a first circuit board, a first storage backboard and a second storage backboard; the first circuit board comprises a first expansion interface; the first storage backboard comprises a first upstream interface and a first downstream interface, and the first upstream interface is connected with the first downstream interface; the second storage backplane includes a second upstream interface; the first upstream interface is connected with the first expansion interface; the second upstream interface is connected with the first downstream interface; or, the first circuit board further includes a second expansion interface, and the second upstream interface is connected with the first downstream interface and the second expansion interface respectively.

2. The signal transmission circuit of claim 1, further comprising a third storage backplane, the third storage backplane comprising a third upstream interface; the second storage backplane further comprises a second downstream interface; the third upstream interface is connected with the second downstream interface; or, the first circuit board further includes a third expansion interface, and the third upstream interface is connected with the second downstream interface and the third expansion interface respectively.

3. The signal transmission circuit of claim 1 or 2, wherein the first expansion interface comprises a first high-speed signal interface, a first management signal interface, and a first power signal interface; the second expansion interface comprises at least one of a second high-speed signal interface, a second management signal interface and a second power supply signal interface; the first upstream interface and the second upstream interface comprise a high-speed signal interface, a management signal interface and a power signal interface, and the first downstream interface comprises at least one of the high-speed signal interface, the management signal interface and the power signal interface;

if the first downstream interface comprises a high-speed signal interface, a management signal interface and a power signal interface, the high-speed signal interface, the management signal interface and the power signal interface in the first downstream interface are correspondingly connected with the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface and the high-speed signal interface, the management signal interface and the power signal interface in the second upstream interface respectively;

If the first downstream interface includes any one or any two interfaces of a high-speed signal interface, a management signal interface and a power signal interface, any one or any two interfaces of the first downstream interface are respectively connected with a corresponding one or two interfaces of the high-speed signal interface, the management signal interface and the power signal interface in the first upstream interface and a corresponding one or two interfaces of the high-speed signal interface, the management signal interface and the power signal interface in the second upstream interface, and the other interfaces in the second upstream interface are connected with a corresponding interface of the second high-speed signal interface, the second management signal interface and the second power signal interface in the second expansion interface.

4. The signal transmission circuit of claim 3, wherein the first memory backplane further comprises an expansion chip, the expansion chip comprising an upstream interface and a downstream interface, a high-speed signal interface in the first upstream interface being connected with the upstream interface of the expansion chip;

if the first downstream interface comprises a high-speed signal interface, the expansion chip comprises at least two downstream interfaces, one of the downstream interfaces of the expansion chip is connected with the high-speed signal interface in the first downstream interface, and the other downstream interfaces of the expansion chip are connected with the storage interfaces of the first storage backboard;

If the first downstream interface does not comprise a high-speed signal interface, the downstream interface of the expansion chip is connected with the storage interface of the first storage backboard; the storage interface is used for connecting with a storage disk.

5. The signal transmission circuit of claim 3 or 4, wherein the first storage backplane further comprises a backplane controller, the backplane controller being coupled to a management signal interface in the first upstream interface if the first downstream interface comprises a management signal interface, the backplane controller being further coupled to a management signal interface in the first downstream interface.

6. The signal transmission circuit of any one of claims 3-5, wherein the first storage backplane further comprises a voltage regulation module, a power signal interface in the first upstream interface being connected to an input of the voltage regulation module, an output of the voltage regulation module being configured to power a component on the first storage backplane.

7. The signal transmission circuit of any one of claims 3-6, wherein the first high speed signal interface of the first circuit board further comprises a peripheral component interconnect express PCIe interface for connecting PCIe devices.

8. The signal transmission circuit of any one of claims 2-7, wherein the second downstream interface comprises at least one of a high speed signal interface, a management signal interface, and a power signal interface;

if the second downstream interface comprises a high-speed signal interface, the high-speed signal interface in the second downstream interface is connected with the high-speed signal interface in the second upstream interface;

if the second downstream interface comprises a management signal interface, the management signal interface in the second downstream interface is connected with the management signal interface in the second upstream interface;

and if the second downstream interface comprises a power signal interface, the power signal interface in the second downstream interface is connected with the power signal interface in the second upstream interface.

9. A computing device comprising the signal transmission circuit of any of claims 1-8.

10. A storage backplane, wherein the storage backplane comprises an upstream interface and a downstream interface, the upstream interface comprising a high-speed signal interface, a management signal interface, and a power signal interface, the downstream interface comprising at least one of the high-speed signal interface, the management signal interface, and the power signal interface;

If the downstream interface of the storage backboard comprises a high-speed signal interface, the high-speed signal interface in the downstream interface is connected with the high-speed signal interface in the upstream interface;

if the downstream interface of the storage backboard comprises a management signal interface, the management signal interface in the downstream interface is connected with the management signal interface in the upstream interface;

if the downstream interface of the storage backboard comprises a power signal interface, the power signal interface in the downstream interface is connected with the power signal interface in the upstream interface.