CN113609035B - Device and method for realizing fool-proof of hard disk backboard cable - Google Patents

Device and method for realizing fool-proof of hard disk backboard cable Download PDF

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Publication number
CN113609035B
CN113609035B CN202110730344.8A CN202110730344A CN113609035B CN 113609035 B CN113609035 B CN 113609035B CN 202110730344 A CN202110730344 A CN 202110730344A CN 113609035 B CN113609035 B CN 113609035B
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connector
hard disk
signal
speed switching
switching unit
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CN113609035A (en
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邹志鑫
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/325—Display of status information by lamps or LED's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application relates to a device and a method for realizing fool-proof of a hard disk backboard cable. Wherein the device comprises: a main board configured with a first CPU connected to the third connector and the fourth connector, a second CPU connected to the fifth connector and the sixth connector, and a recognition signal circuit connected to the third connector, the fourth connector, the fifth connector and the sixth connector; the hard disk backboard is provided with a control unit connected with the first connector and the second connector; a first selection unit connected to the first connector and the control unit, a first high-speed switching unit connected to the first connector and the first selection unit; a second selection unit connected to the second connector and the control unit, a second high-speed switching unit connected to the second connector and the second selection unit; the output end of the first high-speed switching unit and the corresponding output end of the second high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk. The design of preventing foolproof that is connected between hard disk backplate and the mainboard can be realized to this application.

Description

Device and method for realizing fool-proof of hard disk backboard cable
Technical Field
The application relates to the field of hard disk backboard connection design, in particular to a device and a method for realizing foolproof of a hard disk backboard cable.
Background
In the server, one server CPU can mount a plurality of hard disks. In order to ensure that the storage capacity of the server is often designed to be a plurality of hard disks, in order to facilitate the maintenance and management of the hard disks in the server, a plurality of hard disks are often concentrated on a hard disk backboard, and then the hard disk backboard is connected with a server main board.
The hard disk backboard and the server main board are symmetrical in design by adopting the interconnection interface, the problem of connection error is easy to generate when the hard disk backboard is connected to the server main board, and once the interface between the hard disk backboard and the main board is connected in error, disorder of the disk sequence of the hard disk can be caused, and adverse effects can be caused on operation of the server and maintenance and management of the later hard disk. In the prior art, the problem of interface misconnection cannot be thoroughly solved by indicating the mode that the hard disk interface and the main board interface are connected incorrectly through the indicating lamp through the label, and the hard disk sequence is disordered once misconnection is caused.
Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the device and the method for realizing foolproof of the hard disk backboard cable are provided.
In a first aspect, the present application provides a device for implementing fool-proofing of a hard disk backboard cable, including:
the main board is provided with at least one group of first CPU and second CPU, the first CPU is connected with the third connector and the fourth connector, the second CPU is connected with the fifth connector and the sixth connector, and the third connector, the fourth connector, the fifth connector and the sixth connector are connected with the identification signal circuit;
the hard disk backboard is provided with a first connector and a second connector which are connected with the main board, pins of the first connector and the second connector which are connected with the identification signal circuit are connected with the control unit, and the control unit is controlled to be connected with the first selection unit and the second selection unit; the first connector pin connected with the identification signal circuit is connected with the first selection unit, the second connector pin connected with the identification signal circuit is connected with the second selection unit, the first selection unit is controlled to be connected with the first high-speed switching unit, and the second selection unit is controlled to be connected with the second high-speed switching unit;
the first connector is connected with the input end of the first high-speed switching unit, and the second connector is connected with the input end of the second high-speed switching unit; the four output ends of the first high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk.
Still further, the first connector and the second connector include a third identification pin and a fourth identification pin, respectively, the third identification pin and the fourth identification pin being connected to an identification signal circuit.
Still further, the third, fourth, fifth and sixth connectors comprise first and second identification pins, respectively; the first and second identification pins correspond to the third and fourth identification pins, respectively.
Further, the identification signal circuit includes a low level circuit and a high level circuit;
a first identification pin of the third connector and the fourth connector is connected with a low-level circuit;
a first identification pin of the fifth connector and the sixth connector is connected with a high-level circuit;
a second identification pin of the third connector and the fifth connector is connected with a low-level circuit;
the second identification pins of the fourth connector and the sixth connector are connected with a high-level circuit.
Further, the third connector is connected to the low-order output of the first CPU, the fourth connector is connected to the high-order output of the first CPU, the fifth connector is connected to the low-order output of the second CPU, and the sixth connector is connected to the high-order output of the second CPU.
Further, the first selecting unit and the second selecting unit each include two signal input ports, a signal output port and a control port; the signal output of one signal input port is selected by the control signal output port according to the input signal of the control port;
two signal input ports of the first selection unit are respectively connected with a third identification pin and a fourth identification pin of the first connector; two signal input ends of the second selection unit are respectively connected with a third identification pin and a fourth identification pin of the second connector;
the control ports of the first selection unit and the second selection unit are respectively connected with the control unit;
and signal output ports of the first selection unit and the second selection unit are respectively connected with the first high-speed switching unit and the second high-speed switching unit.
Further, the first high-speed switching unit and the second high-speed switching unit each include a high-bandwidth input end, four low-bandwidth output ends and a control signal port, wherein the four output ends include an output end A1, an output end A2, an output end B1 and an output end B2; the signal control output end A1 and the output end A2 of the control signal port are used for combining and outputting the signal of the input end or the signal control output end B1 and the signal control output end B2 are used for combining and outputting the signal of the input end;
the input end of the first high-speed switching unit is connected with a first connector, and the input end of the second high-speed switching unit is connected with a second connector;
the control signal end of the first high-speed switching unit is connected with the signal output port of the first selecting unit; the control signal end of the second high-speed switching unit is connected with the signal output port of the second selecting unit;
the output ends A1 of the first high-speed switching unit and the second high-speed switching unit are connected with the first hard disk;
the output ends A2 of the first high-speed switching unit and the second high-speed switching unit are connected with the second hard disk;
the output ends B1 of the first high-speed switching unit and the second high-speed switching unit are connected with the third hard disk;
and the output ends B2 of the first high-speed switching unit and the second high-speed switching unit are both connected with the fourth hard disk.
Furthermore, the control unit is electrically connected with a plurality of indicator lamps, and the control unit controls the indicator lamps according to the received identification signals.
In a second aspect, the present application provides a method for implementing fool-proofing of a hard disk backboard cable, which is applied to the apparatus for implementing fool-proofing of a hard disk backboard cable, including:
when signals at the input ends of the first high-speed switching unit and the second switching unit are sourced from the same CPU, the low-order output of the CPU corresponds to the first hard disk and the second hard disk, and the high-order output of the CPU corresponds to the third hard disk and the fourth hard disk;
when signals at the input ends of the first high-speed switching unit and the second switching unit are sourced from the first CPU and the second CPU, the output of the first CPU corresponds to the first hard disk and the second hard disk, and the output of the second CPU corresponds to the third hard disk and the fourth hard disk.
Further, the control unit detects whether the signal of the third identification pin of the first connector and the signal of the third identification pin of the second connector are identical,
if the first identification pin is the same as the second identification pin, a first signal is sent to a first selection unit and a second selection unit, so that the first selection unit sends a signal of a fourth identification pin of a first connector to the first high-speed switching unit, and the second selection unit sends a signal of a fourth identification pin of a second connector to the second high-speed switching unit;
and if the first identification pin is different from the second identification pin, sending a second signal to the first selection unit and the second selection unit, so that the first selection unit sends the signal of the third identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends the signal of the third identification pin of the second connector to the second high-speed switching unit.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the third connector, the fourth connector, the fifth connector and the sixth connector which are connected with the first CPU and the second CPU on the main board are identified through the identification signal circuit; the identification signal circuit transmits four different identification signals to the control unit on the hard disk backboard through the third connector, the fourth connector, the fifth connector and the sixth connector respectively.
When the first connector and the second connector on the hard disk backboard are connected to the main board, the control unit receives two of four identification signals, the control unit controls the first selection unit and the second selection unit according to the identification signals, and then the first selection unit and the second selection unit respectively control the first high-speed switching unit and the second high-speed switching unit to realize foolproof design of connection between the hard disk backboard and the main board, so that the backboard hard disk can still ensure that the disk sequence of the hard disk is unchanged under the condition of reverse connection.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a hard disk back plate according to an embodiment of the present application;
FIG. 2 is a signal source table of a first hard disk, a second hard disk, a third hard disk and a fourth hard disk according to an embodiment of the present application;
fig. 3 is a schematic architecture diagram of a motherboard in an embodiment of the present application;
FIG. 4 is a table showing the meaning of the first and second identification pin level signals according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing the correct connection of a hard disk backplane to the same CPU on a motherboard;
FIG. 6 is a schematic diagram of an erroneous connection of a hard disk backplane to the same CPU on a motherboard;
FIG. 7 is a schematic diagram showing the correct connection of a hard disk backplane to different CPUs on a motherboard;
FIG. 8 is a schematic diagram of the erroneous connection of the hard disk back plane to different CPUs on the motherboard.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Example 1
The embodiment provides a device for realizing foolproof of a hard disk backboard cable, which comprises:
as shown in fig. 3, the motherboard is provided with at least one group of first CPU and second CPU, the low-order output of the first CPU is connected with the PCIE data pin of the third connector through the PCIE bus of x8, the high-order output of the first CPU is connected with the PCIE data pin of the fourth connector through the PCIE bus of x8, the low-order output of the second CPU is connected with the PCIE data pin of the fifth connector through the PCIE bus of x8, and the high-order output of the second CPU is connected with the PCIE data pin of the sixth connector through the PCIE bus of x 8.
The third connector, the fourth connector, the fifth connector and the sixth connector pin further comprise a first identification pin and a second identification pin respectively; the first identification pin and the second identification pin are used for being connected with an identification signal circuit; the identification signal circuit comprises a low-level circuit and a high-level circuit, wherein the low-level circuit is grounded through a pull-down resistor, and the high-level circuit is grounded through a pull-up resistor and connected with a 3.3V standard power supply;
the first identification pin of the third connector is connected with the low-level circuit, and the second identification pin of the third connector is connected with the low-level circuit.
The first identification pin of the fourth connector is connected with the low-level circuit, and the second identification pin of the fourth connector is connected with the high-level circuit.
The first identification pin of the fifth connector is connected with the high-level circuit, and the second identification pin of the fifth connector is connected with the low-level circuit.
The first identification pin of the sixth connector is connected with the high-level circuit, and the second identification pin of the sixth connector is connected with the high-level circuit.
Referring to fig. 4, in the embodiment of the present application, the low level of the first identification pin is connected to the first CPU, and the high level of the first identification pin is connected to the second CPU. In this embodiment, the low level of the second identification pin is connected to the low level output, and the high level of the second identification pin is connected to the high level output.
Referring to fig. 1, the hard disk back plate is provided with a first connector and a second connector, wherein the first connector is connected with any one of a third connector, a fourth connector, a fifth connector and a sixth connector on the main board, and the second connector is connected with any one of the third connector, the fourth connector, the fifth connector and the sixth connector on the main board. The first connector and the second connector respectively comprise a third identification pin and a fourth identification pin, wherein the third identification pin corresponds to the first identification pin, and the fourth identification pin corresponds to the second identification pin; and PCIE data pins are respectively arranged on the first connector and the second connector.
The third identification pin and the fourth identification pin of the first connector are electrically connected with two input IO ports of the control unit; the third identification pin and the fourth identification pin of the first connector are also electrically connected with the first selection unit; PCIE data pins of the first connector are connected with the first high-speed switching unit through a PCIE bus of x 8.
The third identification pin and the fourth identification pin of the second connector are electrically connected with the other two input IO ports of the control unit; the third identification pin and the fourth identification pin of the second connector are also electrically connected with a second selection unit; and PCIE data pins of the second connector are connected with the second high-speed switching unit through a PCIE bus of x 8.
In the implementation process, the first selection unit and the second selection unit comprise two signal input ports, a signal output port and a control port; the functions of the first selection unit and the second selection unit are: the signal output port is controlled to select the signal output of one of the signal input ports according to the input signal of the control port.
The connection mode of the first selection unit and the second selection unit is as follows:
two signal input ports of the first selection unit are respectively connected with a third identification pin and a fourth identification pin of the first connector; two signal input ends of the second selection unit are respectively connected with a third identification pin and a fourth identification pin of the second connector;
the control port of the first selection unit is connected with one output IO port of the control unit, and the control port of the second selection unit is connected with the other output IO port of the control unit;
the signal output port of the first selection unit is connected with the control signal port of the first high-speed switching unit, and the signal output port of the second selection unit is connected with the control signal port of the second high-speed switching unit.
In the implementation process, the first high-speed switching unit and the second high-speed switching unit each comprise a high-bandwidth input end, four low-bandwidth output ends and a control signal port, wherein the four output ends comprise an output end A1, an output end A2, an output end B1 and an output end B2; the first high-speed switching unit and the second high-speed switching unit function as: and the output end A1 and the output end A2 are controlled to be combined to output an input end signal or the output end B1 and the output end B2 are controlled to be combined to output an input end signal according to the signal of the control signal port. In this embodiment of the present application, the bandwidth of the input end is x8, and the bandwidths of the output end A1, the output end A2, the output end B1 and the output end B2 are all x4.
The specific connection mode of the first high-speed switching unit and the second high-speed switching unit is as follows:
the input end of the first high-speed switching unit is connected with PCIE data pins of the first connector through a PCIE bus of x8, and the input end of the second high-speed switching unit is connected with PCIE data pins of the second connector through a PCIE bus of x 8;
the control signal end of the first high-speed switching unit is connected with the signal output port of the first selecting unit; the control signal end of the second high-speed switching unit is connected with the signal output port of the second selecting unit;
the output end A1 of the first high-speed switching unit and the output end A1 of the second high-speed switching unit are both connected with the first hard disk;
the output end A2 of the first high-speed switching unit and the output end A2 of the second high-speed switching unit are both connected with the second hard disk;
the output end B1 of the first high-speed switching unit and the output end B1 of the second high-speed switching unit are both connected with the third hard disk;
and the output end B2 of the first high-speed switching unit and the output end B2 of the second high-speed switching unit are both connected with the fourth hard disk.
Referring to fig. 4, the first hard disk, the second hard disk, the third hard disk and the fourth hard disk are all provided with two signal sources, and the control unit controls the first high-speed switching unit and the second high-speed switching unit to switch according to the signals of the third identification pin and the fourth identification pin of the first connector and the second connector, so that the disc sequence of the hard disk is ensured to be correct.
In the implementation process, the control unit is electrically connected with four indicator lamps, and the four indicator lamps indicate signals of the third identification pin of the first connector, the fourth identification pin of the first connector, the third identification pin of the second connector and the fourth identification pin of the second connector. And the control unit controls the four indicator lamps to be on or off according to the received identification signals.
Example 2
The embodiment provides a method for realizing foolproof of a hard disk backboard cable.
The method for realizing fool-proof of the hard disk backboard cable comprises the following hard disk sequence setting rules:
when signals at the input ends of the first high-speed switching unit and the second switching unit are sourced from the same CPU, the low-order output of the CPU corresponds to the first hard disk and the second hard disk, and the high-order output of the CPU corresponds to the third hard disk and the fourth hard disk;
when signals at the input ends of the first high-speed switching unit and the second switching unit are respectively sourced from the first CPU and the second CPU, the output of the first CPU corresponds to the first hard disk and the second hard disk, and the output of the second CPU corresponds to the third hard disk and the fourth hard disk.
In this embodiment of the present application, the device for implementing fool-proofing of a hard disk backboard cable is applied, and the method for implementing fool-proofing of a hard disk backboard cable includes:
the control unit detects whether the signal of the third identification pin of the first connector and the signal of the third identification pin of the second connector are identical,
if the first identification pin is the same as the second identification pin, a first signal is sent to a first selection unit and a second selection unit, so that the first selection unit sends a signal of a fourth identification pin of a first connector to the first high-speed switching unit, and the second selection unit sends a signal of a fourth identification pin of a second connector to the second high-speed switching unit;
and if the first identification pin is different from the second identification pin, sending a second signal to the first selection unit and the second selection unit, so that the first selection unit sends the signal of the third identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends the signal of the third identification pin of the second connector to the second high-speed switching unit.
The device and method for realizing foolproof of the hard disk backboard cable provided by the application are as follows:
referring to fig. 5 and 6, in the case where the first connector and the second connector of the hard disk back plate are connected to one CPU, assuming that fig. 5 is a correct connection, fig. 6 is a wrong connection;
the signals from the first connector third identification pin, the first connector fourth identification pin, the second connector third identification pin, the second connector fourth identification pin collected by the control unit in fig. 5 are 0001.
The control unit controls the two output IO ports to output high-level first signals, wherein the signals of the first connector third identification pin (corresponding to the first identification pin) and the second connector third identification pin (corresponding to the first identification pin) are the same; causing the first selection unit to send signal 0 of the fourth identification pin of the first connector to the first high-speed switching unit and causing the second selection unit to send signal 1 of the fourth identification pin of the second connector to the second high-speed switching unit. The control signal end of the first high-speed switching unit is input with 0, the control signal end of the second high-speed switching unit is input with 1, so that the output end A1 and the output end A2 of the first high-speed switching unit output signals, and the output end B1 and the output end B2 of the second high-speed switching unit output signals.
The signals from the first connector third identification pin, the first connector fourth identification pin, the second connector third identification pin, the second connector fourth identification pin collected by the control unit in fig. 6 are 0100.
The control unit controls the two output IO ports to output high-level first signals, wherein the signals of the first connector third identification pin (corresponding to the first identification pin) and the second connector third identification pin (corresponding to the first identification pin) are the same; causing the first selection unit to send a signal 1 of the fourth identification pin of the first connector to the first high-speed switching unit and causing the second selection unit to send a signal 0 of the fourth identification pin of the second connector to the second high-speed switching unit. The control signal end of the first high-speed switching unit is input with 1, the control signal end of the second high-speed switching unit is input with 0, so that the output end B1 and the output end B2 of the first high-speed switching unit output signals, and the output end A1 and the output end A2 of the second high-speed switching unit output signals.
Whether the connection is correct or wrong, the first hard disk and the second hard disk are always connected with the low-order output of the first CPU, and the third hard disk and the fourth hard disk are always connected with the high-order output of the first CPU.
Therefore, in the case that the first connector and the second connector of the hard disk backboard are connected to one CPU, even if the connection is wrong, the hard disk drive sequence can be ensured not to be changed.
Referring to fig. 7 and 8, in the case where the first connector and the second connector of the hard disk back plate are connected to different CPUs, assuming that fig. 7 is a correct connection, fig. 8 is a wrong connection;
the signals from the third identification pin of the first connector, the fourth identification pin of the first connector, the third identification pin of the second connector, and the fourth identification pin of the second connector collected by the control unit in fig. 7 are 0010.
The control unit controls the two output IO ports to output low-level second signals; causing the first selection unit to send a signal 0 of the third identification pin of the first connector to the first high-speed switching unit and causing the second selection unit to send a signal 1 of the third identification pin of the second connector to the second high-speed switching unit. The control signal end of the first high-speed switching unit is input with 0, the control signal end of the second high-speed switching unit is input with 1, so that the output end A1 and the output end A2 of the first high-speed switching unit output signals, and the output end B1 and the output end B2 of the second high-speed switching unit output signals.
The signals from the third identification pin of the first connector, the fourth identification pin of the first connector, the third identification pin of the second connector, and the fourth identification pin of the second connector collected by the control unit in fig. 8 are 1000.
The control unit controls the two output IO ports to output low-level second signals; causing the first selection unit to send a signal 1 of the third identification pin of the first connector to the first high-speed switching unit and causing the second selection unit to send a signal 0 of the third identification pin of the second connector to the second high-speed switching unit. The control signal end of the first high-speed switching unit is input with 1, the control signal end of the second high-speed switching unit is input with 0, so that the output end B1 and the output end B2 of the first high-speed switching unit output signals, and the output end A1 and the output end A2 of the second high-speed switching unit output signals.
Whether the connection is correct or wrong, the first hard disk and the second hard disk are always connected with the first CPU, and the third hard disk and the fourth hard disk are always connected with the second CPU.
Therefore, under the condition that the first connector and the second connector of the hard disk backboard are connected to different CPUs, even if the first connector and the second connector are connected by mistake, the hard disk backboard can ensure that the disk sequence of the hard disk is unchanged.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A device for realizing fool-proof of a hard disk backboard cable, which is characterized by comprising:
the main board is provided with at least one group of first CPU and second CPU, the first CPU is connected with the third connector and the fourth connector, the second CPU is connected with the fifth connector and the sixth connector, and the third connector, the fourth connector, the fifth connector and the sixth connector are connected with the identification signal circuit;
the hard disk backboard is provided with a first connector and a second connector which are connected with the main board, pins of the first connector and the second connector which are connected with the identification signal circuit are connected with the control unit, and the control unit is controlled to be connected with the first selection unit and the second selection unit; the first connector pin connected with the identification signal circuit is connected with the first selection unit, the second connector pin connected with the identification signal circuit is connected with the second selection unit, the first selection unit is controlled to be connected with the first high-speed switching unit, and the second selection unit is controlled to be connected with the second high-speed switching unit;
the first connector is connected with the input end of the first high-speed switching unit, and the second connector is connected with the input end of the second high-speed switching unit; the four output ends of the first high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk.
2. The apparatus for achieving fool-proofing of a hard disk backplane cable according to claim 1, wherein the first connector and the second connector comprise a third identification pin and a fourth identification pin, respectively, the third identification pin and the fourth identification pin being connected to an identification signal circuit.
3. The apparatus for achieving fool-proofing of a hard disk backplane cable according to claim 2, wherein the third connector, the fourth connector, the fifth connector and the sixth connector comprise a first identification pin and a second identification pin, respectively; the first and second identification pins correspond to the third and fourth identification pins, respectively.
4. The apparatus for achieving foolproof of a hard disk back plate cable according to claim 3, wherein the identification signal circuit comprises a low level circuit and a high level circuit;
a first identification pin of the third connector and the fourth connector is connected with a low-level circuit;
a first identification pin of the fifth connector and the sixth connector is connected with a high-level circuit;
a second identification pin of the third connector and the fifth connector is connected with a low-level circuit;
the second identification pins of the fourth connector and the sixth connector are connected with a high-level circuit.
5. The apparatus for achieving hard disk backplane cable fool-proofing of claim 1, wherein said third connector is connected to a low-level output of said first CPU, said fourth connector is connected to a high-level output of said first CPU, said fifth connector is connected to a low-level output of said second CPU, and said sixth connector is connected to a high-level output of said second CPU.
6. The apparatus for realizing fool-proof of a hard disk back plate cable according to claim 2, wherein the first selecting unit and the second selecting unit each comprise two signal input ports, one signal output port and one control port; the signal output of one signal input port is selected by the control signal output port according to the input signal of the control port;
two signal input ports of the first selection unit are respectively connected with a third identification pin and a fourth identification pin of the first connector; two signal input ends of the second selection unit are respectively connected with a third identification pin and a fourth identification pin of the second connector;
the control ports of the first selection unit and the second selection unit are respectively connected with the control unit;
and signal output ports of the first selection unit and the second selection unit are respectively connected with the first high-speed switching unit and the second high-speed switching unit.
7. The apparatus for realizing foolproof of a hard disk backplane cable according to claim 6, wherein the first high-speed switching unit and the second high-speed switching unit each comprise a high-bandwidth input terminal, four low-bandwidth output terminals and a control signal port, wherein the four output terminals comprise an output terminal A1, an output terminal A2, an output terminal B1 and an output terminal B2; the signal control output end A1 and the output end A2 of the control signal port are used for combining and outputting the signal of the input end or the signal control output end B1 and the signal control output end B2 are used for combining and outputting the signal of the input end;
the input end of the first high-speed switching unit is connected with a first connector, and the input end of the second high-speed switching unit is connected with a second connector;
the control signal end of the first high-speed switching unit is connected with the signal output port of the first selecting unit; the control signal end of the second high-speed switching unit is connected with the signal output port of the second selecting unit;
the output ends A1 of the first high-speed switching unit and the second high-speed switching unit are connected with the first hard disk;
the output ends A2 of the first high-speed switching unit and the second high-speed switching unit are connected with the second hard disk;
the output ends B1 of the first high-speed switching unit and the second high-speed switching unit are connected with the third hard disk;
and the output ends B2 of the first high-speed switching unit and the second high-speed switching unit are both connected with the fourth hard disk.
8. The device for realizing foolproof of a hard disk backboard cable according to claim 1, wherein the control unit is electrically connected with a plurality of indicator lamps, and the control unit controls the indicator lamps according to the received identification signals.
9. A method for realizing foolproof of a hard disk backboard cable, which is applied to the device for realizing foolproof of the hard disk backboard cable according to any one of claims 1 to 8, and is characterized in that,
when signals at the input ends of the first high-speed switching unit and the second switching unit are sourced from the same CPU, the low-order output of the CPU corresponds to the first hard disk and the second hard disk, and the high-order output of the CPU corresponds to the third hard disk and the fourth hard disk;
when signals at the input ends of the first high-speed switching unit and the second switching unit are respectively sourced from the first CPU and the second CPU, the output of the first CPU corresponds to the first hard disk and the second hard disk, and the output of the second CPU corresponds to the third hard disk and the fourth hard disk.
10. The method of claim 9, wherein the control unit detects whether the signal of the third identification pin of the first connector and the signal of the third identification pin of the second connector are identical,
if the first identification pin is the same as the second identification pin, a first signal is sent to a first selection unit and a second selection unit, so that the first selection unit sends a signal of a fourth identification pin of a first connector to the first high-speed switching unit, and the second selection unit sends a signal of a fourth identification pin of a second connector to the second high-speed switching unit;
and if the first identification pin is different from the second identification pin, sending a second signal to the first selection unit and the second selection unit, so that the first selection unit sends the signal of the third identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends the signal of the third identification pin of the second connector to the second high-speed switching unit.
CN202110730344.8A 2021-06-29 2021-06-29 Device and method for realizing fool-proof of hard disk backboard cable Active CN113609035B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104077424A (en) * 2014-07-24 2014-10-01 北京京东尚科信息技术有限公司 Method and device for realizing online hot switch of hard disks
CN107943730A (en) * 2017-12-06 2018-04-20 郑州云海信息技术有限公司 A kind of system for supporting NVMe agreement PCIE signals
CN108491039A (en) * 2018-03-21 2018-09-04 英业达科技有限公司 Composite hard disk backboard and server
CN111475385A (en) * 2020-03-08 2020-07-31 苏州浪潮智能科技有限公司 NVME hard disk backboard lighting system and method supporting mixed insertion of cables
CN112463667A (en) * 2020-11-16 2021-03-09 苏州浪潮智能科技有限公司 PCIE card insertion form hard disk expansion device and electronic equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104077424A (en) * 2014-07-24 2014-10-01 北京京东尚科信息技术有限公司 Method and device for realizing online hot switch of hard disks
CN107943730A (en) * 2017-12-06 2018-04-20 郑州云海信息技术有限公司 A kind of system for supporting NVMe agreement PCIE signals
CN108491039A (en) * 2018-03-21 2018-09-04 英业达科技有限公司 Composite hard disk backboard and server
CN111475385A (en) * 2020-03-08 2020-07-31 苏州浪潮智能科技有限公司 NVME hard disk backboard lighting system and method supporting mixed insertion of cables
CN112463667A (en) * 2020-11-16 2021-03-09 苏州浪潮智能科技有限公司 PCIE card insertion form hard disk expansion device and electronic equipment

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