CN113609035A - Device and method for realizing fool-proofing of hard disk backplane cable - Google Patents

Device and method for realizing fool-proofing of hard disk backplane cable Download PDF

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CN113609035A
CN113609035A CN202110730344.8A CN202110730344A CN113609035A CN 113609035 A CN113609035 A CN 113609035A CN 202110730344 A CN202110730344 A CN 202110730344A CN 113609035 A CN113609035 A CN 113609035A
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connector
hard disk
signal
speed switching
switching unit
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CN113609035B (en
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邹志鑫
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/325—Display of status information by lamps or LED's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application relates to a device and a method for realizing fool-proofing of a hard disk backboard cable. Wherein the device includes: the main board is provided with a first CPU connected with the third connector and the fourth connector, a second CPU connected with the fifth connector and the sixth connector, and the third connector, the fourth connector, the fifth connector and the sixth connector are connected with an identification signal circuit; the hard disk backboard is provided with a control unit connected with the first connector and the second connector; a first selecting unit connecting the first connector and the control unit, and a first high-speed switching unit connecting the first connector and the first selecting unit; a second selection unit connecting the second connector and the control unit, and a second high-speed switching unit connecting the second connector and the second selection unit; the output end of the first high-speed switching unit and the corresponding output end of the second high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk. The fool-proof design of connection between the hard disk backboard and the mainboard can be achieved.

Description

Device and method for realizing fool-proofing of hard disk backplane cable
Technical Field
The application relates to the field of hard disk backboard connection design, in particular to a device and a method for realizing fool-proofing of a hard disk backboard cable.
Background
In the server, one server CPU can mount a plurality of hard disks. The server is often designed to mount a plurality of hard disks in order to guarantee storage capacity, and in order to maintain and manage the hard disks in the server, a plurality of hard disks are often concentrated on the hard disk back plate, and then the hard disk back plate is connected with the server mainboard.
Hard disk backplate and server mainboard adopt interconnection interface own symmetry in the design, produce the problem of connection error easily when being connected to the server mainboard with the hard disk backplate, in case the interface connects the mistake between hard disk backplate and the mainboard, can arouse hard disk preface confusion, all can cause adverse effect to server operation and later stage hard disk maintenance and management. In the prior art, the label indicates that the hard disk interface and the mainboard interface cannot completely solve the problem of wrong interface connection through the mode of indicating the connection error by the indicator lamp, and the hard disk sequence confusion can still be caused once the interface is connected in a wrong way.
Disclosure of Invention
In order to solve the technical problem or at least partially solve the technical problem, the device and the method for realizing fool-proofing of the hard disk backplane cable are provided.
The application of the first aspect provides a device for realizing fool-proofing of a hard disk backboard cable, which comprises:
the main board is provided with at least one group of first CPU and second CPU, the first CPU is connected with a third connector and a fourth connector, the second CPU is connected with a fifth connector and a sixth connector, and the third connector, the fourth connector, the fifth connector and the sixth connector are connected with an identification signal circuit;
the hard disk backboard is provided with a first connector and a second connector which are connected with the mainboard, the first connector and the second connector which are connected with the identification signal circuit are connected with the control unit through pins, and the control unit is connected with the first selection unit and the second selection unit in a control mode; the first connector pin connected with the identification signal circuit is connected with the first selection unit, the second connector pin connected with the identification signal circuit is connected with the second selection unit, the first selection unit is connected with the first high-speed switching unit in a control mode, and the second selection unit is connected with the second high-speed switching unit in a control mode;
the first connector is connected with the input end of the first high-speed switching unit, and the second connector is connected with the input end of the second high-speed switching unit; the four output ends of the first high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk, and the four output ends of the second high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk.
Further, the first connector and the second connector respectively comprise a third identification pin and a fourth identification pin, and the third identification pin and the fourth identification pin are connected with an identification signal circuit.
Furthermore, the third connector, the fourth connector, the fifth connector and the sixth connector respectively comprise a first identification pin and a second identification pin; the first identification stitch and the second identification stitch correspond to the third identification stitch and the fourth identification stitch respectively.
Further, the identification signal circuit includes a low level circuit and a high level circuit;
first identification pins of the third connector and the fourth connector are connected with a low-level circuit;
first identification pins of the fifth connector and the sixth connector are connected with a high-level circuit;
second identification pins of the third connector and the fifth connector are connected with a low-level circuit;
and second identification pins of the fourth connector and the sixth connector are connected with a high-level circuit.
Furthermore, the third connector is connected to the low-order output of the first CPU, the fourth connector is connected to the high-order output of the first CPU, the fifth connector is connected to the low-order output of the second CPU, and the sixth connector is connected to the high-order output of the second CPU.
Furthermore, the first selection unit and the second selection unit each include two signal input ports, one signal output port and one control port; controlling the signal output port to select the signal output of one signal input port according to the input signal of the control port;
two signal input ports of the first selection unit are respectively connected with a third identification pin and a fourth identification pin of the first connector; two signal input ends of the second selection unit are respectively connected with a third identification pin and a fourth identification pin of the second connector;
the control ports of the first selection unit and the second selection unit are respectively connected with the control unit;
and the signal output ports of the first selection unit and the second selection unit are respectively connected with the first high-speed switching unit and the second high-speed switching unit.
Further, the first high-speed switching unit and the second high-speed switching unit each include one high-bandwidth input terminal, four low-bandwidth output terminals, and one control signal port, wherein the four output terminals include an output terminal a1, an output terminal a2, an output terminal B1, and an output terminal B2; controlling the output end A1 and the output end A2 to output an input end signal in a combined mode or controlling the output end B1 and the output end B2 to output an input end signal in a combined mode according to signals of the control signal port;
the input end of the first high-speed switching unit is connected with a first connector, and the input end of the second high-speed switching unit is connected with a second connector;
the control signal end of the first high-speed switching unit is connected with the signal output port of the first selection unit; the control signal end of the second high-speed switching unit is connected with the signal output port of the second selection unit;
the output ends A1 of the first high-speed switching unit and the second high-speed switching unit are both connected with the first hard disk;
the output ends A2 of the first high-speed switching unit and the second high-speed switching unit are both connected with the second hard disk;
the output ends B1 of the first high-speed switching unit and the second high-speed switching unit are both connected with the third hard disk;
the output ends B2 of the first high-speed switching unit and the second high-speed switching unit are both connected with the fourth hard disk.
Furthermore, the control unit is electrically connected with the plurality of indicator lights and controls the indicator lights according to the received identification signals.
In a second aspect, the present application provides a method for implementing fool-proofing of a hard disk backplane cable, which is applied to the apparatus for implementing fool-proofing of a hard disk backplane cable, and includes:
when the signals of the input ends of the first high-speed switching unit and the second switching unit are from the same CPU, the low-order output of the CPU corresponds to the first hard disk and the second hard disk, and the high-order output of the CPU corresponds to the third hard disk and the fourth hard disk;
when the signal sources of the input ends of the first high-speed switching unit and the second switching unit are from the first CPU and the second CPU, the output of the first CPU corresponds to the first hard disk and the second hard disk, and the output of the second CPU corresponds to the third hard disk and the fourth hard disk.
Furthermore, the control unit detects whether the signal of the third identification pin of the first connector and the signal of the third identification pin of the second connector are the same,
if the first signal is the same as the second signal, sending a first signal to a first selection unit and a second selection unit, so that the first selection unit sends a signal of a fourth identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends a signal of a fourth identification pin of the second connector to the second high-speed switching unit;
and if the first selection unit and the second selection unit are different, sending a second signal to the first selection unit and the second selection unit, so that the first selection unit sends a signal of a third identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends a signal of a third identification pin of the second connector to the second high-speed switching unit.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the method includes the steps that a third connector, a fourth connector, a fifth connector and a sixth connector which are connected with a first CPU and a second CPU on a mainboard are marked through a recognition signal circuit; the identification signal circuit transmits four different identification signals to the control unit on the hard disk backboard through the third connector, the fourth connector, the fifth connector and the sixth connector respectively.
When the first connector and the second connector on the hard disk backboard are connected to the mainboard, the control unit receives two of the four identification signals, the control unit controls the first selection unit and the second selection unit according to the identification signals, and then the first selection unit and the second selection unit respectively control the first high-speed switching unit and the second high-speed switching unit to achieve the foolproof design of connection between the hard disk backboard and the mainboard, so that the hard disk of the backboard can still ensure that the disk sequence of the hard disk is unchanged under the condition that the hard disk of the backboard is reversely connected.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic diagram illustrating a hard disk backplane according to an embodiment of the present application;
fig. 2 is a signal source table of a first hard disk, a second hard disk, a third hard disk and a fourth hard disk in the embodiment of the present application;
FIG. 3 is a schematic diagram of a motherboard according to an embodiment of the present application;
FIG. 4 is a table showing the meaning of the level signals of the first identification pin and the second identification pin in the embodiment of the present application;
FIG. 5 is a schematic diagram of a correct connection of a hard disk backplane to the same CPU on a motherboard;
FIG. 6 is a schematic diagram of an erroneous connection of a hard disk backplane to the same CPU on a motherboard;
FIG. 7 is a schematic diagram of the correct connection of the hard disk backplane to different CPUs on the motherboard;
FIG. 8 is a schematic diagram of an erroneous connection of a hard disk backplane to different CPUs on a motherboard.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Example 1
This embodiment provides a device that hard disk backplate cable was prevented slow-witted is realized, includes:
referring to fig. 3, the motherboard is provided with at least one set of a first CPU and a second CPU, where a low-level output of the first CPU is connected to a PCIE data pin of the third connector through a PCIE bus of x8, a high-level output of the first CPU is connected to a PCIE data pin of the fourth connector through a PCIE bus of x8, a low-level output of the second CPU is connected to a PCIE data pin of the fifth connector through a PCIE bus of x8, and a high-level output of the second CPU is connected to a PCIE data pin of the sixth connector through a PCIE bus of x 8.
The third connector pin, the fourth connector pin, the fifth connector pin and the sixth connector pin respectively comprise a first identification pin and a second identification pin; the first identification pin and the second identification pin are used for connecting an identification signal circuit; the identification signal circuit comprises a low-level circuit and a high-level circuit, specifically, the low-level circuit is realized by grounding a pull-down resistor, and the high-level circuit is realized by connecting a 3.3V standard power supply through a pull-up resistor;
the first identification pin of the third connector is connected with a low-level circuit, and the second identification pin of the third connector is connected with the low-level circuit.
The first identification pin of the fourth connector is connected with a low-level circuit, and the second identification pin of the fourth connector is connected with a high-level circuit.
And a first identification pin of the fifth connector is connected with a high-level circuit, and a second identification pin of the fifth connector is connected with a low-level circuit.
And a first identification pin of the sixth connector is connected with a high-level evaluation circuit, and a second identification pin of the sixth connector is connected with a high-level circuit.
Referring to fig. 4, in the embodiment of the present application, a low level of the first identification pin indicates that the first CPU is connected, and a high level of the first identification pin indicates that the second CPU is connected. In the embodiment of the application, the low level of the second identification pin indicates that the connection is at the low output, and the high level of the second identification pin indicates that the connection is at the high output.
Referring to fig. 1, the hard disk backplane is connected to a first connector and a second connector of the motherboard, specifically, the first connector is connected to any one of a third connector, a fourth connector, a fifth connector and a sixth connector on the motherboard, and the second connector is connected to any one of the third connector, the fourth connector, the fifth connector and the sixth connector on the motherboard. The first connector and the second connector respectively comprise a third identification pin and a fourth identification pin, the third identification pin corresponds to the first identification pin, and the fourth identification pin corresponds to the second identification pin; the first connector and the second connector are respectively provided with PCIE data pins.
The third identification pin and the fourth identification pin of the first connector are electrically connected with two input/output (IO) ports of the control unit; the third identification pin and the fourth identification pin of the first connector are also electrically connected with the first selection unit; the PCIE data pin of the first connector is connected to the first high-speed switching unit through the PCIE bus of x 8.
The third identification pin and the fourth identification pin of the second connector are electrically connected with the other two input IO ports of the control unit; the third identification pin and the fourth identification pin of the second connector are also electrically connected with the second selection unit; and the PCIE data pins of the second connector are connected with the second high-speed switching unit through a PCIE bus of x 8.
In a specific implementation process, the first selection unit and the second selection unit respectively comprise two signal input ports, a signal output port and a control port; the first selection unit and the second selection unit function to: and controlling the signal output port to select the signal output of one signal input port according to the input signal of the control port.
The first selection unit and the second selection unit are connected in the following way:
two signal input ports of the first selection unit are respectively connected with a third identification pin and a fourth identification pin of the first connector; two signal input ends of the second selection unit are respectively connected with a third identification pin and a fourth identification pin of the second connector;
the control port of the first selection unit is connected with one output IO port of the control unit, and the control port of the second selection unit is connected with the other output IO port of the control unit;
the signal output port of the first selection unit is connected with the control signal port of the first high-speed switching unit, and the signal output port of the second selection unit is connected with the control signal port of the second high-speed switching unit.
In a specific implementation process, the first high-speed switching unit and the second high-speed switching unit each include a high-bandwidth input terminal, four low-bandwidth output terminals, and a control signal port, where the four output terminals include an output terminal a1, an output terminal a2, an output terminal B1, and an output terminal B2; the first high-speed switching unit and the second high-speed switching unit function as: the output terminal A1 and the output terminal A2 are controlled to combine the output-input-terminal signal or the output terminal B1 and the output terminal B2 are controlled to combine the output-input-terminal signal according to the signal of the control signal port. In the embodiment of the present application, the bandwidth of the input terminal is x8, and the bandwidths of the output terminal a1, the output terminal a2, the output terminal B1 and the output terminal B2 are all x 4.
The first high-speed switching unit and the second high-speed switching unit are connected in a specific manner as follows:
the input end of the first high-speed switching unit is connected with a PCIE data pin of the first connector through a PCIE bus of x8, and the input end of the second high-speed switching unit is connected with a PCIE data pin of the second connector through a PCIE bus of x 8;
the control signal end of the first high-speed switching unit is connected with the signal output port of the first selection unit; the control signal end of the second high-speed switching unit is connected with the signal output port of the second selection unit;
the output end A1 of the first high-speed switching unit and the output end A1 of the second high-speed switching unit are both connected with the first hard disk;
the output end A2 of the first high-speed switching unit and the output end A2 of the second high-speed switching unit are both connected with the second hard disk;
the output end B1 of the first high-speed switching unit and the output end B1 of the second high-speed switching unit are both connected with the third hard disk;
the output end B2 of the first high-speed switching unit and the output end B2 of the second high-speed switching unit are both connected with the fourth hard disk.
Referring to fig. 4, the first hard disk, the second hard disk, the third hard disk and the fourth hard disk are all provided with two signal sources, and the control unit controls the first high-speed switching unit and the second high-speed switching unit to switch according to signals of a third identification pin and a fourth identification pin of the first connector and the second connector, so as to ensure that the disk sequence of the hard disks is correct.
In the specific implementation process, the control unit is electrically connected with the four indicator lamps, and the four indicator lamps indicate signals of the third identification pin of the first connector, the fourth identification pin of the first connector, the third identification pin of the second connector and the fourth identification pin of the second connector. And the control unit controls the four indicator lamps to be turned on or off according to the received identification signals.
Example 2
The embodiment provides a method for realizing fool-proofing of a hard disk backboard cable.
The method for realizing the fool-proof of the hard disk backboard cable comprises the following hard disk sequence setting rules:
when the signals of the input ends of the first high-speed switching unit and the second switching unit are from the same CPU, the low-order output of the CPU corresponds to the first hard disk and the second hard disk, and the high-order output of the CPU corresponds to the third hard disk and the fourth hard disk;
when the signals of the input ends of the first high-speed switching unit and the second switching unit are respectively sourced from the first CPU and the second CPU, the output of the first CPU corresponds to the first hard disk and the second hard disk, and the output of the second CPU corresponds to the third hard disk and the fourth hard disk.
In the embodiment of the application, the method for realizing the fool-proof of the hard disk backboard cable comprises the following steps:
the control unit detects whether the signal of the third identification pin of the first connector and the signal of the third identification pin of the second connector are the same,
if the first signal is the same as the second signal, sending a first signal to a first selection unit and a second selection unit, so that the first selection unit sends a signal of a fourth identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends a signal of a fourth identification pin of the second connector to the second high-speed switching unit;
and if the first selection unit and the second selection unit are different, sending a second signal to the first selection unit and the second selection unit, so that the first selection unit sends a signal of a third identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends a signal of a third identification pin of the second connector to the second high-speed switching unit.
The principle of the device and the method for realizing the fool-proofing of the hard disk backboard cable provided by the application is as follows:
referring to fig. 5 and 6, in the case where the first connector and the second connector of the hard disk backplane are connected to one CPU, it is assumed that fig. 5 is a correct connection and fig. 6 is an incorrect connection;
the signals collected by the control unit in fig. 5 from the first connector third identification pin, the first connector fourth identification pin, the second connector third identification pin and the second connector fourth identification pin are 0001.
The control unit controls the two output IO ports to output a first signal with high level, wherein the signals of a third identification pin (corresponding to the first identification pin) of the first connector and a third identification pin (corresponding to the first identification pin) of the second connector are the same; the first selection unit is enabled to send a signal 0 of a fourth identification pin of the first connector to the first high-speed switching unit, and the second selection unit is enabled to send a signal 1 of a fourth identification pin of the second connector to the second high-speed switching unit. The control signal terminal of the first high speed switching unit is inputted with 0, the control signal terminal of the second high speed switching unit is inputted with 1, so that the output terminal a1 and the output terminal a2 of the first high speed switching unit output signals, and the output terminal B1 and the output terminal B2 of the second high speed switching unit output signals.
The signals from the first connector third identification pin, the first connector fourth identification pin, the second connector third identification pin and the second connector fourth identification pin collected by the control unit in fig. 6 are 0100.
The control unit controls the two output IO ports to output a first signal with high level, wherein the signals of a third identification pin (corresponding to the first identification pin) of the first connector and a third identification pin (corresponding to the first identification pin) of the second connector are the same; the first selection unit is enabled to send a signal 1 of a fourth identification pin of the first connector to the first high-speed switching unit, and the second selection unit is enabled to send a signal 0 of a fourth identification pin of the second connector to the second high-speed switching unit. The control signal terminal of the first high speed switching unit is input with 1, the control signal terminal of the second high speed switching unit is input with 0, so that the output terminal B1 and the output terminal B2 of the first high speed switching unit output signals, and the output terminal a1 and the output terminal a2 of the second high speed switching unit output signals.
Whether the connection is correct or wrong, the first hard disk and the second hard disk start to terminate the low-order output of the first CPU, and the third hard disk and the fourth hard disk start to terminate the high-order output of the first CPU.
Therefore, under the condition that the first connector and the second connector of the hard disk backboard are connected to one CPU, even if the connection is wrong, the hard disk order can be ensured to be unchanged.
Referring to fig. 7 and 8, in the case where the first connector and the second connector of the hard disk backplane are connected to different CPUs, it is assumed that fig. 7 is a correct connection and fig. 8 is an incorrect connection;
the signals collected by the control unit in fig. 7 from the first connector third identification pin, the first connector fourth identification pin, the second connector third identification pin and the second connector fourth identification pin are 0010.
The control unit controls the two output IO ports to output a second signal with a low level, wherein the signals of a third identification pin (corresponding to the first identification pin) of the first connector and a third identification pin (corresponding to the first identification pin) of the second connector of the control unit are different; the first selection unit is enabled to send a signal 0 of a third identification pin of the first connector to the first high-speed switching unit, and the second selection unit is enabled to send a signal 1 of a third identification pin of the second connector to the second high-speed switching unit. The control signal terminal of the first high speed switching unit is inputted with 0, the control signal terminal of the second high speed switching unit is inputted with 1, so that the output terminal a1 and the output terminal a2 of the first high speed switching unit output signals, and the output terminal B1 and the output terminal B2 of the second high speed switching unit output signals.
The signals collected by the control unit in fig. 8 from the first connector third identification pin, the first connector fourth identification pin, the second connector third identification pin, and the second connector fourth identification pin are 1000.
The control unit controls the two output IO ports to output a second signal with a low level, wherein the signals of a third identification pin (corresponding to the first identification pin) of the first connector and a third identification pin (corresponding to the first identification pin) of the second connector of the control unit are different; the first selection unit is enabled to send a signal 1 of a third identification pin of the first connector to the first high-speed switching unit, and the second selection unit is enabled to send a signal 0 of a third identification pin of the second connector to the second high-speed switching unit. The control signal terminal of the first high speed switching unit is input with 1, the control signal terminal of the second high speed switching unit is input with 0, so that the output terminal B1 and the output terminal B2 of the first high speed switching unit output signals, and the output terminal a1 and the output terminal a2 of the second high speed switching unit output signals.
Whether the connection is correct or wrong, the first hard disk and the second hard disk are terminated to the first CPU, and the third hard disk and the fourth hard disk are terminated to the second CPU.
Therefore, under the condition that the first connector and the second connector of the hard disk backboard are connected to different CPUs, even if the connection is wrong, the hard disk order can be guaranteed to be unchanged.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The utility model provides a realize hard disk backplate cable and prevent slow-witted device which characterized in that includes:
the main board is provided with at least one group of first CPU and second CPU, the first CPU is connected with a third connector and a fourth connector, the second CPU is connected with a fifth connector and a sixth connector, and the third connector, the fourth connector, the fifth connector and the sixth connector are connected with an identification signal circuit;
the hard disk backboard is provided with a first connector and a second connector which are connected with the mainboard, the first connector and the second connector which are connected with the identification signal circuit are connected with the control unit through pins, and the control unit is connected with the first selection unit and the second selection unit in a control mode; the first connector pin connected with the identification signal circuit is connected with the first selection unit, the second connector pin connected with the identification signal circuit is connected with the second selection unit, the first selection unit is connected with the first high-speed switching unit in a control mode, and the second selection unit is connected with the second high-speed switching unit in a control mode;
the first connector is connected with the input end of the first high-speed switching unit, and the second connector is connected with the input end of the second high-speed switching unit; the four output ends of the first high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk, and the four output ends of the second high-speed switching unit are respectively connected with the first hard disk, the second hard disk, the third hard disk and the fourth hard disk.
2. The device for realizing the fool-proofing of the hard disk backplane cable according to claim 1, wherein the first connector and the second connector respectively comprise a third identification pin and a fourth identification pin, and the third identification pin and the fourth identification pin are connected with an identification signal circuit.
3. The device for realizing the fool-proofing of the hard disk backplane cable according to claim 2, wherein the third connector, the fourth connector, the fifth connector and the sixth connector respectively comprise a first identification pin and a second identification pin; the first identification stitch and the second identification stitch correspond to the third identification stitch and the fourth identification stitch respectively.
4. The device for realizing the fool-proofing of the hard disk backplane cable according to claim 3, wherein the identification signal circuit comprises a low level circuit and a high level circuit;
first identification pins of the third connector and the fourth connector are connected with a low-level circuit;
first identification pins of the fifth connector and the sixth connector are connected with a high-level circuit;
second identification pins of the third connector and the fifth connector are connected with a low-level circuit;
and second identification pins of the fourth connector and the sixth connector are connected with a high-level circuit.
5. The device of claim 1, wherein the third connector is connected to the low-level output of the first CPU, the fourth connector is connected to the high-level output of the first CPU, the fifth connector is connected to the low-level output of the second CPU, and the sixth connector is connected to the high-level output of the second CPU.
6. The device for realizing the fool-proofing of the hard disk backplane cable according to claim 2, wherein the first selection unit and the second selection unit each comprise two signal input ports, one signal output port and one control port; controlling the signal output port to select the signal output of one signal input port according to the input signal of the control port;
two signal input ports of the first selection unit are respectively connected with a third identification pin and a fourth identification pin of the first connector; two signal input ends of the second selection unit are respectively connected with a third identification pin and a fourth identification pin of the second connector;
the control ports of the first selection unit and the second selection unit are respectively connected with the control unit;
and the signal output ports of the first selection unit and the second selection unit are respectively connected with the first high-speed switching unit and the second high-speed switching unit.
7. The apparatus of claim 6, wherein the first high-speed switch unit and the second high-speed switch unit each comprise a high-bandwidth input terminal, four low-bandwidth output terminals, and a control signal port, wherein the four output terminals comprise an output terminal A1, an output terminal A2, an output terminal B1, and an output terminal B2; controlling the output end A1 and the output end A2 to output an input end signal in a combined mode or controlling the output end B1 and the output end B2 to output an input end signal in a combined mode according to signals of the control signal port;
the input end of the first high-speed switching unit is connected with a first connector, and the input end of the second high-speed switching unit is connected with a second connector;
the control signal end of the first high-speed switching unit is connected with the signal output port of the first selection unit; the control signal end of the second high-speed switching unit is connected with the signal output port of the second selection unit;
the output ends A1 of the first high-speed switching unit and the second high-speed switching unit are both connected with the first hard disk;
the output ends A2 of the first high-speed switching unit and the second high-speed switching unit are both connected with the second hard disk;
the output ends B1 of the first high-speed switching unit and the second high-speed switching unit are both connected with the third hard disk;
the output ends B2 of the first high-speed switching unit and the second high-speed switching unit are both connected with the fourth hard disk.
8. The device for realizing the fool-proofing of the hard disk backboard cable according to claim 1, wherein the control unit is electrically connected with a plurality of indicator lamps, and the control unit controls the indicator lamps according to the received identification signal.
9. A method for realizing the fool-proof of hard disk backboard cable is applied to the device for realizing the fool-proof of hard disk backboard cable in any claim 1-8,
when the signals of the input ends of the first high-speed switching unit and the second switching unit are from the same CPU, the low-order output of the CPU corresponds to the first hard disk and the second hard disk, and the high-order output of the CPU corresponds to the third hard disk and the fourth hard disk;
when the signals of the input ends of the first high-speed switching unit and the second switching unit are respectively sourced from the first CPU and the second CPU, the output of the first CPU corresponds to the first hard disk and the second hard disk, and the output of the second CPU corresponds to the third hard disk and the fourth hard disk.
10. The method of claim 9, wherein the control unit detects whether the signal of the third identification pin of the first connector and the signal of the third identification pin of the second connector are the same,
if the first signal is the same as the second signal, sending a first signal to a first selection unit and a second selection unit, so that the first selection unit sends a signal of a fourth identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends a signal of a fourth identification pin of the second connector to the second high-speed switching unit;
and if the first selection unit and the second selection unit are different, sending a second signal to the first selection unit and the second selection unit, so that the first selection unit sends a signal of a third identification pin of the first connector to the first high-speed switching unit, and the second selection unit sends a signal of a third identification pin of the second connector to the second high-speed switching unit.
CN202110730344.8A 2021-06-29 2021-06-29 Device and method for realizing fool-proof of hard disk backboard cable Active CN113609035B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104077424A (en) * 2014-07-24 2014-10-01 北京京东尚科信息技术有限公司 Method and device for realizing online hot switch of hard disks
CN107943730A (en) * 2017-12-06 2018-04-20 郑州云海信息技术有限公司 A kind of system for supporting NVMe agreement PCIE signals
CN108491039A (en) * 2018-03-21 2018-09-04 英业达科技有限公司 Composite hard disk backboard and server
CN111475385A (en) * 2020-03-08 2020-07-31 苏州浪潮智能科技有限公司 NVME hard disk backboard lighting system and method supporting mixed insertion of cables
CN112463667A (en) * 2020-11-16 2021-03-09 苏州浪潮智能科技有限公司 PCIE card insertion form hard disk expansion device and electronic equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104077424A (en) * 2014-07-24 2014-10-01 北京京东尚科信息技术有限公司 Method and device for realizing online hot switch of hard disks
CN107943730A (en) * 2017-12-06 2018-04-20 郑州云海信息技术有限公司 A kind of system for supporting NVMe agreement PCIE signals
CN108491039A (en) * 2018-03-21 2018-09-04 英业达科技有限公司 Composite hard disk backboard and server
CN111475385A (en) * 2020-03-08 2020-07-31 苏州浪潮智能科技有限公司 NVME hard disk backboard lighting system and method supporting mixed insertion of cables
CN112463667A (en) * 2020-11-16 2021-03-09 苏州浪潮智能科技有限公司 PCIE card insertion form hard disk expansion device and electronic equipment

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