CN117606522A - Five-channel absolute type angle encoder analysis device - Google Patents
Five-channel absolute type angle encoder analysis device Download PDFInfo
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- CN117606522A CN117606522A CN202311462489.XA CN202311462489A CN117606522A CN 117606522 A CN117606522 A CN 117606522A CN 202311462489 A CN202311462489 A CN 202311462489A CN 117606522 A CN117606522 A CN 117606522A
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- absolute angle
- clock
- data
- angle encoder
- programmable logic
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- 238000005070 sampling Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
- G01D5/249—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains using pulse code
- G01D5/2497—Absolute encoders
Abstract
The invention discloses a five-channel absolute type angle encoder analysis device, which comprises an operation processing module, a clock signal module, a data signal module, an ISA communication interface and an absolute type angle encoder interface; the operation processing module sends unified clock signals and position information acquisition instructions to the five absolute angle encoders through the absolute angle encoder interface after passing through the clock signal module and the data signal module respectively; the signal sent to the data signal module by the operation processing module controls the original position information of the five absolute angle encoders, the original position information is sequentially received by the operation processing module through one path of port, and the operation processing module analyzes the position information and then transmits the position information to the industrial personal computer through the ISA communication interface for use. The invention optimizes the use of the ports of the operation processing module and realizes the position analysis of the absolute angle encoder of five channels.
Description
Technical Field
The invention relates to a five-channel absolute type angle encoder analyzing device.
Background
Currently, angle encoders are widely used in the field of industrial control. The absolute angle encoder angular position information can be analyzed by a plurality of channels from a single channel to a three channel, each channel needs to occupy port resources independently, more hardware is needed for the port resources to be analyzed for five channels, and the hardware cost is increased.
Disclosure of Invention
The present invention is directed to a five-channel absolute angle encoder parsing apparatus, which solves the above-mentioned problems in the prior art.
The technical scheme adopted for realizing the aim is that the five-channel absolute type angle encoder analysis device comprises an operation processing module, a clock signal module, a data signal module, an ISA communication interface and an absolute type angle encoder interface; the operation processing module comprises an FPGA programmable logic chip; one port of the FPGA programmable logic chip is respectively connected with the input ends of the five paths of clock data transceiver chips of the clock signal module, the output ends of the clock data transceiver chips are connected with the clock RC filter circuit, and clock signals generated by the FPGA programmable logic chip are respectively sent to the five absolute angle encoders through the absolute angle encoder interfaces; five ports of the FPGA programmable logic chip are connected with control ports of five paths of data transceiver chips corresponding to the data signal modules, and control data acquisition instructions and data input and output; one port of the FPGA programmable logic chip is respectively connected with the input ends of five paths of data transceiver chips of the data signal module, the output ends of the data transceiver chips are connected with a data RC filter circuit, and sampling position instructions generated by the FPGA programmable logic chip are respectively sent to five absolute angle encoders through an absolute angle encoder interface in a carrier wave mode; one port of the FPGA programmable logic chip is respectively connected with the output ends of the five paths of data transceiver chips of the data signal module, and the FPGA programmable logic chip sends control signals to the data transceiver chips in a time period of 5 k: in the first period, the output of the first path of data transceiver is valid, and the other four paths of output are invalid; the second period, the second transceiver output is valid, and the other four outputs are invalid; the third period, the output of the third transceiver is valid, and the other four outputs are invalid; the fourth period, the fourth transceiver output is valid, and the other four outputs are invalid; in the fifth period, the output of the fifth transceiver is valid, and the other four outputs are invalid; and after the data transceiver chip receives the angular position original information, the angular position is analyzed and then is transmitted to the industrial personal computer for use through the ISA communication interface.
Further, the model of the FPGA programmable logic chip is EP2C8_144.
Further, the operation processing module further comprises a serial configuration chip, a clock circuit and a power circuit; the serial configuration chip is EPCS16 and is used for storing a software program for the FPGA programmable logic chip; the clock circuit is used for providing clock signals for the FPGA programmable logic chip.
Further, the clock signal module comprises a five-way clock data transceiver chip and a five-way clock filter circuit, and is used for converting the single-ended clock signal sent by the operation processing module into a differential clock signal and transmitting the differential clock signal to the absolute angle encoder interface.
Further, the data signal module comprises five paths of data transceiver chips and five paths of filter circuits, and is used for converting the single-ended angular position acquisition instruction signals into differential angular position acquisition instruction signals, controlling the original position information of the five absolute angle encoders according to signals output by the operation processing module, and sequentially receiving the information by the operation processing module through one path of ports.
Further, the clock data transceiver chip and the data transceiver chip are each MAX3485 in model number.
Advantageous effects
Compared with the prior art, the invention has the following advantages.
The invention optimizes the use of port resources based on the existing hardware, and can realize the analysis of the angular position information of the five-way absolute angle encoder; and reallocating port resources, the optimized port resources may provide for other signal usage.
Drawings
The present invention is described in further detail below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the overall structure of the present invention;
FIG. 2 is a schematic diagram of an arithmetic processing module according to the present invention;
FIG. 3 is a schematic diagram of a clock signal module according to the present invention;
fig. 4 is a schematic diagram of a data signal module according to the present invention.
Detailed Description
The invention is further described below with reference to examples and figures.
As shown in fig. 1-4, a five-channel absolute angle encoder parsing device includes an operation processing module 1, a clock signal module 2, a data signal module 3, an ISA communication interface 4 and an absolute angle encoder interface 5; the operation processing module 1 comprises an FPGA programmable logic chip 8; one port of the FPGA programmable logic chip 8 is respectively connected with the input ends of the five paths of clock data transceiver chips 13 of the clock signal module 2, the output ends of the clock data transceiver chips 13 are connected with the clock RC filter circuit 12, and clock signals generated by the FPGA programmable logic chip 8 are respectively sent to the five absolute angle encoders 6 through the absolute angle encoder interface 5; five ports of the FPGA programmable logic chip 8 are connected with control ports of five paths of data transceiver chips 14 corresponding to the data signal module 3, and control data acquisition instructions and data input and output; one port of the FPGA programmable logic chip 8 is respectively connected with the input ends of five paths of data transceiver chips 14 of the data signal module 3, the output ends of the data transceiver chips 14 are connected with a data RC filter circuit 15, and sampling position instructions generated by the FPGA programmable logic chip 8 are respectively sent to five absolute angle encoders 6 through an absolute angle encoder interface 5 in a carrier wave mode; one port of the FPGA programmable logic chip 8 is respectively connected to the output terminals of the five paths of data transceiver chips 14 of the data signal module 3, and the FPGA programmable logic chip 8 sends control signals to the data transceiver chips 14 in a time period of 5 k: in the first period, the output of the first path of data transceiver is valid, and the other four paths of output are invalid; the second period, the second transceiver output is valid, and the other four outputs are invalid; the third period, the output of the third transceiver is valid, and the other four outputs are invalid; the fourth period, the fourth transceiver output is valid, and the other four outputs are invalid; in the fifth period, the output of the fifth transceiver is valid, and the other four outputs are invalid; after receiving the original information of the angular position, the data transceiver chip 14 completes the analysis of the angular position and transmits the information to the industrial personal computer through the ISA communication interface 4 for use.
The model of the FPGA programmable logic chip 8 is EP2C8_144.
The operation processing module 1 further comprises a serial configuration chip 7, a clock circuit 11 and a power circuit 10; the serial configuration chip 7 is of the type EPCS16 and is used for storing software programs for the FPGA programmable logic chip 8; the clock circuit 11 is used for providing clock signals for the FPGA programmable logic chip 8.
The clock signal module 2 includes a five-way clock data transceiver chip 13 and a five-way clock filter circuit 12, and is configured to convert a single-ended clock signal sent by the operation processing module 1 into a differential clock signal and send the differential clock signal to the absolute angle encoder interface 5.
The data signal module 3 includes five paths of data transceiver chips 14 and five paths of filter circuits 15, and is configured to convert a single-ended angular position acquisition command signal into a differential angular position acquisition command signal, and control the original position information of the five absolute angle encoders 6 according to the signal output by the operation processing module 1, and sequentially receive the information through one path of ports by the operation processing module 1.
The model numbers of the clock data transceiver chip 13 and the data transceiver chip 14 are MAX3485.
In the invention, the operation processing module 1 comprises an FPGA programmable logic chip 8, a serial configuration chip 7, a clock circuit 11 and a power circuit 10; the clock signal module 2 comprises a clock data transceiver chip 13 with the model number of MAX3485 and a clock RC filter circuit 12, and is used for converting a single-ended clock signal into a differential clock signal; the data signal module 3 comprises a data transceiver chip 14 with the model number of MAX3485 and a data RC filter circuit 15, and is used for converting a single-ended angular position acquisition command signal into a differential angular position acquisition command signal; and the original position information of the five-channel absolute angle encoder is controlled according to the signal output by the operation processing module 1, and is sequentially received by the operation processing module 1 through one channel port.
The working principle of the invention is that the operation processing module 1 sends a clock signal through one port and a position acquisition instruction through one port, and the position acquisition instruction is respectively transmitted to five absolute angle encoders 6 through the clock signal module 2 and the data signal module 3 and the absolute angle encoder interface 5; on the other hand, the operation processing module 1 sends control signals to the data signal module 3 through five paths of ports, the output of a control position acquisition instruction and the input of angle position original data are controlled, and when the respective control signals of the five paths of angle position original signals are valid, the five paths of angle position original signals are transmitted to the operation processing module 1 through one path of ports after being converted from differential to single ended; after the angular position information is analyzed, the angular position information is transmitted to the industrial personal computer through the ISA communication interface 4 in a period of 1 ms.
The invention discloses a five-channel absolute angle encoder analyzing device which is fixed in an industrial personal computer through an ISA slot for use; the invention transmits unified clock signals and position information acquisition instructions to five absolute angle encoders 6 through the clock signal module 2 and the data signal module 2 respectively through the operation processing module 1; the signal sent to the data signal module by the operation processing module 1 controls the original position information of the five absolute angle encoders 6, the information is sequentially received by the operation processing module 1 through one path of port, and the position information is transmitted to the industrial personal computer through the ISA communication interface 4 after the operation processing module 1 analyzes the position information; the method optimizes the use of the port of the operation processing module 1 and can realize the position analysis of the five-channel absolute angle encoder.
Claims (6)
1. A five-channel absolute angle encoder analysis device comprises an operation processing module (1), a clock signal module (2), a data signal module (3), an ISA communication interface (4) and an absolute angle encoder interface (5); the device is characterized in that the operation processing module (1) comprises an FPGA programmable logic chip (8); one port of the FPGA programmable logic chip (8) is respectively connected with the input end of the five paths of clock data transceiver chips (13) of the clock signal module (2), the output end of the clock data transceiver chips (13) is connected with the clock RC filter circuit (12), and clock signals generated by the FPGA programmable logic chip (8) are respectively sent to the five absolute angle encoders (6) through the absolute angle encoder interfaces (5); five ports of the FPGA programmable logic chip (8) are connected with control ports of five paths of data transceiver chips (14) corresponding to the data signal module (3) to control data acquisition instructions and data input and output; one port of the FPGA programmable logic chip (8) is respectively connected with the input end of the five paths of data transceiver chips (14) of the data signal module (3), the output end of the data transceiver chips (14) is connected with the data RC filter circuit (15), and sampling position instructions generated by the FPGA programmable logic chip (8) are respectively sent to the five absolute angle encoders (6) through the absolute angle encoder interface (5) in a carrier mode; one port of the FPGA programmable logic chip (8) is respectively connected with the output ends of the five paths of data transceiver chips (14) of the data signal module (3), and the FPGA programmable logic chip (8) sends control signals to the data transceiver chips (14) in a time period of 5 k: in the first period, the output of the first path of data transceiver is valid, and the other four paths of output are invalid; the second period, the second transceiver output is valid, and the other four outputs are invalid; the third period, the output of the third transceiver is valid, and the other four outputs are invalid; the fourth period, the fourth transceiver output is valid, and the other four outputs are invalid; in the fifth period, the output of the fifth transceiver is valid, and the other four outputs are invalid; after receiving the original information of the angular position, the data transceiver chip (14) finishes the analysis of the angular position and then transmits the information to the industrial personal computer for use through the ISA communication interface (4).
2. The five-channel absolute angle encoder parsing apparatus according to claim 1, characterized in that the FPGA programmable logic chip (8) is EP2c8_144.
3. The five-channel absolute angle encoder parsing device according to claim 1, characterized in that the arithmetic processing module (1) further comprises a serial configuration chip (7), a clock circuit (11) and a power circuit (10); the serial configuration chip (7) is of the type EPCS16 and is used for storing software programs for the FPGA programmable logic chip (8); the clock circuit (11) is used for providing clock signals for the FPGA programmable logic chip (8).
4. The five-channel absolute angle encoder parsing device according to claim 1, wherein the clock signal module (2) comprises a five-channel clock data transceiver chip (13) and a five-channel clock filter circuit (12) for converting a single-ended clock signal sent by the operation processing module (1) into a differential clock signal and transmitting the differential clock signal to the absolute angle encoder interface (5).
5. The five-channel absolute angle encoder analyzing device according to claim 1, wherein the data signal module (3) comprises five paths of data transceiver chips (14) and five paths of filter circuits (15) for converting single-ended angular position acquisition command signals into differential angular position acquisition command signals, and controlling the original position information of the five absolute angle encoders (6) according to the signals output by the operation processing module (1), and the information is sequentially received by the operation processing module (1) through one path of ports.
6. The five-channel absolute angle encoder parsing apparatus according to claim 1, wherein the clock data transceiver chip (13) and the data transceiver chip (14) are each of the type MAX3485.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311462489.XA CN117606522A (en) | 2023-11-06 | 2023-11-06 | Five-channel absolute type angle encoder analysis device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311462489.XA CN117606522A (en) | 2023-11-06 | 2023-11-06 | Five-channel absolute type angle encoder analysis device |
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| Publication Number | Publication Date |
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| CN117606522A true CN117606522A (en) | 2024-02-27 |
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| CN202311462489.XA Pending CN117606522A (en) | 2023-11-06 | 2023-11-06 | Five-channel absolute type angle encoder analysis device |
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| CN (1) | CN117606522A (en) |
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- 2023-11-06 CN CN202311462489.XA patent/CN117606522A/en active Pending
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