CN218446445U

CN218446445U - Novel multi-protocol encoder and IO data acquisition unit

Info

Publication number: CN218446445U
Application number: CN202222769887.3U
Authority: CN
Inventors: 刘建东; 张云志; 任翀; 蒋倩
Original assignee: AVIC Beijing Aeronautical Manufacturing Technology Research Institute
Current assignee: AVIC Beijing Aeronautical Manufacturing Technology Research Institute
Priority date: 2022-10-20
Filing date: 2022-10-20
Publication date: 2023-02-03
Anticipated expiration: 2032-10-20

Abstract

The utility model provides a novel data collection station of multiprotocol encoder and IO data, the code analysis for solving present industrial field multiple protocol encoder data and multiple IO interface data, protocol conversion and bus data transmission scheduling problem, developed and realized increment encoder and BISS-C by a slice multinuclear DSP digital processor, enDat2.2, absolute value encoder data such as the multifriction river is handled to the agreement, and CAN gather multichannel digital switching value and analog sensor data, and through RS232, RS485, CAN, bus such as industrial ethernet carries out data transmission, compact structure's novel data collection station. The system has the characteristics of supporting various data interfaces and various coding protocols, can realize the online configuration of acquisition parameters, realizes the data acquisition of encoder data with various protocols and data of various sensors on a single board card in an industrial field, and is convenient for the data acquisition of various sensors of heterogeneous equipment on an automatic production line.

Description

Novel multi-protocol encoder and IO data acquisition unit

Technical Field

The utility model relates to an industrial automation control field especially relates to a novel data collection station of multiprotocol encoder and IO data.

Background

With the rapid development of unmanned factories and industrial automation fields, signal processing tasks of people are heavier and heavier, the requirements on the types and processing of industrial field real-time data acquisition are higher and higher, common data such as the data acquisition of sensor signals of voltage, current, thermocouples, pressure sensors and the like are required, and effective acquisition of parameters such as position, speed and the like is required to be completed by encoder signals of some control systems. The encoders applied to the industrial field are various in types, the encoders of various manufacturers generally adopt self-defined interfaces and protocols to transmit signals, and the encoder data acquisition modules used in the industrial field all analyze a single encoder protocol at present. Therefore, when field data acquisition is performed on heterogeneous equipment in a production line, a plurality of different encoder data acquisition cards or modules are required to be equipped, so that the cost and complexity of the system are increased. Therefore, a multifunctional data collector capable of independently collecting signals of multiple encoder protocols is needed.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

The utility model aims at solving the problems of coding analysis, protocol conversion and bus data transmission of the present industrial field multiple protocol encoder data and multiple IO interface data.

(II) technical scheme

In order to solve the technical problem, the utility model provides a novel data collection station of multiprotocol encoder and IO data, including increment encoder module, absolute value encoder module, digital quantity input/output and analog input interface module and multicore DSP processor module, multicore DSP processor module respectively with increment encoder module absolute value encoder module digital quantity input/output and analog input interface module link to each other.

Furthermore, the incremental encoder module comprises an incremental power supply encoder interface, a differential processing circuit and a conversion unit, the incremental power supply encoder interface is connected with the differential processing circuit, the differential processing circuit is connected with the conversion unit, and the conversion unit is connected with the multi-core DSP processor module.

Further, the incremental power encoder interface comprises A +, A-, B +, B-, I +, I-, + V and 0V, and the + V and 0V are connected with a power supply.

Further, the absolute value encoder interface of the absolute value encoder module comprises MA +, MA, SL +, SL, V + and V-connection power supplies.

Furthermore, the digital quantity input/output and analog quantity input interface module comprises a six-channel digital switching quantity input circuit, a four-channel digital switching quantity output circuit and a single-channel analog quantity input circuit.

Furthermore, the six-channel digital switching value input circuit comprises a digital input interface, a photoelectric isolation circuit and a processing circuit, wherein the digital input interface is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the processing circuit, and the processing circuit is connected with the multi-core DSP processor module.

Furthermore, the four-channel digital switching value output circuit comprises a digital output interface, a photoelectric isolation circuit and a processing circuit, wherein the digital output interface is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the processing circuit, and the processing circuit is connected with the multi-core DSP processor module.

Furthermore, the single-channel analog input circuit comprises an analog input interface and an amplification processing circuit, the analog input interface is connected with the amplification processing circuit, and the amplification processing circuit is connected with the multi-core DSP processor module.

Furthermore, the multi-core DSP processor module is respectively connected with the DC-DC power supply circuit, the data storage circuit, the RS485 interface circuit, the RS232 interface circuit and the industrial Ethernet interface circuit.

(III) advantageous effects

The above technical scheme of the utility model has following advantage:

1. the data acquisition of encoders with various protocols is realized on one acquisition card, so that the data acquisition of an A, B and C three-wire incremental encoder and a differential incremental encoder is realized, the data of single-turn and multi-turn absolute value encoders such as Endat2.2, moghan, BISS-C and the like can be acquired, the problem that signal processing devices of different types of encoders need to be accessed in an application system is effectively solved, the system is simple in structure, and the cost and the complexity of the system are reduced.

2. The data acquisition of the digital quantity IO and the analog quantity IO can also complete the data acquisition of multi-path input digital switching value, output switching value and analog quantity on the basis of realizing the data acquisition of the multi-protocol encoder, so that the data acquisition device can complete more functions in an industrial field, and the cost is reduced.

3. Compact structure miniaturization design, on the basis of guaranteeing to accomplish multiple function data acquisition, the hardware circuit adopts the design of multimode and multiply wood, has realized data collection station's miniaturization, and the installation space who occupies is very little, and convenience of customers uses in narrow and small space.

Drawings

FIG. 1 is a general block diagram of a novel multi-protocol encoder and data acquisition unit for IO data;

FIG. 2 is a schematic diagram of the structure of an incremental encoder module;

FIG. 3 is a schematic diagram of an absolute value encoder block;

FIG. 4 is a schematic diagram of the structure of the digital input/output and analog input interface module;

in the figure, 1: an incremental encoder module; 2. an absolute value encoder module; 3. the digital input/output and analog input interface module; 4. a multi-core DSP processor module; 5. a six-channel digital switching value input circuit; 6. a four-channel digital switching value output circuit; 7. a single-channel analog input circuit.

Detailed Description

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

As shown in fig. 1, the utility model provides a novel data collection station of multiprotocol encoder and IO data, including increment encoder module 1, absolute value encoder module 2, digital quantity input/output and analog quantity input interface module 3 and multicore DSP processor module 4, multicore DSP processor module 4 respectively with increment encoder module 1 absolute value encoder module 2 digital quantity input/output and analog quantity input interface module 3 link to each other.

The incremental encoder module 1 comprises an incremental encoder signal interface, is connected with the incremental encoder through an interface terminal and acquires a position signal of the incremental encoder, and the circuit receives three groups of pulse signals of the encoders A, B and Z to perform encoding processing and transmits the pulse signals into the DSP to perform decoding processing.

The absolute value encoder module 2 comprises a multi-protocol absolute value signal interface, receives a protocol signal of the absolute value encoder, determines the protocol form of the switched-on absolute value encoder through the parameter selection of the upper computer, and the DSP processor carries out corresponding absolute value encoding analysis.

The digital quantity input/output and analog quantity input interface module 3 comprises a six-channel digital switching value input circuit 5, a four-channel digital switching value output circuit 6 and a single-channel analog quantity input circuit 7.

The six-channel digital switching value input circuit 5 can be connected with 12-24V digital switching value signals, and the signals are converted into standard IO signals through filtering and photoelectric isolation circuit processing and then enter a DSP processor unit for digital processing. The four-channel digital switching value output circuit 6 and the DSP processor convert the IO signal into a digital switching value signal of 12-24V which can be processed on site through the photoelectric isolation processing circuit. The single-channel analog input circuit 7 amplifies and A/D converts the analog signal of 4-20mA or + -10V in the industrial field into IO signal which can be processed by DSP and then generates a digital signal with a certain digit.

The multi-core DSP processor module 4 comprises a single-chip multi-core DSP processor connected with an increment encoder unit, an absolute value encoder unit, a digital input unit, a digital output unit, an analog input unit, a storage unit, an industrial Ethernet communication unit, an RS232 communication unit and an RS485 communication unit, processes the functions of the different interfaces according to the configuration selection of upper computer software parameters, and generates corresponding data to be transmitted through a bus interface.

The data acquisition unit can acquire one path of incremental encoder signals through the functional parameter configuration of upper computer software, and simultaneously and selectively acquire one path of absolute value encoder signals of BISS-C, moghan and ENDAT2.2 protocols, and also can acquire six paths of digital switching value input signals, one path of 4-20mA or +/-10V analog signals and four paths of digital switching value output control signals. The collected signals can be transmitted to an upper computer through RS232, RS485 or industrial Ethernet and other buses. The acquired data can be interconnected through networks in various bus forms, and the method has the characteristics of flexible software configuration, rich data acquisition content, strong practicability and the like.

As shown in fig. 2, in some embodiments, the incremental encoder module 1 includes an incremental power encoder interface, a differential processing circuit, and a conversion unit, where the incremental power encoder interface is connected to the differential processing circuit, the differential processing circuit is connected to the conversion unit, and the conversion unit is connected to the multi-core DSP processor module 4. Further, the incremental power encoder interface comprises A +, A-, B +, B-, I +, I-, + V and 0V, and the + V and 0V are connected with a power supply.

In order to ensure high-quality signal transmission and reading and signal anti-interference capability, the incremental encoder interface circuit adopts a differential signal processing mode, and in the incremental pulse signals, every two signals are in a group and are respectively in a reverse direction. The encoder power supply comprises A + and A-, B + and B-, I + and I-, and + V and 0V. The differential signal of the incremental encoder firstly enters a differential signal processing circuit for processing balanced or unbalanced digital data transmission, so that only two kinds of data output are possible, and the reliability of the data is ensured. After differential signal processing, incremental encoder signals are changed into 3 tri-state output signals of A, B and I, and the three-state output signals are connected into a voltage level conversion circuit with ESD protection, wherein the voltage level conversion circuit converts the + V differential signal into an I/O signal with 3.3V level which can be accepted by a DSP processor. A. And B, enabling the I signal to enter a QEP orthogonal coding pulse module of the DSP, wherein the module comprises an orthogonal decoding unit (QDU), a Position Counter and Control Unit (PCCU), an edge capturing unit (QCAP), a timer reference Unit (UTIME) and a watchdog unit (QWDOG). Firstly, the QCLK internal clock signal, the QDIR direction signal and the QI synchronous signal are generated according to the input A, B and Z three-phase signals, and the part of work is completed by the QDU submodule. The polarity of the input signal, the source of the output, etc. may be configured. The generated QCLK signal is derived from the A and B two phase signal transition edges, which together with the QDIR direction signal determines the count up or down of the QPOSCNT register. In the orthogonal counting mode, the orthogonal decoding module generates a position counter clock signal and a direction signal, the CPU can record the pulse number of the incremental encoder by using the counting function of the timer, and simultaneously, the CPU can obtain whether the encoder forwards rotates or backwards rotates according to the phase of the encoder AB.

As shown in FIG. 2, in some embodiments, the absolute value encoder interface of the absolute value encoder module 2 comprises MA +, MA, SL +, SL, V +, and V-connected power supplies. The upper computer software can be selectively configured to acquire the signal of a BISS-C, a Mooney (T-Format) or an EnDat2.2 absolute value encoder. Location manager technology inside the DSP processor can provide an integrated solution to connect the most common digital and analog location sensors without the need for an external Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC). The connection between the CLB configurable logic module of the DSP processor and the XBAR can realize the signal acquisition of the I/O interfaces of the three encoders through software parameter configuration under the condition of the same hardware circuit. When the connection uses a BISS-C encoder, two signals MA (clock) and SL (data) are used for communication. In order to ensure the anti-interference capability of signals, a differential mode is adopted, namely MA +, MA, SL + and SL + are respectively a pair, and the full-duplex mode is adopted for communication. The other two wires V + and V-are used for the encoder power supply, where V-is typically GND. The MA-clock frequency is variable depending on the cable length. When a Morgan (T _ Format) encoder is used for connection, the DATA +, DATA-, power supply V + and power supply GND communicate through 4 signal lines, and four lines for communication comprise two wires for DATA + and DATA-which are transmitted in a differential manner, and a 5V power supply and a power supply ground wire for supplying power to the encoder. When the EnDat2.2 absolute value encoder is connected, the DATA +, the DATA-and CLOCK +, the CLOCK-and the 5V power supply are connected with the ground through six wires, and the signal transmission quality is ensured in a differential mode. The absolute value encoder signal is transmitted to a signal processing circuit module which comprises a differential drive and a differential receiver and operates under a single 3.3V power supply. The driver differential output and the receiver differential input are internally connected to form a bus port suitable for half-duplex (two-wire bus) communication. The module bus interface conforms to the RS485 bus standard, and the data bus interface is communicated with the DSP processor. The SPI bus inside the DSP processor performs the encoder data transmission and reception functions while the CLB controls clock generation. The CLB module generates two different clocks and adjusts the delay between the two clocks to ensure that the rising edges of the two clocks transmit and receive encoder data. The CLB also generates a direction signal for encoder data transfer, and the DSP processor configures the FIFO transmit signal of the SPI with commands and other data from the encoder according to the format and requirements of the absolute value encoder commands. The DSP performs digital decoding and arithmetic processing to obtain single-turn absolute position information, position subdivision information and period counting information, and position information of multi-turn absolute values can be obtained by reading and recording the single-turn absolute high-resolution position information. In addition, the DSP encoder analysis software carries out protocol analysis on a single-turn absolute value and a multi-turn absolute value according to the encoder signal type selected by a user, wherein the protocol analysis comprises absolute value encoder types of Morgan, BISS-C, endat and the like.

As shown in fig. 4, in some embodiments, the digital quantity input/output and analog quantity input interface module 3 includes a six-channel digital switching quantity input circuit 5, a four-channel digital switching quantity output circuit 6, and a single-channel analog quantity input circuit 7. Further, the six-channel digital switching value input circuit 5 comprises a digital input interface, a photoelectric isolation circuit and a processing circuit, wherein the digital input interface is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the processing circuit, and the processing circuit is connected with the multi-core DSP processor module 4. Further, the four-channel digital switching value output circuit 6 includes a digital output interface, a photoelectric isolation circuit and a processing circuit, the digital output interface is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the processing circuit, and the processing circuit is connected with the multi-core DSP processor module 4. Further, the single-channel analog input circuit 7 includes an analog input interface and an amplification processing circuit, the analog input interface is connected with the amplification processing circuit, and the amplification processing circuit is connected with the multi-core DSP processor module 4.

The digital quantity input/output and analog quantity input interface module 3 comprises a six-channel digital switching value input circuit 5, a four-channel digital switching value output circuit 6 and a single-channel analog quantity input circuit 7. The six digital input signals are accessed to the photoelectric isolation processing unit and are filtered, so that the anti-interference capability of the signals is improved. The six input channels can collect voltage type and passive contact type digital signals, when the external input is a level signal and the voltage of the input signal is less than 1V, the optocoupler is conducted, a low level is output, and the logic state is 0; when the voltage of the input signal is larger than 3.5V and smaller than 30V, the optical coupler is cut off, high level is output, and the logic state is 1. When the module is connected with a switch contact signal, when the switch is closed, the optocoupler is conducted, and the logic state is 0; when the switch is switched off, the optical coupler is switched off, and the logic state is 1. The four-way digital output circuit is also connected to the photoelectric isolation processing unit, the output adopts a collector open-drain output mode, a load and a pull-up power supply are required to be connected to an output port, the maximum load voltage is +30V, and the load current is 30mA. The DSP is controlled by upper computer software, when a signal control bit is written in a high level signal, the optocoupler is conducted, and an output pin outputs a low level signal; otherwise, the signal control bit is written into a low level signal, the optical coupler is cut off, and the output is pulled to be high level by an external pull-up resistor. The single-channel analog quantity input circuit is connected to the analog signal front end amplification processing circuit, and the signal processing circuit basically comprises a smoothing filter, an amplification gain adjusting circuit and an A/D conversion circuit. The smoothing filter is used for filtering the input signal, the amplification gain adjusting circuit is used for adjusting the signal to a proper voltage according to the amplitude of the input signal, the ADC is used for measuring the signal, and the analog signal is converted into a digital signal. The voltage input range is +/-10V, the current input range is 0-20 mA, and the received analog signals are of the type of universal control signals.

In some embodiments, the multi-core DSP processor module 4 is connected to the DC-DC power supply circuit, the data storage circuit, the RS485 interface circuit, the RS232 interface circuit, and the industrial ethernet interface circuit, respectively.

The DC-DC power supply circuit carries out filtering processing and voltage reduction conversion on a direct current 12V-24V power supply and outputs a stabilized voltage power supply, wherein the stabilized voltage power supply comprises 5V and 3.3VDC power supplies of various interfaces and circuits and a 1.2VDC power supply of a DSP processor.

The data storage circuit is used for storing parameter configuration data of each module in the system, and when the DSP processor is powered on, the content of the memory can be read firstly for data processing.

The industrial Ethernet interface circuit comprises an Ethernet controller with 100M bandwidth and a network transformer, and the incremental encoder data, the absolute value encoder data and the IO interface data can be in high-speed data communication with an upper computer through an industrial Ethernet bus.

The RS232 interface circuit is a standard serial data communication interface, provides data transmission with the maximum rate of 115200bps, and can be in data communication with an upper computer by adopting a Rx, tx and GND three-wire connection mode.

The RS485 interface circuit adopts a 50Mbps half-duplex RS485 module with an IEC ESD protection function, is provided with a differential driver and a differential receiver, is suitable for RS485 bus transmission of a long cable, and the data acquisition unit and the upper computer can adopt an MODBUS protocol for data exchange.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. The utility model provides a data collection station of novel multiprotocol encoder and IO data which characterized in that: the multi-core DSP processor module is respectively connected with the increment encoder module, the absolute value encoder module and the digital input/output and analog input interface module.

2. The novel data collector of multi-protocol encoder and IO data according to claim 1, wherein: the incremental encoder module comprises an incremental power encoder interface, a differential processing circuit and a conversion unit, wherein the incremental power encoder interface is connected with the differential processing circuit, the differential processing circuit is connected with the conversion unit, and the conversion unit is connected with the multi-core DSP processor module.

3. The novel data collector of the multi-protocol encoder and the IO data according to claim 2, characterized in that: the incremental power encoder interface comprises A +, A-, B +, B-, I +, I-, + V and 0V, and the + V and 0V are connected with a power supply.

4. The novel data collector of multi-protocol encoder and IO data according to claim 1, wherein: the absolute value encoder interface of the absolute value encoder module comprises MA +, MA, SL +, SL, V + and V-, and V + and V-are connected with a power supply.

5. The novel data collector of multi-protocol encoder and IO data according to claim 1, wherein: the digital quantity input/output and analog quantity input interface module comprises a six-channel digital switching value input circuit, a four-channel digital switching value output circuit and a single-channel analog quantity input circuit.

6. The novel data collector of multi-protocol encoder and IO data according to claim 5, wherein: the six-channel digital switching value input circuit comprises a digital input interface, a photoelectric isolation circuit and a processing circuit, wherein the digital input interface is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the processing circuit, and the processing circuit is connected with the multi-core DSP processor module.

7. The novel data collector of the multi-protocol encoder and the IO data according to claim 5, wherein: the four-channel digital switching value output circuit comprises a digital output interface, a photoelectric isolation circuit and a processing circuit, wherein the digital output interface is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the processing circuit, and the processing circuit is connected with the multi-core DSP processor module.

8. The novel data collector of multi-protocol encoder and IO data according to claim 5, wherein: the single-channel analog input circuit comprises an analog input interface and an amplification processing circuit, the analog input interface is connected with the amplification processing circuit, and the amplification processing circuit is connected with the multi-core DSP processor module.

9. The novel data collector of the multi-protocol encoder and the IO data according to any one of claims 1 to 8, wherein: and the multi-core DSP processor module is respectively connected with the DC-DC power supply circuit, the data storage circuit, the RS485 interface circuit, the RS232 interface circuit and the industrial Ethernet interface circuit.