CN116662235A - Interface for multi-protocol encoder - Google Patents
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- CN116662235A CN116662235A CN202310956352.3A CN202310956352A CN116662235A CN 116662235 A CN116662235 A CN 116662235A CN 202310956352 A CN202310956352 A CN 202310956352A CN 116662235 A CN116662235 A CN 116662235A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention relates to the field of interfaces, and discloses an interface for a multi-protocol encoder, which comprises a control system, an encoder data register set, a decoder set, a multi-path selection switch, a data transmission A channel and an RS485 interface circuit A which are connected in sequence; the device also comprises a data transmission B channel and an RS485 interface circuit B which are sequentially connected, wherein the data transmission B channel is connected with the multi-path selection switch; the device also comprises a transceiver controller, wherein the transceiver controller is connected with the multiplexing switch and then is respectively connected with the RS485 interface circuit A and the RS485 interface circuit B, and the transceiver controller is also respectively connected with the data transmission A channel and the data transmission B channel. The invention is provided with the double RS485 interface circuit, and is adaptive to encoders of various different protocols such as an incremental encoder, a multi-Mochuan encoder, an EnDat encoder, an SSI encoder, a BISS-C encoder and the like, without additionally adding a hardware interface, thereby improving the compatibility of the invention.
Description
Technical Field
The present invention relates to the field of interfaces, and in particular, to an interface for a multi-protocol encoder.
Background
With the rapid development of industrial automation, the application of numerical control systems and industrial robots is becoming more and more widespread. In the development process that the market is gradually refined, the demand is further clear, and the differentiated competition is gradually becoming the mainstream, in the fixed field of equiaxial number of numerical control system and robot, a control and driving integrated system is derived, and an automatic control system with higher efficiency, better performance, smaller volume and lower cost is formed by integrating control and driving circuits. The servo drive system is an important component part of the control and drive integrated system. In the servo drive system, an encoder is often employed as a position detecting element. Different application systems will choose different encoders according to design requirements, but encoders of each manufacturer usually adopt different standard protocols for signal transmission, so that different encoders often need to be connected with matching hardware interfaces and protocols. In the prior art, a servo drive system usually only can support a communication protocol of one encoder, if other encoder communication protocols need to be adapted, a plurality of different types of encoder data acquisition cards or modules need to be equipped, thereby increasing the cost and complexity of the system. In order to reduce the complexity of the hardware structure, some servo driving systems do not need to replace a servo control circuit board when supporting multiple communication protocol encoders, but need to re-download FPGA firmware. For a complex customer site for installing a servo drive system, when encoders with different communication protocols need to be replaced, the FPGA firmware needs to be downloaded again by disassembling equipment, so that the maintenance workload of products is greatly increased, and the production efficiency is reduced. Thus, there is a need for a generic interface that can adapt to a variety of encoder protocols.
Disclosure of Invention
The present invention aims to solve the above problems and provide an interface for a multi-protocol encoder, which adapts encoders of a plurality of different protocols including but not limited to incremental encoder, multi-Moire encoder, endat encoder, SSI encoder and BISS-C encoder through a double 485 interface circuit, and reduces the system cost. Meanwhile, decoders of different protocols are integrated, different decoding protocols are switched through a multi-path selection switch, so that the compatibility of interfaces is improved, the maintenance workload of a system is reduced, and the problems of poor interface suitability and low compatibility of the existing encoder are solved.
To achieve the purpose, the invention adopts the following technical scheme:
an interface for a multi-protocol encoder comprises a control system, an encoder data register set, a decoder set, a multi-path selection switch, a data transmission A channel and an RS485 interface circuit A which are connected in sequence; the device also comprises a data transmission B channel and an RS485 interface circuit B which are sequentially connected, wherein the data transmission B channel is connected with the multi-path selection switch; the device also comprises a receiving and transmitting controller, wherein the receiving and transmitting controller is connected with the multi-path selection switch and then is respectively connected with the RS485 interface circuit A and the RS485 interface circuit B, and the receiving and transmitting controller is also respectively connected with a data transmission A channel and a data transmission B channel;
the RS485 interface circuit A and the RS485 interface circuit B are used for connecting an external encoder, and the control system alternatively or simultaneously exchanges data with the RS485 interface circuit A and the RS485 interface circuit B;
the control system is used for sending configuration parameters to the encoder data register set and reading feedback data of the encoder data register set;
the encoder data register set is used for transmitting the configuration parameters to the decoder set and reading the feedback data of the decoder set, and simultaneously is used for transmitting the enabling signals to the decoder set, wherein the decoder set comprises a plurality of decoders, and the decoder set enables the decoder of the adaptive external encoder after receiving the enabling signals;
the encoder data register group is simultaneously used for sending a switch selection signal to the multi-path selection switch, and the multi-path selection switch receives the switch selection signal and communicates the decoder group with the data transmission A channel and/or the data transmission B channel according to the switch selection signal;
when the decoder group is communicated with the data transmission A channel and/or the data transmission B channel, the decoder group generates a receiving and transmitting control signal, the receiving and transmitting control signal is transmitted to the RS485 interface circuit A and/or the RS485 interface circuit B through the multiplexing switch and the receiving and transmitting controller, and the RS485 interface circuit A and/or the RS485 interface circuit B receive the receiving and transmitting control signal and correspondingly enter a transmitting mode or a receiving mode;
the decoder group also generates control data, and sends the control data to the data transmission A channel and/or the data transmission B channel through the multi-way selection switch, and the data transmission A channel and the data transmission B channel also respectively receive clock control data;
when the RS485 interface circuit A and/or the RS485 interface circuit B enter a transmission mode, the decoder group generates a data selection signal, the data selection signal is transmitted to a data transmission A channel and/or a data transmission B channel through a multiplexing switch and a transceiver controller, the data transmission A channel and/or the data transmission B channel select to transmit to the RS485 interface circuit A and/or the RS485 interface circuit B from clock control data or control data based on the data selection signal, and the transmission of the control data or the clock control data of the RS485 interface circuit A and/or the RS485 interface circuit B by the decoder group is realized; then the control data or clock control data is sent to the external encoder through the RS485 interface circuit A and/or the RS485 interface circuit B;
when the RS485 interface circuit A and/or the RS485 interface circuit B enter a receiving mode, the decoder group receives response data from the external encoder through the data transmission A channel and/or the data transmission B channel and the multiplexing switch, and the RS485 interface circuit A and/or the RS485 interface circuit B receives the response data.
Preferably, the decoder group includes an incremental decoder, a multi-molton decoder, an EnDat decoder, an SSI decoder, and a BISS-C decoder.
Preferably, the data transmission channel A comprises a transmission buffer A, a transmission selector A and a transmitter A which are sequentially connected between the multiplexing switch and the RS485 interface circuit A, wherein the transmission and reception controller is connected with the transmission selector A, the transmission selector A is used for receiving a data selection signal of the transmission and reception controller, and simultaneously, the transmission selector A receives clock control data and control data sent by the transmission buffer A, and the transmission selector A sends clock control data or control data to the transmitter A based on one of the data selection signals; the data transmission B channel comprises a transmission buffer B, a transmission selector B and a transmitter B which are sequentially connected between the multiplexing switch and the RS485 interface circuit B, the transceiver controller is connected with the transmission selector B, the transmission selector B is used for receiving a data selection signal of the transceiver controller, and meanwhile, the transmission selector B receives clock control data and control data sent by the transmission buffer B, and the transmission selector B sends clock control data or control data to the transmitter B based on one of the data selection signals.
Preferably, the transmitter a further receives a synchronous clock, and sends clock control data or control data sent by the transmission selector a to the RS485 interface circuit a based on the synchronous clock; the transmitter B also receives a synchronous clock, and transmits clock control data or control data transmitted by the transmission selector B to the RS485 interface circuit B based on the synchronous clock.
Preferably, the data transmission channel A further comprises a receiver A and a receiving buffer A, wherein the receiver A and the receiving buffer A are sequentially connected between the RS485 interface circuit A and the multiplexing switch, the receiver A is used for receiving a synchronous clock, and transmitting response data received by the RS485 interface circuit A to the receiving buffer A based on the synchronous clock, and the receiving buffer A transmits the response data to the multiplexing switch; the data transmission B channel further comprises a receiver B and a receiving buffer B which are sequentially connected between the RS485 interface circuit B and the multiplexing switch, wherein the receiver B is used for receiving a synchronous clock and transmitting response data received by the RS485 interface circuit B to the receiving buffer B based on the synchronous clock, and the receiving buffer B transmits the response data to the multiplexing switch.
Preferably, the external connection encoder connected with the RS485 interface circuit A and the RS485 interface circuit B is an asynchronous communication encoder, a synchronous communication encoder or an incremental encoder, the RS485 interface circuit A and the RS485 interface circuit B are alternatively connected with one asynchronous communication encoder, or the RS485 interface circuit A and the RS485 interface circuit B are respectively connected with two asynchronous communication encoders, or the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same synchronous communication encoder, or the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same incremental encoder.
Preferably, when the RS485 interface circuit a and the RS485 interface circuit B are connected with two ports of the same synchronous communication encoder, and both the RS485 interface circuit a and the RS485 interface circuit B enter a transmission mode, a data transmission channel a is used for transmitting clock control data, and a data transmission channel B is used for transmitting control data; or the data transmission B channel is used for transmitting clock control data, and the data transmission A channel is used for transmitting control data.
Preferably, when the RS485 interface circuit a and the RS485 interface circuit B are connected to two ports of the same incremental encoder, both the RS485 interface circuit a and the RS485 interface circuit B only enter a receiving mode.
The contribution of the invention is as follows: the double RS485 interface circuit is arranged to externally connect different types of encoders, and the encoders with different protocols including but not limited to an incremental encoder, a multi-Mochuan encoder, an Endat encoder, an SSI encoder, a BISS-C encoder and the like can be adapted under the condition that a plurality of types of different encoder data acquisition cards or modules are not required to be equipped and the FPGA firmware is not required to be downloaded again by disassembling equipment through the cooperation of the decoder group, the multi-path selection switch, the transceiver controller, the data transmission channel and the interface circuit. The interface on hardware is not required to be additionally added, the cost of the system is reduced, different encoders can be decoded by arranging a multi-path selection switch and a decoder group on the interface, and the compatibility of the interface of the invention is improved.
Drawings
Fig. 1 is a schematic diagram of the structure of the interface of the present invention.
Fig. 2 is a block diagram of one embodiment of an interface of the present invention.
Detailed Description
The following examples are further illustrative and supplementary of the present invention and are not intended to limit the invention in any way.
Example 1
As shown in fig. 1 and 2, the device comprises a control system, an encoder data register set, a decoder set, a multi-path selection switch, a data transmission A channel and an RS485 interface circuit A which are connected in sequence; the device also comprises a data transmission B channel and an RS485 interface circuit B which are sequentially connected, wherein the data transmission B channel is connected with the multi-path selection switch; the device also comprises a receiving and transmitting controller, wherein the receiving and transmitting controller is connected with the multi-path selection switch and then is respectively connected with the RS485 interface circuit A and the RS485 interface circuit B, and the receiving and transmitting controller is also respectively connected with a data transmission A channel and a data transmission B channel; the RS485 interface circuit A and the RS485 interface circuit B are used for connecting an external encoder, and the control system alternatively or simultaneously exchanges data with the RS485 interface circuit A and the RS485 interface circuit B; the control system is used for sending configuration parameters to the encoder data register set and reading feedback data of the encoder data register set; the encoder data register set is used for transmitting the configuration parameters to the decoder set and reading the feedback data of the decoder set, and simultaneously is used for transmitting the enabling signals to the decoder set, wherein the decoder set comprises a plurality of decoders, and the decoder set enables the decoder of the adaptive external encoder after receiving the enabling signals; the encoder data register group is simultaneously used for sending a switch selection signal to the multi-path selection switch, and the multi-path selection switch receives the switch selection signal and communicates the decoder group with the data transmission A channel and/or the data transmission B channel according to the switch selection signal; when the decoder group is communicated with the data transmission A channel and/or the data transmission B channel, the decoder group generates a receiving and transmitting control signal, the receiving and transmitting control signal is transmitted to the RS485 interface circuit A and/or the RS485 interface circuit B through the multiplexing switch and the receiving and transmitting controller, and the RS485 interface circuit A and/or the RS485 interface circuit B receive the receiving and transmitting control signal and correspondingly enter a transmitting mode or a receiving mode; the decoder group also generates control data, and sends the control data to the data transmission A channel and/or the data transmission B channel through the multi-way selection switch, and the data transmission A channel and the data transmission B channel also respectively receive clock control data; when the RS485 interface circuit A and/or the RS485 interface circuit B enter a transmission mode, the decoder group generates a data selection signal, the data selection signal is transmitted to a data transmission A channel and/or a data transmission B channel through a multiplexing switch and a transceiver controller, the data transmission A channel and/or the data transmission B channel select to transmit to the RS485 interface circuit A and/or the RS485 interface circuit B from clock control data or control data based on the data selection signal, and the transmission of the control data or the clock control data of the RS485 interface circuit A and/or the RS485 interface circuit B by the decoder group is realized; then the control data or clock control data is sent to the external encoder through the RS485 interface circuit A and/or the RS485 interface circuit B; when the RS485 interface circuit A and/or the RS485 interface circuit B enter a receiving mode, the decoder group receives response data from the external encoder through the data transmission A channel and/or the data transmission B channel and the multiplexing switch, and the RS485 interface circuit A and/or the RS485 interface circuit B receives the response data. The decoder set includes, but is not limited to, an incremental decoder, a multi-Moire decoder, an Endat decoder, an SSI decoder, and a BISS-C decoder. The external connection encoder is used for adapting the external connection encoder, and the external connection encoder connected through the RS485 interface circuit A and/or the RS485 interface circuit B can correspondingly adopt an incremental encoder, a multi-Mochuann encoder, an EnDat encoder, an SSI encoder and a BISS-C encoder to improve the compatibility of the interface.
The delta decoder, the polymorphous decoder, the EnDat decoder, the SSI decoder and the BISS-C decoder described above are actually divided into three different types.
The first is an asynchronous communication decoder, and a multi-Moire decoder belongs to the type, and can decode the multi-Moire encoder; in this case, the RS485 interface circuit a and the RS485 interface circuit B are alternatively connected to one asynchronous communication encoder, or the RS485 interface circuit a and the RS485 interface circuit B are respectively connected to two different asynchronous communication encoders. The second is a synchronous communication decoder, to which the EnDat decoder, the SSI decoder, and the BISS-C decoder belong, and the EnDat decoder, the SSI decoder, and the BISS-C decoder can correspondingly decode the EnDat encoder, the SSI encoder, and the BISS-C encoder; in this case, the RS485 interface circuit a and the RS485 interface circuit AB are connected to two ports of the same synchronous communication encoder. The third is an incremental decoder, which can decode an incremental encoder. In this case, the RS485 interface circuit a and the RS485 interface circuit B are connected to two ports of the same incremental encoder.
The following describes how the data interaction between the control system and the RS485 interface circuit a is implemented by taking the RS485 interface circuit a connected to a first type of asynchronous communication encoder, specifically a polymichuan encoder as an example.
The control system sends the configuration parameters to the encoder data register set, the encoder data register set sends the configuration parameters to the decoder set, the configuration parameters comprise a multi-Mochuan decoder option and a channel configuration option, the encoder data register set is simultaneously used for sending enabling signals to the decoder set, the decoder set at least comprises a multi-Mochuan decoder, and the multi-Mochuan decoder can be used for decoding a multi-Mochuan encoder externally connected with the RS485 interface circuit A; the decoder group enables the multi-Moire decoder according to the enabling signal; the encoder data register sends a switch selection signal to the multi-path selection switch, and the multi-path selection switch is communicated with the data transmission A channel and the decoder group according to the switch selection signal, and specifically, the multi-path selection switch is communicated with the multi-Mochuanxi decoder in the data transmission A channel and the decoder group according to the switch selection signal.
When the multi-Mochuan decoder is communicated with the data transmission A channel, the decoder group can send out a receiving and transmitting control signal, namely the multi-Mochuan decoder can send out the receiving and transmitting control signal, the receiving and transmitting control signal comprises a sending control signal and a receiving control signal, the receiving and transmitting control signal is sent to the RS485 interface circuit A through a multi-path selection switch and the receiving and transmitting controller, the RS485 interface circuit A correspondingly enters a sending mode or a receiving mode, more particularly, if the multi-Mochuan decoder sends out the sending control signal, the RS485 interface circuit A enters the sending mode; if the multi-Moire decoder sends out a receiving control signal, the RS485 interface circuit A enters a receiving mode.
When the RS485 interface circuit A enters a transmitting mode, the multi-Moire decoder transmits control data to the data transmission A channel through the multi-path selection switch, wherein the control data is used for requesting response data from the multi-Moire encoder, and the response data is data generated after sampling and encoding of the multi-Moire encoder. The data transmission A channel also receives clock control data; the multi-channel decoder also transmits a data selection signal, wherein the data selection signal comprises selection control data transmission and selection clock control data transmission. The multi-channel decoder sends a data selection signal for selecting and controlling data transmission, and sends the data selection signal for selecting and controlling data transmission to the data transmission A channel through the multi-channel selection switch and the transceiver controller, and the data transmission A channel selects and controls data to be transmitted to the RS485 interface circuit A from clock control data and control data according to the received data selection signal for selecting and controlling data, so that data transmission between the control system and the RS485 interface circuit A is completed. The RS485 interface circuit A sends the control data to the connected multi-Moire encoder. When the multi-Moire encoder receives control data requesting response data, data sampling is performed and response data is generated for transmission.
When the RS485 interface circuit A enters a receiving mode, the RS485 interface circuit A receives response data from the multi-Mochuanxi encoder connected with the RS485 interface circuit A and sends the response data to the decoder group through a data transmission A channel and a multi-channel selection switch, and particularly, the response data is sent to the multi-Mochuanxi decoder in the decoder group through the data transmission A channel and the multi-channel selection switch. The multi-Moire decoder decodes and latches the response data into feedback data for the encoder register set to read, and the encoder data register reads the feedback data and latches for the control system to read. Thereby realizing the data receiving between the control system and the RS485 interface circuit A.
When the RS485 interface circuit B is connected with the asynchronous communication encoder, the data interaction between the control system and the RS485 interface circuit B is realized by referring to the mode of the RS485 interface circuit A.
When the RS485 interface circuit A and the RS485 interface circuit B are simultaneously connected with two different asynchronous communication encoders, the control system also performs data interaction with the RS485 interface circuit A and the RS485 interface circuit B respectively by referring to the mode of the RS485 interface circuit A.
If the external encoder connected to the RS485 interface circuit a and the RS485 interface circuit B is a second type of synchronous communication encoder, the external encoder is slightly different from the asynchronous communication encoder in the implementation due to the requirement of communication synchronization, and this condition requires that the RS485 interface circuit a and the RS485 interface circuit B are simultaneously connected to two different ports of the same synchronous communication encoder.
In the following, an example is taken in which the RS485 interface circuit a and the RS485 interface circuit B are simultaneously connected to two different ports of the same second type synchronous communication encoder, specifically, the RS485 interface circuit a and the RS485 interface circuit B are simultaneously connected to two different ports of the same SSI encoder, so as to illustrate how the data interaction between the control system and the RS485 interface circuit a and the RS485 interface circuit B is realized in the embodiment. When the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same synchronous communication encoder, the RS485 interface circuit A and the RS485 interface circuit B enter a transmission mode, a data transmission A channel is used for transmitting clock control data, and a data transmission B channel is used for transmitting control data; or the data transmission B channel is used for transmitting clock control data, and the data transmission A channel is used for transmitting control data.
The control system sends the configuration parameters to the encoder data register set, the encoder data register set sends the configuration parameters to the decoder set, the configuration parameters comprise SSI encoder options and channel configuration options, the SSI encoder is provided with a channel 1 and a channel 2, the encoder data register set is simultaneously used for sending enabling signals to the decoder set, the decoder set at least comprises an SSI decoder, and the SSI decoder can be used for decoding SSI encoders externally connected with an RS485 interface circuit A and an RS485 interface circuit B; the decoder group enables the SSI decoder according to the enabling signal, the encoder data register sends a switch selection signal to the multi-path selection switch, the multi-path selection switch is communicated with the data transmission A channel and the decoder group according to the switch selection signal and is also communicated with the data transmission B channel and the decoder group, specifically, the multi-path selection switch is communicated with the data transmission A channel and the channel 1 of the SSI decoder according to the switch selection signal, and at the moment, the channel 1 of the SSI decoder, the multi-path selection switch, the data transmission A channel and the RS485 interface circuit A form a complete channel which is used as a clock control channel; the multi-path selection switch is communicated with a data transmission B path and a path 2 of the SSI decoder according to a switch selection signal, and at the moment, the path 2 of the SSI decoder, the multi-path selection switch, the data transmission B path and the RS485 interface circuit B form a complete path which is used as a data receiving and transmitting path;
when the channel 1 of the SSI decoder is connected with the data transmission channel a as a clock control channel and the channel 2 of the SSI decoder is connected with the data transmission channel B as a data receiving and transmitting channel, the decoder group sends out a receiving and transmitting control signal, specifically, the channel 1 of the SSI decoder sends out a sending control signal to the RS485 interface circuit a through the multiplexing switch and the receiving and transmitting controller, the RS485 interface circuit a enters a sending mode, the channel 2 of the SSI decoder sends out a sending control signal or a receiving control signal to the RS485 interface circuit B through the multiplexing switch and the receiving and transmitting controller, the RS485 interface circuit B enters a sending mode or a receiving mode, more specifically, the channel 2 of the SSI decoder sends out a sending control signal, the RS485 interface circuit B enters a sending mode, and the channel 2 of the SSI decoder sends out a receiving control signal, then the RS485 interface circuit B enters a receiving mode.
When the RS485 interface circuit A is used as a clock control channel to enter a transmitting mode, the SSI decoder transmits a data selection signal for selecting clock control data to the data transmission A channel through the multi-channel selection switch and the transceiver controller, and the data transmission A channel selects the clock control data from the clock control data and the control data according to the received data selection signal for selecting the clock control data and transmits the clock control data to the RS485 interface circuit A as a synchronous clock for establishing communication with the SSI encoder. When the RS485 interface circuit B is used as a data receiving and transmitting channel to enter a transmitting mode, the SSI decoder transmits control data to a data transmission B channel through a multi-way selection switch, wherein the control data is used for requesting response data from an SSI encoder; the data transmission B channel also receives clock control data; meanwhile, the SSI decoder also sends a data selection signal for selecting and controlling data to be sent to a data transmission B channel through a multi-channel selection switch and a transceiver controller, and the data transmission B channel selects and controls data to be sent to an RS485 interface circuit B from clock control data and control data according to the received data selection signal for selecting and controlling data to send data between a control system and the RS485 interface circuit B. In addition, through the channel configuration option, the data transmission A channel can also be configured to transmit control data, and the data transmission B channel can also transmit clock control data. When the RS485 interface circuit A and the RS485 interface circuit B receive corresponding control data or clock control data, the data transmission between the control system and the RS485 interface circuit A and the RS485 interface circuit B is realized. The RS485 interface circuit A and the RS485 interface circuit B send the received data to the corresponding port connected with the SSI encoder, and the SSI encoder samples and generates response data after receiving clock control data or control data. The response data herein refers to data generated after sampling and encoding by the SSI encoder.
When the RS485 interface circuit B as a data receiving and transmitting channel enters a receiving mode, the RS485 interface circuit B receives response data from an SSI encoder connected with the RS485 interface circuit B and sends the response data to a decoder group through a data transmission B channel and a multiplexing switch, in particular to a channel 2 of the SSI decoder through the data transmission B channel and the multiplexing switch. The SSI decoder decodes and latches the response data into feedback data that the encoder data register reads and latches for the control system to read. Thereby realizing the data receiving between the control system and the RS485 interface circuit A and the RS485 interface circuit B.
If the externally connected encoders connected to the RS485 interface circuit a and the RS485 interface circuit B are of the third type of incremental encoder, the implementation will be slightly different from the first two since their communication is only for reception and not for transmission. This situation requires that the RS485 interface circuit a and the RS485 interface circuit B are simultaneously connected to two different ports of the same incremental encoder, and neither the RS485 interface circuit a nor the RS485 interface circuit B enter the transmit mode, but only enter the receive mode.
The following describes how the control system interacts with the data of the RS485 interface circuit a and the RS485 interface circuit B by taking the example that the RS485 interface circuit a and the RS485 interface circuit B are simultaneously connected with two different ports of the same third type incremental encoder.
The control system sends the configuration parameters to the encoder data register set, the encoder data register set sends the configuration parameters to the decoder set, the configuration parameters comprise incremental decoder options and channel configuration options, the encoder data register set is simultaneously used for sending enabling signals to the decoder set, and the decoder set at least comprises incremental decoders which can be used for decoding incremental encoders externally connected with the RS485 interface circuit A and the RS485 interface circuit B; the decoder group enables the incremental decoder according to the enabling signal, the encoder data register sends a switch selection signal to the multi-path selection switch, the multi-path selection switch is communicated with the data transmission A channel and the decoder group according to the switch selection signal and is also communicated with the data transmission B channel and the decoder group at the same time, and the multi-path selection switch is communicated with the incremental decoder in the data transmission A channel and the decoder group according to the switch selection signal and is also communicated with the incremental decoder in the data transmission B channel and the decoder group at the same time.
When the incremental decoder is communicated with the data transmission A channel and the data transmission B channel, the decoder group can send out a receiving and transmitting control signal, specifically the incremental decoder can send out a receiving control signal, and the receiving control signal is sent to the RS485 interface circuit A and the RS485 interface circuit B through the multiplexing switch and the receiving and transmitting controller, so that the RS485 interface circuit A and the RS485 interface circuit B both enter a receiving mode.
When the RS485 interface circuit A and the RS485 interface circuit B both enter a receiving mode, the RS485 interface circuit A and the RS485 interface circuit B simultaneously receive response data from an incremental encoder connected with the RS485 interface circuit A and the RS485 interface circuit B, wherein the response data refer to data generated after sampling and encoding of the incremental encoder, and the response data are respectively sent to a decoder group through a data transmission A channel, a data transmission B channel and a multiplexing switch, and specifically, the response data are sent to incremental decoders in the decoder group through the data transmission A channel, the data transmission B channel and the multiplexing switch. The incremental decoder decodes and latches the response data as feedback data that the encoder data register reads and latches for the control system to read. Thereby realizing the data receiving between the control system and the RS485 interface circuit A and the RS485 interface circuit B.
Example 2
As shown in fig. 2, the present embodiment perfects the structure of a data transmission a channel and a data transmission B channel, where the data transmission a channel includes a transmission buffer a, a transmission selector a, and a transmitter a sequentially connected between a multiplexing switch and an RS485 interface circuit a, the transmission selector a is connected to the transmission selector a, and the transmission selector a is used to receive a data selection signal of the transmission controller, and at the same time, the transmission selector a receives clock control data and control data sent by the transmission buffer a, and the transmission selector a sends clock control data or control data to the transmitter a based on one of the data selection signals; the data transmission B channel comprises a transmission buffer B, a transmission selector B and a transmitter B which are sequentially connected between the multiplexing switch and the RS485 interface circuit B, the transceiver controller is connected with the transmission selector B, the transmission selector B is used for receiving a data selection signal of the transceiver controller, and meanwhile, the transmission selector B receives clock control data and control data sent by the transmission buffer B, and the transmission selector B sends clock control data or control data to the transmitter B based on one of the data selection signals. The transmitter A also receives a synchronous clock, and transmits clock control data or control data transmitted by the transmission selector A to the RS485 interface circuit A based on the synchronous clock; the transmitter B also receives a synchronous clock, and transmits clock control data or control data transmitted by the transmission selector B to the RS485 interface circuit B based on the synchronous clock.
In the following, a data transmission a channel is taken as an example of how the data transmission a channel realizes transmission and transmission, control data sent by a decoder group is sent to a sending buffer a in the data transmission a channel through a multiplexing switch, the sending selector a receives the control data and simultaneously receives clock control data and a data selection signal sent by a transceiver controller, the sending selector a sends one of the control data and the clock control data to a sender a based on the data selection signal, the sender a also receives a synchronous clock, and the sender sends the received control data or clock control data to an RS485 interface circuit a based on the synchronous clock.
The data transmission B channel refers to the data transmission A channel to realize transmission and sending.
Example 3
As shown in fig. 2, the present embodiment perfects the structures of a data transmission a channel and a data transmission B channel, the data transmission a channel further includes a receiver a and a receiving buffer a sequentially connected between the RS485 interface circuit a and the multiplexing switch, the receiver a is configured to receive a synchronous clock, and send response data received by the RS485 interface circuit a to the receiving buffer a based on the synchronous clock, and the receiving buffer a sends the response data to the multiplexing switch;
the data transmission B channel further comprises a receiver B and a receiving buffer B which are sequentially connected between the RS485 interface circuit B and the multiplexing switch, wherein the receiver B is used for receiving a synchronous clock and transmitting response data received by the RS485 interface circuit B to the receiving buffer B based on the synchronous clock, and the receiving buffer B transmits the response data to the multiplexing switch.
In the following, a data transmission a channel is taken as an example of how the data transmission a channel realizes transmission and reception, after receiving response data of an external encoder, the RS485 interface circuit a sends the response data to the receiver a, and the receiver a also receives a synchronous clock, and the receiver a sends the response data to the receiving buffer a based on the synchronous clock, and the receiving buffer a sends the response data to the multiplexing switch.
The data transmission B channel refers to the data transmission A channel to realize transmission and reception.
Although the present invention has been disclosed by the above embodiments, the scope of the present invention is not limited thereto, and modifications, substitutions, etc. made to the above components will fall within the scope of the claims of the present invention without departing from the spirit of the present invention.
Claims (8)
1. The interface for the multi-protocol encoder is characterized by comprising a control system, an encoder data register set, a decoder set, a multi-path selection switch, a data transmission A channel and an RS485 interface circuit A which are connected in sequence; the device also comprises a data transmission B channel and an RS485 interface circuit B which are sequentially connected, wherein the data transmission B channel is connected with the multi-path selection switch; the device also comprises a receiving and transmitting controller, wherein the receiving and transmitting controller is connected with the multi-path selection switch and then is respectively connected with the RS485 interface circuit A and the RS485 interface circuit B, and the receiving and transmitting controller is also respectively connected with a data transmission A channel and a data transmission B channel;
the RS485 interface circuit A and the RS485 interface circuit B are used for connecting an external encoder, and the control system alternatively or simultaneously exchanges data with the RS485 interface circuit A and the RS485 interface circuit B;
the control system is used for sending configuration parameters to the encoder data register set and reading feedback data of the encoder data register set;
the encoder data register set is used for transmitting the configuration parameters to the decoder set and reading the feedback data of the decoder set, and simultaneously is used for transmitting the enabling signals to the decoder set, wherein the decoder set comprises a plurality of decoders, and the decoder set enables the decoder of the adaptive external encoder after receiving the enabling signals;
the encoder data register group is simultaneously used for sending a switch selection signal to the multi-path selection switch, and the multi-path selection switch receives the switch selection signal and communicates the decoder group with the data transmission A channel and/or the data transmission B channel according to the switch selection signal;
when the decoder group is communicated with the data transmission A channel and/or the data transmission B channel, the decoder group generates a receiving and transmitting control signal, the receiving and transmitting control signal is transmitted to the RS485 interface circuit A and/or the RS485 interface circuit B through the multiplexing switch and the receiving and transmitting controller, and the RS485 interface circuit A and/or the RS485 interface circuit B receive the receiving and transmitting control signal and correspondingly enter a transmitting mode or a receiving mode;
the decoder group also generates control data, and sends the control data to the data transmission A channel and/or the data transmission B channel through the multi-way selection switch, and the data transmission A channel and the data transmission B channel also respectively receive clock control data;
when the RS485 interface circuit A and/or the RS485 interface circuit B enter a transmission mode, the decoder group generates a data selection signal, the data selection signal is transmitted to a data transmission A channel and/or a data transmission B channel through a multiplexing switch and a transceiver controller, the data transmission A channel and/or the data transmission B channel select to transmit to the RS485 interface circuit A and/or the RS485 interface circuit B from clock control data or control data based on the data selection signal, and the transmission of the control data or the clock control data of the RS485 interface circuit A and/or the RS485 interface circuit B by the decoder group is realized; then the control data or clock control data is sent to the external encoder through the RS485 interface circuit A and/or the RS485 interface circuit B;
when the RS485 interface circuit A and/or the RS485 interface circuit B enter a receiving mode, the decoder group receives response data from the external encoder through the data transmission A channel and/or the data transmission B channel and the multiplexing switch, and the RS485 interface circuit A and/or the RS485 interface circuit B receives the response data.
2. An interface for a multi-protocol encoder as claimed in claim 1, wherein: the decoder group comprises an incremental decoder, a multi-Mouch decoder, an Endat decoder, an SSI decoder and a BISS-C decoder.
3. An interface for a multi-protocol encoder as claimed in claim 2, wherein: the data transmission A channel comprises a transmission buffer A, a transmission selector A and a transmitter A which are sequentially connected between a multiplexing switch and an RS485 interface circuit A, wherein a transceiver controller is connected with the transmission selector A, the transmission selector A is used for receiving a data selection signal of the transceiver controller, and simultaneously, the transmission selector A receives clock control data and control data transmitted by the transmission buffer A, and the transmission selector A transmits clock control data or control data to the transmitter A based on one of the data selection signals;
the data transmission B channel comprises a transmission buffer B, a transmission selector B and a transmitter B which are sequentially connected between the multiplexing switch and the RS485 interface circuit B, the transceiver controller is connected with the transmission selector B, the transmission selector B is used for receiving a data selection signal of the transceiver controller, and meanwhile, the transmission selector B receives clock control data and control data sent by the transmission buffer B, and the transmission selector B sends clock control data or control data to the transmitter B based on one of the data selection signals.
4. An interface for a multi-protocol encoder according to claim 3, characterized in that: the transmitter A also receives a synchronous clock, and transmits clock control data or control data transmitted by the transmission selector A to the RS485 interface circuit A based on the synchronous clock;
the transmitter B also receives a synchronous clock, and transmits clock control data or control data transmitted by the transmission selector B to the RS485 interface circuit B based on the synchronous clock.
5. An interface for a multi-protocol encoder as defined in claim 4, wherein: the data transmission A channel also comprises a receiver A and a receiving buffer A which are sequentially connected between the RS485 interface circuit A and the multiplexing switch, wherein the receiver A is used for receiving a synchronous clock and transmitting response data received by the RS485 interface circuit A to the receiving buffer A based on the synchronous clock, and the receiving buffer A transmits the response data to the multiplexing switch;
the data transmission B channel further comprises a receiver B and a receiving buffer B which are sequentially connected between the RS485 interface circuit B and the multiplexing switch, wherein the receiver B is used for receiving a synchronous clock and transmitting response data received by the RS485 interface circuit B to the receiving buffer B based on the synchronous clock, and the receiving buffer B transmits the response data to the multiplexing switch.
6. An interface for a multi-protocol encoder as defined in claim 5, wherein: the external connection encoder connected with the RS485 interface circuit A and the RS485 interface circuit B is an asynchronous communication encoder, a synchronous communication encoder or an incremental encoder, the RS485 interface circuit A and the RS485 interface circuit B are alternatively connected with one asynchronous communication encoder, or the RS485 interface circuit A and the RS485 interface circuit B are respectively connected with two asynchronous communication encoders, or the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same synchronous communication encoder, or the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same incremental encoder.
7. An interface for a multi-protocol encoder as defined in claim 6, wherein: when the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same synchronous communication encoder, the RS485 interface circuit A and the RS485 interface circuit B enter a transmission mode, a data transmission A channel is used for transmitting clock control data, and a data transmission B channel is used for transmitting control data; or the data transmission B channel is used for transmitting clock control data, and the data transmission A channel is used for transmitting control data.
8. An interface for a multi-protocol encoder as defined in claim 7, wherein: when the RS485 interface circuit A and the RS485 interface circuit B are connected with two ports of the same incremental encoder, the RS485 interface circuit A and the RS485 interface circuit B only enter a receiving mode.
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