CN117542930A - Preparation method of LED chip - Google Patents
Preparation method of LED chip Download PDFInfo
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- CN117542930A CN117542930A CN202311603263.7A CN202311603263A CN117542930A CN 117542930 A CN117542930 A CN 117542930A CN 202311603263 A CN202311603263 A CN 202311603263A CN 117542930 A CN117542930 A CN 117542930A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- 238000007788 roughening Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000003892 spreading Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 8
- 238000010586 diagram Methods 0.000 description 11
- 229910002601 GaN Inorganic materials 0.000 description 10
- 239000003292 glue Substances 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention relates to the technical field of chip preparation, in particular to a preparation method of an LED chip. The preparation method of the LED chip comprises the following steps: step one: depositing an epitaxial layer on a substrate; step two: depositing a current expansion layer; step three: etching to remove photoresist; step four: the chip preparation is completed after the Metal process-DBR process-Bonding process, and the loss of the light emission at the corner part is reduced and the reflection area is increased through a series of etching photoresist removal, so that the light emission is increased, and the brightness and the die Bonding yield of the chip are improved.
Description
Technical Field
The invention relates to the technical field of chip preparation, in particular to a preparation method of an LED chip.
Background
Currently, LED chips are classified into forward mounted chips, flip chips, and vertical chips. Flip chips are widely used for their brightness advantages. Compared with a forward chip, the flip chip has the advantages that the back surface of the flip chip emits light, the light emitting area is larger, the electrode is connected with the bonding pad through solder paste, and the heat dissipation is better. The publication number is: although the technical scheme of improving the brightness of the flip-chip LED chip and the preparation method thereof disclosed in CN106848005B is provided, the flip-chip LED chip is mainly used for searching a material capable of replacing ITO, and the problems of the brightness and the die bonding yield of the chip prepared from the ITO are not solved.
Disclosure of Invention
The invention aims to solve the technical problems that: overcomes the defects of the prior art and provides a preparation method of the LED chip.
The invention adopts the technical proposal for solving the technical problems that: the preparation method of the LED chip comprises the following steps:
step one: depositing an epitaxial layer on a substrate;
step two: depositing a current expansion layer;
step three: etching to remove photoresist;
step four: and (3) finishing chip preparation after the Metal process-DBR process-Bonding process.
The epitaxial layer in the first step comprises an N-GaN layer, an MQW layer and a P-GaN layer. In this embodiment, the substrate is a sapphire substrate, and an epitaxial layer is deposited on the sapphire substrate.
And in the second step, a transparent conductive Indium Tin Oxide (ITO) is deposited on the epitaxial layer by using a magnetron sputtering device, and the thickness of the ITO is about 600 angstroms and is used as a current expansion layer.
The third step comprises the following substeps:
3-1: positive photoresist is coated, exposed and developed. After development, part of the epitaxial layer is protected by photoresist, and part of the epitaxial layer is not protected.
3-2: removing photoresist after ITO wet etching;
3-3: coating positive photoresist, and exposing and developing; after development, a circular or polygonal pattern is formed, the pattern is not limited to one type, and the dimensions can be designed to different dimensions, and the main purpose of this step is to pattern the ITO.
3-4: removing photoresist after ITO wet etching, wherein the etching time is shorter than the etching time of 3 < -2 >;
3-5: performing MESA photoetching process, and then coating positive photoresist, exposing and developing; after development, part of the chip is protected by photoresist, and the other part is not protected;
3-6: performing an MESA etching process and a photoresist removing process;
3-7: ISO photolithography is performed followed by positive photoresist coating, exposure, development. After development, the chip is protected by photoresist, and only part of the chip is unprotected.
3-8: ISO dry etching and photoresist removal;
3-9: and (3) carrying out platform smoothing treatment, and then coating positive photoresist, exposing and developing. After development, only the folded corner part of the platform step and the folded corner part of the cutting channel are not protected, and the other parts are protected by photoresist;
3-10: performing ICP etching treatment and roughening treatment and photoresist removal.
And 3-2, adopting mixed solution of ferric trichloride and hydrochloric acid for wet etching, wherein the edge of the etched transparent conductive indium tin oxide layer is about 2-4 microns away from the edge of the photoresist, and then removing the photoresist.
The 3-4 is prepared from mixed solution of ferric trichloride and hydrochloric acid, the etching time of the step is shorter than that of 3-2, the specific time can be determined according to design, the ITO is incompletely etched after etching, only a part of ITO is etched, the photoresist is removed, an annealing process is performed, and the annealing process is performed for about 10 minutes in a nitrogen environment under 550 ℃.
And 3-6, etching by ICP until the N-GaN layer is exposed, and completely etching is not needed, wherein the step is used as an N electrode platform.
And 3-8, etching the epitaxial layer by adopting an ICP dry etching process until the substrate is exposed, and then performing a photoresist removing process.
And in the step 3-10, the ICP etching adopts low-power etching to smooth the folded corner part of the platform step and the folded corner part of the cutting channel. The step is mainly to reduce the loss of the light emission at the folded angle part, increase the reflection area, and the roughening treatment adopts KOH solution for treatment, so that the smooth platform step and the surface of the cutting channel form a microstructure, the surface area is further increased, and the light emission is increased.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a preparation method of an LED chip, which reduces the loss of light emission at the corner part and increases the reflection area through a series of etching photoresist removal, thereby increasing the light emission and the brightness and the die bonding yield of the chip.
Drawings
Fig. 1 is a schematic diagram of the structure of a substrate and an epitaxial layer according to the present invention.
FIG. 2 is a schematic diagram of the structure of the present invention 3-1.
FIG. 3 is a schematic view of the structure of the present invention 3-2.
FIG. 4 is a schematic diagram of the structure of the invention 3-3.
FIG. 5 is a schematic diagram of the structure of the invention 3-4.
FIG. 6 is a schematic diagram of the structure of the invention 3-5.
FIG. 7 is a schematic diagram of the structure of the invention 3-6.
FIG. 8 is a schematic diagram of the structure of the invention 3-7.
Fig. 9 is a schematic diagram of the structure of the present invention 3-8.
Fig. 10 is a schematic diagram of the structure of inventions 3-9.
Fig. 11 is a schematic diagram of the structure of inventions 3-10.
Fig. 12 is a schematic diagram of the final chip structure of the invention.
Reference numerals: 1. a P-GaN layer; 2. an MQW layer; 3. an N-GaN layer; 4. an ITO layer; 5. a photoresist; 6. a step; 7. cutting the channel; 8. a DBR layer; 9. a metal pad; 10. a current conducting electrode; 11. a substrate.
Detailed Description
Embodiments of the invention are further described below with reference to the accompanying drawings:
examples
As in fig. 1 to 12, comprising the steps of:
step one: depositing an epitaxial layer on the substrate 11; the epitaxial layer in the first step includes an N-GaN layer 3 (i.e., an N-type gallium nitride layer), an MQW layer 2 (i.e., a quantum well layer), and a P-GaN layer 1 (P-type gallium nitride layer). In this embodiment, the substrate is a sapphire substrate, and an epitaxial layer is deposited on the sapphire substrate, and the structure of the epitaxial layer is shown in fig. 1.
Step two: depositing a current expansion layer; in the second step, transparent conductive indium tin oxide is deposited on the epitaxial layer by utilizing a magnetron sputtering device to generate an ITO layer 4, wherein the ITO layer is about 600 angstroms thick and is used as a current expansion layer.
Step three: etching to remove photoresist;
the third step comprises the following substeps:
3-1: positive photoresist 5 is coated, exposed and developed. After development, part of the epitaxial layer is protected by photoresist 5 and part is unprotected, as shown in fig. 2. The photoresist coating is to coat the whole surface of the wafer, then ultraviolet exposure is carried out by using a mask, the pattern of the mask forms a shading and light transmitting part, and the photoresist of the exposed part is removed after development. In this embodiment, the thickness of the glue is about 2-3um, 9 points of the same wafer are tested after glue application, the thickness error between the points is not more than 0.3um, and the protected and unprotected areas are determined by the exposure, i.e. the pattern of the mask.
3-2: removing photoresist after ITO wet etching; the wet etching in 3-2 adopts mixed solution of ferric trichloride and hydrochloric acid, the edge of the etched transparent conductive indium tin oxide layer is about 2-4 microns away from the edge of the photoresist 5, and then the photoresist 5 is removed, as shown in figure 3.
3-3: coating positive photoresist 5, and exposing and developing; after development, a circular or polygonal pattern is formed, the pattern is not limited to one type, and the dimensions can be designed to different dimensions, and the main purpose of this step is to pattern the ITO layer, as shown in fig. 4 after development. In the step, the thickness of the glue is about 2-3um, 9 points of the same wafer are tested after glue spreading, and the thickness error between the points is not more than 0.3um.
3-4: photoresist is removed after ITO wet etching, and the etching time is shorter than 3-2 etching time; the mixed solution of ferric trichloride and hydrochloric acid is adopted in 3-4, the etching time of the step is shorter than that of 3-2, the specific time can be determined according to design, the ITO is incompletely etched after etching, only a part of the ITO is etched, then the photoresist 5 is removed, an annealing process is carried out, and the rapid thermal annealing at 550 ℃ and the nitrogen environment are adopted for annealing for about 10 minutes, as shown in figure 5.
3-5: performing MESA photoetching process, and then coating positive photoresist 5, exposing and developing; after development, part of the photoresist 5 is protected, and part of the photoresist is not protected, as shown in fig. 6, the thickness of the photoresist is about 2-3um, 9 points of the wafer are tested after the photoresist is coated, and the thickness error between the points is not more than 0.3um.
3-6: performing a MESA etching and photoresist removing process; and 3-6 is etched by ICP until the N-GaN layer 3 is exposed, and the step is used as an N electrode platform and is shown in fig. 7 after photoresist removal without completely etching.
3-7: an ISO photolithography process is performed followed by coating of positive photoresist 5, exposure and development. After development the chip is protected by the photoresist 5, only part of it is unprotected, as shown in fig. 8. The thickness of the glue coating is about 5.5-6um, 9 points of the same wafer are tested after the glue coating, and the thickness error between the points is not more than 0.5um.
3-8: ISO dry etching and photoresist removal; in 3-8, an ICP dry etching process is adopted to etch the epitaxial layer until the substrate 11 is exposed, and then a photoresist removing process is performed, and the photoresist is removed as shown in fig. 9.
3-9: the platform is rounded, and then positive photoresist 5 is coated, exposed and developed. Only the folded corner portions of the steps 6 and the folded corner portions of the dicing streets 7 are unprotected after development, and the other are protected by the photoresist 5, as shown in fig. 10. The thickness of the glue coating is about 5.5-6um, 9 points of the same wafer are tested after the glue coating, and the thickness error between the points is not more than 0.5um. The platform performs the MESA process (i.e., the step process) and the ISO process (the dicing street process).
3-10: performing ICP etching treatment and roughening treatment and photoresist removal. In the 3-10, the ICP etching adopts low power (source power 500W, radio frequency power 150W) etching to smooth the folded angle part of the step 6 and the cutting channel 7. In this step, the reflection area is increased mainly to reduce the loss of the light emitted from the corner, and the roughening treatment is performed by using KOH solution, so that the rounded step 6 and the surface of the scribe line 7 form a microstructure, the surface area is further increased, the light emitted is increased, and the photoresist is removed as shown in fig. 11.
Step four: and (3) finishing chip preparation after the Metal process-DBR process-Bonding process. The patterning of the ITO layer 4 increases light extraction, and at the same time, the patterning of the ITO layer 4 patterns the metal pad to increase the contact area with the solder paste, improve adhesion, improve the overall die bonding yield, increase the area of the step 6 and the scribe line 7, and micro-pattern, increase the reflective light area of the DBR layer 8 (i.e., the bragg reflector layer) of the chip, and improve the brightness of the chip, as shown in fig. 12. Exposure in this embodiment: the Nikon ultraviolet exposure machine or the Shanghai micro exposure machine is adopted, the wavelength is 365nm, and the exposure energy is different according to different processes; the development is carried out at room temperature, and high-temperature baking is carried out after the development, the temperature ranges from 100 ℃ to 120 ℃ and the time ranges from 60s to 90s, and the temperature and the time are different according to different processes.
Metal process (Metal electrode process): and (3) coating negative photoresist with the thickness of 3-5um, exposing and developing. After development, the photoresist remains in the exposed areas and the photoresist is washed away by the developer solution, contrary to the positive photoresist process. After development, ion cleaning is carried out, mainly for cleaning the residual adhesive film, and then water cleaning is carried out, so that the surface of the wafer is further cleaned. The metal is vacuum coated after cleaning, the metal is vapor deposited, cr, al, ti, pt, au and other metal are used, the total thickness is about 2.4um-3um, stripping is carried out after vapor deposition, a full-automatic photoresist stripping machine is adopted, high-pressure NMP (N-methyl pyrrolidone) is utilized to separate from a metal layer on photoresist, photoresist is removed, normal-temperature acetone is utilized to remove residual photoresist and NMP, pure water is utilized to clean a wafer, IPA is utilized to carry out dehydration, nitrogen gas drying is carried out, and partial metal is reserved as the current conducting electrode 10.
DBR process (bragg mirror process): the deposition material is a silicon dioxide and titanium oxide laminated structure by using a deposition machine, 39 layers or 41 layers are laminated by using a traditional process, wherein a laminated layer 57 layer is adopted, the thickness of the laminated layer is about 5.8um-6um, and compared with the traditional laminated layer, the laminated layer has wider wave band and is more beneficial to light reflection. And then coating positive photoresist, exposing and developing. After development, part of the DBR layer 8 is exposed to the surface, and the other part is protected by photoresist. The dry etching and photoresist removal process of the DBR layer 8 is performed after the photolithography. And forming a channel after etching, wherein the channel ensures that the subsequent metal electrode is connected with the welding metal, and removing the photoresist.
Bonding process (metal pad process) negative photoresist is coated, exposed and developed. The developed exposed portion includes the chip surface of the DBR channel. Ion cleaning and acid cleaning of the wafer are carried out, metal deposition and stripping are carried out, metal deposition is carried out by using metal lamination processes of chromium, aluminum, titanium, platinum, gold and the like, the total thickness is about 4.8um to 5.2um, part of metal and photoresist are stripped after stripping, and part of metal is remained to be used as a metal bonding pad 9 of a chip.
Claims (9)
1. The preparation method of the LED chip is characterized by comprising the following steps of:
step one: depositing an epitaxial layer on a substrate (11);
step two: depositing a current expansion layer;
step three: etching to remove photoresist;
step four: and (3) finishing chip preparation after the Metal process-DBR process-Bonding process.
2. The method of manufacturing an LED chip of claim 1, wherein said epitaxial layer in step one comprises an N-GaN layer (3), an MQW layer (2) and a P-GaN layer (1).
3. The method of manufacturing an LED chip of claim 2, wherein in the second step, a transparent conductive indium tin oxide is deposited on the epitaxial layer as a current spreading layer using a magnetron sputtering apparatus.
4. A method of manufacturing an LED chip according to claim 3, wherein the third step comprises the sub-steps of:
3-1: coating positive photoresist (5), exposing and developing;
3-2: removing photoresist after ITO wet etching;
3-3: coating positive photoresist (5), exposing and developing;
3-4: removing photoresist after ITO wet etching, wherein the etching time is shorter than the etching time of 3 < -2 >;
3-5: carrying out MESA photoetching process, and then coating positive photoresist (5), exposing and developing;
3-6: performing an MESA etching process and a photoresist removing process;
3-7: performing an ISO photoetching process, and then coating positive photoresist (5), exposing and developing;
3-8: ISO dry etching and photoresist removal;
3-9: smooth processing of the platform, and then coating positive photoresist (5), exposing and developing;
3-10: performing ICP etching treatment and roughening treatment and photoresist removal.
5. The method for manufacturing an LED chip according to claim 4, wherein the wet etching in 3-2 is performed by using a mixed solution of ferric trichloride and hydrochloric acid, the edge of the etched current spreading layer is 2-4 micrometers away from the edge of the photoresist (5), and the photoresist (5) is removed.
6. The method for manufacturing an LED chip according to claim 4, wherein the 3-4 is a mixed solution of ferric trichloride and hydrochloric acid, the photoresist (5) is removed after etching, and an annealing process is performed.
7. The method for manufacturing the LED chip according to claim 4, wherein the etching is performed by using an ICP etching process in the steps 3-6 until the N-GaN layer (3) is exposed.
8. The method of manufacturing an LED chip of claim 4, wherein the epitaxial layer is etched to expose the substrate by ICP dry etching in 3-8, followed by photoresist removal.
9. The method of manufacturing an LED chip of claim 4, wherein the step corner portions and the scribe line corner portions are rounded by etching 3-10 using an ICP etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311603263.7A CN117542930A (en) | 2023-11-28 | 2023-11-28 | Preparation method of LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311603263.7A CN117542930A (en) | 2023-11-28 | 2023-11-28 | Preparation method of LED chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117542930A true CN117542930A (en) | 2024-02-09 |
Family
ID=89795563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311603263.7A Withdrawn CN117542930A (en) | 2023-11-28 | 2023-11-28 | Preparation method of LED chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117542930A (en) |
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- 2023-11-28 CN CN202311603263.7A patent/CN117542930A/en not_active Withdrawn
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| PB01 | Publication | ||
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Application publication date: 20240209 |