CN112510135A - LED chip structure with inverted double-layer DBR and manufacturing method thereof - Google Patents

LED chip structure with inverted double-layer DBR and manufacturing method thereof Download PDF

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Publication number
CN112510135A
CN112510135A CN202011508892.8A CN202011508892A CN112510135A CN 112510135 A CN112510135 A CN 112510135A CN 202011508892 A CN202011508892 A CN 202011508892A CN 112510135 A CN112510135 A CN 112510135A
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layer
dbr
chip
chip structure
technology
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张秀敏
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Purui Wuxi R & D Co ltd
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Purui Wuxi R & D Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Abstract

The invention discloses an LED chip structure of an inverted double-layer DBR and a manufacturing method thereof, wherein the LED chip structure of the inverted double-layer DBR comprises: an LED chip epitaxial structure grows on the front surface of the chip substrate, and an ITO film is plated on the surface of the epitaxial structure; n, P metal conductive branches are manufactured on the chip structure; SiO is deposited on the front surface of the chip structure2Insulating layer of SiO2The surface of the insulating layer is plated with a first DBR reflecting layer, N, P metal conducting branch lines are exposed through an ICP etching technology, and N, P pad electrodes are manufactured at corresponding positions; a second DBR reflection layer is plated on the back of the chip structure; when the chip structure is not cut, a cutting channel is formed on the chip structure through an etching technology, and the chip is cut along the cutting channel. According to the invention, the DBR reflecting layer is divided into a plurality of small blocks by arranging the cutting channels on the DBR reflecting layer, so that the overall stress of the chip structure is reduced, and the chip structure is prevented from warping.

Description

LED chip structure with inverted double-layer DBR and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LED chip structure with a double-layer inverted DBR and a manufacturing method thereof.
Background
A Light Emitting Diode (LED) is a solid light emitting device that converts electric energy into light energy, in which GaN-based LED chips have been greatly developed and applied. The luminous efficiency of the light emitting diode has two main factors: internal and external quantum efficiencies of the device. The light extraction efficiency of the LED chip is reduced due to the presence of fresnel loss, total reflection loss, and material absorption loss. The light extraction efficiency refers to the proportion of photons emitted into the air to electron-hole pairs that generate photons in the active region of the chip through radiative recombination, which is mainly related to the geometry and material optical properties of the LED. In order to improve the light extraction efficiency, the following technical solutions are generally adopted: growing a Distributed Bragg Reflector (DBR) structure, surface roughening technology, photonic crystal technology and the like. The reflectivity of the distributed Bragg reflection layer can reach more than 99 percent, the distributed Bragg reflection layer does not have the absorption problem of a metal reflection layer, and the position of an energy gap can be adjusted by changing the refractive index or the thickness of a material. The double-sided DBR structure adopted in the prior art has the problems of overlarge stress, high cutting difficulty and the like, and the manufacturing method of the double-sided DBR structure also needs to be further improved and perfected.
Disclosure of Invention
The LED chip structure comprises a substrate, a plurality of LED chips, a plurality of DBR reflecting layers, a plurality of small blocks, a plurality of cutting channels, a plurality of small blocks, a plurality of cutting lines and a plurality of cutting lines.
The technical scheme adopted by the invention is as follows:
an LED chip structure of a flip double-layer DBR is characterized in that an LED chip epitaxial structure grows on the front surface of a chip substrate, an ITO film is plated on the surface of the epitaxial structure, and an N-GaN layer of an exposure area is etched through an ICP etching technology to form an N-GaN step; n, P metal conductive branches are manufactured on the chip structure; SiO is deposited on the front surface of the chip structure2Insulating layer of SiO2The surface of the insulating layer is plated with a first DBR reflecting layer, N, P metal conducting branch lines are exposed through an ICP etching technology, and N, P pad electrodes are manufactured at the corresponding positions of N, P metal conducting branch lines; a second DBR reflection layer is plated on the back of the chip structure; when the chip structure is not cut, the chip structure is cut,and forming a cutting channel on the chip structure by an etching technology, wherein the cutting channel is positioned on the front side or the back side or both sides of the chip structure, and the chip is cut along the cutting channel.
As a further improvement of the above technical solution:
SiO deposition on the surface of a chip structure by utilizing PECVD technology2An insulating layer formed on SiO by oxide coating2The insulating layer is coated with a first DBR reflecting layer, then a mask pattern is manufactured by utilizing a positive photoetching mask technology, and N, P metal conducting branch lines are exposed by utilizing an ICP etching technology.
The pad electrode pattern was made using a negative photolithographic masking technique and N, P pad electrodes were made by an electron beam evaporation technique.
And plating a second DBR reflecting layer on the back surface of the chip structure by using an oxide coating technology.
And manufacturing a mask pattern by using a positive photoetching mask technology, exposing the cutting path, and etching the DBR at the cutting path by using an ICP (inductively coupled plasma) etching technology to form the cutting path.
The invention also adopts the following technical scheme:
a manufacturing method of an LED chip structure of a flip double-layer DBR comprises the following steps:
step S1, providing a chip substrate, and growing an LED chip epitaxial structure on the front surface of the chip substrate;
step S2, plating an ITO film on the surface of the chip epitaxial structure;
step S3: etching the N-GaN layer of the exposed region by an ICP (inductively coupled plasma) etching technology to form an N-GaN step;
step S4, manufacturing N, P metal conductive branch lines on the chip structure;
step S5, depositing SiO on the front surface of the chip structure2Insulating layer of SiO2Plating a first DBR reflecting layer on the surface of the insulating layer, and exposing N, P metal conducting branch lines by an ICP etching technology;
step S6, manufacturing N, P pad electrodes by an electron beam evaporation technology;
step S7, plating a second DBR reflection layer on the back of the chip structure;
step S8, forming a cutting channel on the chip structure by an etching technology, wherein the cutting channel is positioned on the front side or the back side or both sides of the chip structure;
and step S9, cutting the device on the chip substrate along the cutting path by using a grinding wheel knife, and separating the chip by using a splitting technology.
As a further improvement of the above technical solution:
step S5 further includes: SiO deposition on the surface of a chip structure by utilizing PECVD technology2An insulating layer formed on SiO by oxide coating2The insulating layer is coated with a first DBR reflecting layer, then a mask pattern is manufactured by utilizing a positive photoetching mask technology, and N, P metal conducting branch lines are exposed by utilizing an ICP etching technology.
Step S7 further includes: and plating a second DBR reflecting layer on the back surface of the chip structure by using an oxide coating technology.
The oxide coating technology adopts an electron beam evaporation technology.
Step S8 further includes: and manufacturing a mask pattern by using a positive photoetching mask technology, exposing the cutting path, and etching the DBR at the cutting path by using an ICP (inductively coupled plasma) etching technology to form the cutting path.
The invention has the following beneficial effects:
according to the invention, the DBR reflecting layer is divided into a plurality of small blocks by arranging the cutting channels on the DBR reflecting layer, so that the overall stress of the chip structure is reduced, and the chip structure is prevented from warping. The chip structure utilizes positive photoetching mask technology to make mask patterns before cutting, the cutting channel is exposed, the DBR at the cutting channel is etched by ICP etching technology to form the cutting channel, the cutting channel is positioned on the front side or the back side or both sides of the chip structure, the chip is cut along the cutting channel, the cutting channel region does not contain the DBR, the cutting difficulty of the chip is reduced, and therefore the yield of chip manufacturing is improved. The invention adopts the deposition of SiO on the front surface of a chip structure2Insulating layer of SiO2The insulating layer surface plates first DBR reflection stratum, exposes N, P metal conduction branch line through ICP etching technique, makes N, P pad electrode through electron beam evaporation technique, both is convenient for the processing preparation of first DBR reflection stratum, has realized N, P pad electrode againThe lead-out structure of (1). According to the invention, the side light-emitting is enhanced through the double-layer DBR reflecting layers on the front surface and the back surface of the chip structure, the Optical Distance (OD) is reduced, the light extraction efficiency can be obviously improved, and the manufacturing process is simple and convenient.
Drawings
Fig. 1 is a schematic structural diagram of an LED chip structure of a flip-chip double-layer DBR according to the present invention.
In the figure: 1. a chip substrate; 2. an ITO film; 3. a metal conductive branch line; 4. SiO 22An insulating layer; 5. a first DBR reflective layer; 6. a pad electrode; 7. a second DBR reflective layer.
Detailed Description
The following describes embodiments of the present invention with reference to the drawings.
As shown in fig. 1, the LED chip structure of the flip-chip double-layer DBR of the present invention grows an LED chip epitaxial structure on a chip substrate 1, where the chip substrate 1 includes but is not limited to sapphire, silicon wafer, silicon carbide wafer or metal. For example, an LED chip epitaxial structure is grown on the chip substrate 1 by using an MOCVD (Metal-organic Chemical Vapor Deposition) apparatus, the LED chip epitaxial structure is a multilayer structure, and may be, for example, a buffer layer, a U-GaN layer, an N-GaN layer, a multi-quantum well layer and a P-GaN layer which are sequentially grown, or an N-GaN layer, a multi-quantum well layer and a P-GaN layer which are sequentially grown according to actual needs, and the LED chip epitaxial structure covers the entire surface of the chip substrate 1. MOCVD is a new vapor phase epitaxial growth technology developed on the basis of vapor phase epitaxial growth (VPE).
And an ITO film 2 is plated on the P-GaN layer, and the ITO film 2 and the P-GaN layer form good ohmic contact. Specifically, an ITO film 2 (ITO, Indium Tin Oxide) is plated on the chip structure by using a magnetron sputtering technique, and the ITO film 2 and the P-GaN layer form a good ohmic contact by using a Rapid Thermal Annealing (RTA) of an Annealing furnace.
And etching the N-GaN layer in the exposed region by an ICP (Inductively Coupled Plasma) etching technology to form an N-GaN step. On the basis, metal coating is utilizedThe technique makes N, P metal conducting branches 3. SiO deposition on the surface of a chip structure by utilizing PECVD technology2An insulating layer 4 formed on SiO by an oxide coating technique such as electron beam evaporation2The insulating layer 4 is coated with the first DBR reflective layer 5, and then a mask pattern is formed by using a positive photolithography mask technique, and the N, P metal conductive branches 3 are exposed by using an ICP etching technique. The pad electrode pattern was made using a negative photolithographic masking technique and the pad electrode 6 was made N, P by an electron beam evaporation technique.
The second DBR reflective layer 7 is coated on the back of the chip structure using an oxide coating technique such as electron beam evaporation. And manufacturing a mask pattern by using a positive photoetching mask technology, exposing a cutting path which is positioned on the front side or the back side or both sides of the chip structure, and etching the DBR at the cutting path by using an ICP (inductively coupled plasma) etching technology.
Referring to fig. 1, the invention also provides a method for manufacturing an LED chip structure of a flip-chip double-layer DBR, comprising the following steps:
step S1: providing a chip substrate 1 comprising but not limited to sapphire, silicon wafer, silicon carbide wafer or metal, growing an LED chip epitaxial structure on the chip substrate 1 by using MOCVD equipment, wherein the LED chip epitaxial structure is a multilayer structure, and for example, an N-GaN layer, a multi-quantum well layer and a P-GaN layer can be grown in sequence according to actual needs, and also can be a buffer layer, a U-GaN layer, an N-GaN layer, a multi-quantum well layer and a P-GaN layer can be grown in sequence, and the LED chip epitaxial structure covers the whole surface of the chip substrate 1.
Step S2: the ITO film 2 is plated on the surface of the chip structure by utilizing a magnetron sputtering technology, and the ITO film 2 and the P-GaN layer form good ohmic contact by utilizing high-temperature rapid annealing of an annealing furnace.
Step S3: and manufacturing a mask pattern by using a positive photoetching mask technology, and etching the N-GaN layer in the exposure region by using an ICP (inductively coupled plasma) etching technology to form an N-GaN step.
Step S4: n, P the metal conductive branch line 3 is made by metal plating technology.
Step S5: SiO deposition on the surface of a chip structure by utilizing PECVD technology2Insulating layer 4, by oxide coating techniques such asElectron beam evaporation technique on SiO2The insulating layer 4 is coated with the first DBR reflective layer 5, and then a mask pattern is formed by using a positive photolithography mask technique, and the N, P metal conductive branches 3 are exposed by using an ICP etching technique.
Step S6: the pad electrode pattern was made using a negative photolithographic masking technique and the pad electrode 6 was made N, P by an electron beam evaporation technique.
Step S7: and thinning the chip structure by using a grinding wheel.
Step S8: the second DBR reflective layer 7 is coated on the back of the chip structure using an oxide coating technique such as electron beam evaporation.
Step S9: and manufacturing a mask pattern by using a positive photoetching mask technology, exposing a cutting path which is positioned on the front side or the back side or both sides of the chip structure, and etching the DBR at the cutting path by using an ICP (inductively coupled plasma) etching technology.
Step S10: the devices on the chip substrate 1 are cut along the dicing streets by a grinding wheel cutter, and the chips are separated by a chipping technique. And testing and classifying the photoelectric parameters of the cut chips through a probe station and sorting machine equipment to form finished chips.
In the present invention, the positive photoresist mask technology is a technology for making a mask pattern by using a positive photoresist, and a photoresist mainly subjected to a degradation reaction under irradiation of an energy beam (a light beam, an electron beam, an ion beam, or the like) is referred to as a positive photoresist, which is referred to as a positive photoresist for short. The negative photoresist mask technology is a technology for making a mask pattern by using a negative photoresist, and the photoresist mainly subjected to a cross-linking reaction under the irradiation of an energy beam (a light beam, an electron beam, an ion beam and the like) is called a negative photoresist, which is called a negative photoresist for short.
The foregoing description is illustrative of the present invention and is not to be construed as limiting thereof, as the invention may be modified in any manner without departing from the spirit thereof.

Claims (10)

1. The utility model provides a LED chip structure of double-deck DBR of flip-chip which characterized in that: an LED chip epitaxial structure grows on the front surface of a chip substrate (1), and the surface of the epitaxial structure is platedAn ITO film (2) is arranged, and an N-GaN layer in the exposed region is etched out through an ICP etching technology to form an N-GaN step; n, P metal conductive branches (3) are manufactured on the chip structure; SiO is deposited on the front surface of the chip structure2An insulating layer (4) on SiO2The surface of the insulating layer (4) is plated with a first DBR (distributed Bragg reflector) layer (5), N, P metal conducting branch lines (3) are exposed through an ICP (inductively coupled plasma) etching technology, and N, P pad electrodes (6) are manufactured at corresponding positions of N, P metal conducting branch lines (3); a second DBR reflecting layer (7) is plated on the back of the chip structure; when the chip structure is not cut, a cutting channel is formed on the chip structure through an etching technology, the cutting channel is located on the front side or the back side or both sides of the chip structure, and the chip is cut along the cutting channel.
2. The LED chip structure of the flip-chip double-layer DBR of claim 1, wherein: SiO deposition on the surface of a chip structure by utilizing PECVD technology2An insulating layer (4) formed on the SiO layer by an oxide coating technique2The surface of the insulating layer (4) is plated with a first DBR reflecting layer (5), then a mask pattern is manufactured by utilizing a positive photoetching mask technology, and N, P metal conducting branch lines (3) are exposed by utilizing an ICP etching technology.
3. The LED chip structure of the flip-chip double-layer DBR of claim 1, wherein: the pad electrode pattern was made using a negative photolithographic masking technique and N, P pad electrodes (6) were made by an electron beam evaporation technique.
4. The LED chip structure of the flip-chip double-layer DBR of claim 1, wherein: a second DBR reflective layer (7) is coated on the back of the chip structure using an oxide coating technique.
5. The LED chip structure of the flip-chip double-layer DBR of claim 1, wherein: and manufacturing a mask pattern by using a positive photoetching mask technology, exposing the cutting path, and etching the DBR at the cutting path by using an ICP (inductively coupled plasma) etching technology to form the cutting path.
6. A manufacturing method of an LED chip structure of an inverted double-layer DBR is characterized by comprising the following steps: the method comprises the following steps:
step S1, providing a chip substrate (1), and growing an LED chip epitaxial structure on the front surface of the chip substrate (1);
step S2, plating an ITO film (2) on the surface of the chip epitaxial structure;
step S3: etching the N-GaN layer of the exposed region by an ICP (inductively coupled plasma) etching technology to form an N-GaN step;
step S4, manufacturing N, P metal conductive branch lines (3) on the chip structure;
step S5, depositing SiO on the front surface of the chip structure2An insulating layer (4) on SiO2Plating a first DBR (distributed Bragg reflector) layer (5) on the surface of the insulating layer (4), and exposing N, P metal conducting branch lines (3) by an ICP (inductively coupled plasma) etching technology;
step S6, manufacturing N, P pad electrodes (6) by an electron beam evaporation technology;
step S7, plating a second DBR reflection layer (7) on the back of the chip structure;
step S8, forming a cutting channel on the chip structure by an etching technology, wherein the cutting channel is positioned on the front side or the back side or both sides of the chip structure;
and step S9, cutting the device on the chip substrate (1) along the cutting path by using a grinding wheel knife, and separating the chip by using a splitting technology.
7. The method of fabricating the LED chip structure of the flip-chip double-layer DBR of claim 6, wherein: step S5 further includes: SiO deposition on the surface of a chip structure by utilizing PECVD technology2An insulating layer (4) formed on the SiO layer by an oxide coating technique2The surface of the insulating layer (4) is plated with a first DBR reflecting layer (5), then a mask pattern is manufactured by utilizing a positive photoetching mask technology, and N, P metal conducting branch lines (3) are exposed by utilizing an ICP etching technology.
8. The method of fabricating the LED chip structure of the flip-chip double-layer DBR of claim 6, wherein: step S7 further includes: a second DBR reflective layer (7) is coated on the back of the chip structure using an oxide coating technique.
9. The method for manufacturing the LED chip structure of the flip-chip double-layer DBR according to claim 7 or 8, wherein: the oxide coating technology adopts an electron beam evaporation technology.
10. The method of fabricating the LED chip structure of the flip-chip double-layer DBR of claim 6, wherein: step S8 further includes: and manufacturing a mask pattern by using a positive photoetching mask technology, exposing the cutting path, and etching the DBR at the cutting path by using an ICP (inductively coupled plasma) etching technology to form the cutting path.
CN202011508892.8A 2020-12-18 2020-12-18 LED chip structure with inverted double-layer DBR and manufacturing method thereof Pending CN112510135A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115863498A (en) * 2023-02-21 2023-03-28 江西兆驰半导体有限公司 Preparation method of normally-installed LED chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115863498A (en) * 2023-02-21 2023-03-28 江西兆驰半导体有限公司 Preparation method of normally-installed LED chip
CN115863498B (en) * 2023-02-21 2024-03-12 江西兆驰半导体有限公司 Preparation method of forward-mounted LED chip

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