CN117542729A - Wafer thinning method and wafer - Google Patents

Wafer thinning method and wafer Download PDF

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Publication number
CN117542729A
CN117542729A CN202311386980.9A CN202311386980A CN117542729A CN 117542729 A CN117542729 A CN 117542729A CN 202311386980 A CN202311386980 A CN 202311386980A CN 117542729 A CN117542729 A CN 117542729A
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China
Prior art keywords
wafer
edge
thinned
thinning
bonding
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CN202311386980.9A
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Inventor
杜文娟
李石光
孙文超
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Shanghai Dingtai Craftsman Core Technology Co ltd
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Shanghai Dingtai Craftsman Core Technology Co ltd
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Priority to CN202311386980.9A priority Critical patent/CN117542729A/en
Publication of CN117542729A publication Critical patent/CN117542729A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The application discloses a wafer thinning method and a wafer, and belongs to the field of semiconductor manufacturing, wherein the method comprises the following steps: trimming the front edge of the wafer to be thinned to enable the front edge of the wafer to form a step perpendicular to the back surface of the wafer; bonding the front surface of the trimmed wafer with a supporting plate; thinning the back surface of the bonded wafer to enable the wafer to reach the target thickness; and de-bonding the thinned wafer to obtain the wafer with the target thickness. According to the method, the edge trimming process is added before bonding, the edge of the wafer is trimmed, the vertical steps are formed at the edge, the traditional circular arc edge is replaced, the utilization rate of the effective area of the wafer is improved, meanwhile, the breakage rate of the ultrathin wafer in the back process is reduced, and then the 12-inch ultrathin wafer product with high yield is obtained efficiently.

Description

Wafer thinning method and wafer
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a wafer thinning method and a wafer.
Background
In order to solve the problem of taking and placing an ultrathin wafer, two methods, namely a temporary bonding process and a Taiko (Taiko) process are generally adopted in the process of thinning the wafer. However, a temporary bonding process is employed: in the manufacturing process of the wafer, the edge becomes smooth through the polishing process, and after the wafer and glass are temporarily bonded, the problem of sharp edge easily occurs during grinding, and the edge of the wafer is easily damaged or even broken, so that the yield and the productivity of the wafer are affected. The Taiko process is applied in the temporary bonding process: the Taiko ring is cut off before the wafer is shipped, and a part of the effective area of the wafer is wasted; meanwhile, the circular cutting process has certain risks of edge damage, micro cracks, particle pollution and the like, and further influences the yield and the yield of wafer shipment. Therefore, how to improve the yield and productivity of the wafer is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The purpose of the application is to provide a wafer thinning method and a wafer, so that the utilization rate of an effective area of the wafer is improved, meanwhile, the damage rate of an ultrathin wafer in a back process is reduced, and a 12-inch ultrathin wafer product with high yield is obtained efficiently.
In order to achieve the above object, the present application provides a wafer thinning method, including:
trimming the front edge of the wafer to be thinned to enable the front edge of the wafer to form a step perpendicular to the back surface of the wafer;
bonding the front surface of the trimmed wafer with a supporting plate;
thinning the back surface of the bonded wafer to enable the wafer to reach the target thickness;
and de-bonding the thinned wafer to obtain the wafer with the target thickness.
Optionally, before the debonding the thinned wafer, the method further includes:
the wafer is stuck to the inside of the annular wafer frame in the circumferential direction of the annular wafer frame.
Optionally, before the debonding the thinned wafer, the method further includes:
and etching and/or metallizing the back surface of the bonded wafer.
Optionally, the bonding the front surface of the trimmed wafer to a support plate includes:
spin coating Jie Jiaoceng on the front side of the trimmed wafer;
spin-coating an adhesion layer on the surface of the supporting plate, which is close to the wafer;
placing the front surface of the wafer with the photoresist layer on the surface of the supporting plate with the adhesion layer;
removing the photoresist layer and the adhesion layer overflowed from the edge of the wafer;
and bonding the front surface of the wafer with the supporting plate by curing the photoresist layer and the adhesive layer at high temperature.
Optionally, the debonding the thinned wafer includes:
and de-bonding the thinned wafer through ultraviolet irradiation.
Optionally, the trimming the front edge of the wafer to be thinned includes:
and trimming the front edge of the wafer to be thinned through mechanical cutting.
Optionally, the trim has a depth greater than the target thickness.
Optionally, the trimmed depth is 100 μm to 200 μm greater than the target thickness and includes values at both ends.
Optionally, the width of the trimming is 1.5 mm-3 mm, and includes values of both ends.
To achieve the above object, the present application further provides a wafer, including: a wafer prepared by the wafer thinning method of any of the above.
The wafer thinning method provided by the application comprises the following steps: trimming the front edge of the wafer to be thinned to enable the front edge of the wafer to form a step perpendicular to the back surface of the wafer; bonding the front surface of the trimmed wafer with a supporting plate; thinning the back surface of the bonded wafer to enable the wafer to reach the target thickness; and de-bonding the thinned wafer to obtain the wafer with the target thickness.
Obviously, the edge trimming process is added before bonding, the edge of the wafer is trimmed, a vertical step is formed at the edge, the traditional arc-shaped edge is replaced, the problem of sharp edge can be avoided, the wafer is ensured to have higher structural integrity in subsequent processing, and the breaking rate is reduced; the wafer is conveyed and operated together with the support plate in the whole back process until all the back processes are completed, so that enough mechanical support strength can be provided for the ultrathin wafer; an edge trimming process is applied to the temporary bonding process, so that the effective area of the wafer is improved; the method does not need to carry out ring cutting, does not have the risk existing in the ring cutting process, and is beneficial to improving the yield and the yield of chips. The application also provides a wafer, and compared with the wafer prepared by the traditional wafer thinning method, the wafer has the advantages that the utilization rate of the effective area is higher, the breakage rate is lower, and the yield is higher.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic view of a wafer structure in a conventional thinning process;
FIG. 2 is a schematic diagram showing the occurrence of chipping in the region of the wafer edge a during conventional thinning;
FIG. 3 is a flowchart of a wafer thinning method according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of another method for thinning a wafer according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart of a wafer thinning method according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a trimmed wafer structure according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a bonded wafer structure according to an embodiment of the present application.
The reference numerals are explained as follows:
1-wafer; 2-glass; 3-a glue-releasing layer and an adhesive layer.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Ultra-thin chips are becoming the dominant development in 12-inch wafer fabrication based on TSV (Through Silicon Via) interconnects and Three-dimensional stacked 3D (Three-dimensional) integrated fabrication requirements. At present, the thickness of the thinned wafer can be less than 100 mu m, but the mechanical strength of the ultrathin device wafer is reduced, the ultrathin device wafer is easy to warp and undulate, the device performance is easy to be reduced, the uniformity of products is easy to be poor, the fragmentation rate in the production process is increased, and the defects are particularly obvious for a 12-inch wafer.
In order to solve the problem of picking and placing ultrathin wafers, temporary bonding and debonding processes are generally adopted in the industry in the process of thinning the wafers. The temporary bonding and unbinding process is to temporarily bond the front surface of the wafer to thicker glass through an adhesive layer to provide enough supporting strength for the wafer and expose the back surface of the wafer so as to finish the back surface processes of thinning and the like, and then tear off the glass. However, as shown in fig. 1, only the temporary bonding process is adopted to bond the wafer 1 and the glass 2, since the edge of the wafer 1 is smooth, after the temporary bonding is performed on the common wafer 1, during the back grinding process, the edge of the wafer 1 will have a sharp edge, the grinding is continued, the problem of edge chipping is easy to occur (as shown in fig. 2), and the grinding is continued to cause crack propagation with a risk of chipping, thereby affecting the yield and productivity of the wafer.
Currently, domestic 12-inch wafer fabrication mainly adopts a method of applying the Taiko process to a temporary bonding process. The Taiko process is a technique in which, when a wafer is ground, only the inside of the wafer is thinned by grinding while leaving the peripheral edge portion (about 3 mm) of the wafer. The Taiko ring is cut off before the wafer is shipped, the width of the cut off is usually more than 4mm, and a part of the effective area of the wafer is wasted; meanwhile, the circular cutting process has certain risks of edge damage, micro cracks, particle pollution and the like, and further influences the yield and the yield of wafer shipment.
Therefore, the wafer edge is trimmed by adding an edge trimming process before bonding, a vertical step is formed at the edge to replace the traditional circular arc edge, so that the utilization rate of an effective area of the wafer is improved, the breakage rate of the ultrathin wafer in a back process is reduced, and a 12-inch ultrathin wafer product with high yield is obtained efficiently.
Referring to fig. 1, fig. 1 is a flowchart of a wafer thinning method according to an embodiment of the present application, where the method may include:
s101: and trimming the front edge of the wafer to be thinned to form a step perpendicular to the back surface of the wafer.
The embodiment is not limited to a specific manner of performing the trimming, as long as it is ensured that the front edge of the wafer can be formed to be a step perpendicular to the back surface of the wafer, and for example, the front edge of the wafer to be thinned may be trimmed by mechanical dicing.
It should be noted that, by reserving a sufficient thickness, on the premise of ensuring that the wafer can be polished to an effective thickness, it is also ensured that polishing damage (edge may be broken) will not cause the effective thickness and area of the wafer. Thus, the depth of modification in this embodiment may be greater than the target thickness. Further, the present embodiment is not limited to a specific value of the trimming depth, for example, the trimming depth may be 100 μm to 200 μm larger than the target thickness and include values of both ends.
The present embodiment is not limited to a specific value of the trimming width, and a specific value of the trimming width may be determined according to actual conditions, for example, the trimming width may be 1.5mm to 3mm, and include values of both ends.
S102: and bonding the front surface of the trimmed wafer with the supporting plate.
The embodiment is not limited to a specific manner of bonding, as long as the wafer can be temporarily fixed to the support plate, and for example, the wafer after trimming may be spin-coated Jie Jiaoceng on the front surface; spin-coating an adhesion layer on the surface of the support plate close to the wafer; placing the front surface of the wafer with the photoresist layer on the surface of the supporting plate with the adhesion layer; removing the photoresist layer and the adhesion layer overflowed from the edge of the wafer; and bonding the front surface of the wafer with the supporting plate through the high-temperature curing photoresist layer and the adhesive layer.
Furthermore, in this embodiment, after the front surface of the wafer is bonded to the support plate by the high-temperature curing glue solution layer and the adhesion layer, the glue solution layer and the adhesion layer overflowing from the edge of the wafer can be removed.
The present embodiment is not limited to a specific kind of support plate, as long as it is ensured that the support can be provided for the wafer, for example, the support plate may be glass.
S103: and thinning the back surface of the bonded wafer to enable the wafer to reach the target thickness.
In this embodiment, the thinning process is performed by a grinding process.
S104: and de-bonding the thinned wafer to obtain the wafer with the target thickness.
The embodiment is not limited to the specific manner of performing the deblocking, and the corresponding specific manner of deblocking may be determined according to the specific manner of bonding, for example, when front spin coating Jie Jiaoceng on the trimmed wafer is used; spin-coating an adhesion layer on the surface of the support plate close to the wafer; placing the front surface of the wafer with the photoresist layer on the surface of the supporting plate with the adhesion layer; removing the photoresist layer and the adhesion layer overflowed from the edge of the wafer; when the front surface of the wafer is bonded with the supporting plate through the high-temperature curing photoresist layer and the adhesion layer, the thinned wafer can be unbonded through ultraviolet irradiation.
Further, in this embodiment, before the thinned wafer is de-bonded, the wafer may be further adhered to the inside of the annular wafer frame along the circumferential direction of the annular wafer frame. Before the thinned wafer is de-bonded, the vacuum film is added, so that the wafer can be protected by the annular wafer frame, and the wafer can be safely delivered.
It should be noted that, bonding the wafer to the support plate is convenient for polishing the wafer, and other backside processes such as etching and metallization are also convenient. Therefore, in this embodiment, before the thinned wafer is de-bonded, etching and/or metallization may be performed on the back surface of the bonded wafer.
Further, after the thinned wafer is de-bonded in this embodiment, the support plate and the wafer after de-bonding may be cleaned, so as to avoid affecting the subsequent use of the support plate and the performance of the wafer.
Based on the embodiment, an edge trimming process is added before bonding, the edge of the wafer is trimmed, a vertical step is formed at the edge, the traditional arc-shaped edge is replaced, the problem of sharp edge can be avoided, the wafer is ensured to have higher structural integrity in subsequent processing, and the breaking rate is reduced; the wafer is conveyed and operated together with the support plate in the whole back process until all the back processes are completed, so that enough mechanical support strength can be provided for the ultrathin wafer; an edge trimming process is applied to the temporary bonding process, so that the effective area of the wafer is improved; the method does not need to carry out ring cutting, does not have the risk existing in the ring cutting process, and is beneficial to improving the yield and the yield of chips.
Referring to fig. 2, fig. 2 is a flowchart of another wafer thinning method according to an embodiment of the present application, where the method may include:
s201: trimming the front edge of the wafer to be thinned to form a step perpendicular to the back surface of the wafer; the finishing depth is greater than the target thickness;
s202: spin-coating Jie Jiaoceng on the front side of the trimmed wafer; spin-coating an adhesion layer on the surface of the support plate close to the wafer; placing the front surface of the wafer with the photoresist layer on the surface of the supporting plate with the adhesion layer; removing the photoresist layer and the adhesion layer overflowed from the edge of the wafer; bonding the front surface of the wafer with the supporting plate through the high-temperature curing photoresist layer and the adhesive layer;
s203: thinning the back surface of the bonded wafer to enable the wafer to reach the target thickness;
s204: adhering the wafer to the inside of the annular wafer frame along the circumferential direction of the annular wafer frame;
s205: and (5) de-bonding the thinned wafer through ultraviolet irradiation to obtain the wafer with the target thickness.
Based on the embodiment, an edge trimming process is added before bonding, the edge of the wafer is trimmed, a vertical step is formed at the edge, the traditional arc-shaped edge is replaced, the problem of sharp edge can be avoided, the wafer is ensured to have higher structural integrity in subsequent processing, and the breaking rate is reduced; the wafer is conveyed and operated together with the support plate in the whole back process until all the back processes are completed, so that enough mechanical support strength can be provided for the ultrathin wafer; an edge trimming process is applied to the temporary bonding process, so that the effective area of the wafer is improved; the method does not need to carry out ring cutting, does not have the risk existing in the ring cutting process, and is beneficial to improving the yield and the yield of chips. In addition, by reserving enough thickness, on the premise of ensuring that the wafer can be ground to an effective thickness, grinding damage (the edge possibly breaks) can be ensured not to cause the effective thickness and the area of the wafer; before the thinned wafer is subjected to de-bonding, a vacuum film pasting step is added, and the wafer can be protected through the annular wafer frame, so that the wafer can be safely delivered.
The embodiment of the application also provides a wafer, which comprises: a wafer prepared by the wafer thinning method of any of the above.
Based on the embodiment of the wafer thinning method, as the edge trimming process is added before bonding, the edge of the wafer is trimmed, a vertical step is formed at the edge, the traditional circular arc edge is replaced, the problem of sharp edge can be avoided, the wafer is ensured to have higher structural integrity in subsequent processing, and the breaking rate is reduced; the wafer is conveyed and operated together with the support plate in the whole back process until all the back processes are completed, so that enough mechanical support strength can be provided for the ultrathin wafer; an edge trimming process is applied to the temporary bonding process, so that the effective area of the wafer is improved; the wafer prepared by the wafer thinning method has the advantages that the wafer is not required to be subjected to ring cutting, the risk existing in the ring cutting process does not exist, the yield and the yield of chips are improved, and compared with the wafer prepared by the traditional wafer thinning method, the wafer prepared by the wafer thinning method is higher in utilization rate of an effective area, lower in breakage rate and higher in yield.
Referring to fig. 5, fig. 6, and fig. 7, fig. 5 is a schematic flow chart of a wafer thinning method according to an embodiment of the present application, fig. 6 is a schematic diagram of a trimmed wafer structure according to an embodiment of the present application, and fig. 7 is a schematic diagram of a bonded wafer structure according to an embodiment of the present application. The glass used for the support plate in this embodiment is specifically as follows:
1. edge trimming is carried out on the wafer 1 through mechanical cutting; cutting width L:1.5 mm-3 mm; depth of cut H: wafer 1 final thickness+ (100 μm-200 μm); the trimmed wafer 1 is shown in fig. 6;
2. spin-coating a photoresist layer and an adhesive layer 3 on the glass 2 and the wafer 1 respectively, then curing at high temperature, removing residual photoresist overflowed from the edge, and temporarily bonding the trimmed wafer 1 and the glass 2; the bonded wafer 1 is shown in fig. 7;
3. grinding and thinning the back surface of the bonded wafer 1 to enable the wafer 1 to reach the target thickness; and performing back surface processes such as etching, metallization and the like;
4. vacuum film pasting is carried out: adhering the wafer 1 to the inside of the annular wafer frame along the circumferential direction of the annular wafer frame;
5. the thinned wafer 1 is de-bonded through ultraviolet irradiation;
6. and cleaning the unbonded glass 2 and the wafer 1 to finish the shipment of the wafer 1.
The principles and embodiments of the present application are described herein by applying specific examples, and the examples are in progressive relationship, and each example mainly illustrates differences from other examples, where the same similar parts of the examples are mutually referred to. The above description of embodiments is only for aiding in the understanding of the method of the present application and its core ideas. It will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the principles of the application, which are intended to be covered by the appended claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Claims (10)

1. A method of thinning a wafer, comprising:
trimming the front edge of the wafer to be thinned to enable the front edge of the wafer to form a step perpendicular to the back surface of the wafer;
bonding the front surface of the trimmed wafer with a supporting plate;
thinning the back surface of the bonded wafer to enable the wafer to reach the target thickness;
and de-bonding the thinned wafer to obtain the wafer with the target thickness.
2. The method for thinning a wafer according to claim 1, wherein before the step of debonding the thinned wafer, the method further comprises:
the wafer is stuck to the inside of the annular wafer frame in the circumferential direction of the annular wafer frame.
3. The method for thinning a wafer according to claim 1, wherein before the step of debonding the thinned wafer, the method further comprises:
and etching and/or metallizing the back surface of the bonded wafer.
4. The method of claim 1, wherein bonding the front surface of the trimmed wafer to a support plate comprises:
spin coating Jie Jiaoceng on the front side of the trimmed wafer;
spin-coating an adhesion layer on the surface of the supporting plate, which is close to the wafer;
placing the front surface of the wafer with the photoresist layer on the surface of the supporting plate with the adhesion layer;
removing the photoresist layer and the adhesion layer overflowed from the edge of the wafer;
and bonding the front surface of the wafer with the supporting plate by curing the photoresist layer and the adhesive layer at high temperature.
5. The method of claim 4, wherein said debonding the thinned wafer comprises:
and de-bonding the thinned wafer through ultraviolet irradiation.
6. The wafer thinning method of claim 1, wherein the trimming the front side edge of the wafer to be thinned comprises:
and trimming the front edge of the wafer to be thinned through mechanical cutting.
7. The wafer thinning method according to any one of claims 1 to 6, wherein the depth of the trimming is greater than the target thickness.
8. The wafer thinning method according to claim 7, wherein the trimming depth is 100 μm to 200 μm larger than the target thickness and includes values of both ends.
9. The method of claim 8, wherein the trimming has a width of 1.5mm to 3mm and includes values at both ends.
10. A wafer, comprising: a wafer prepared by the wafer thinning method according to any of claims 1 to 9.
CN202311386980.9A 2023-10-24 2023-10-24 Wafer thinning method and wafer Pending CN117542729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311386980.9A CN117542729A (en) 2023-10-24 2023-10-24 Wafer thinning method and wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311386980.9A CN117542729A (en) 2023-10-24 2023-10-24 Wafer thinning method and wafer

Publications (1)

Publication Number Publication Date
CN117542729A true CN117542729A (en) 2024-02-09

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Application Number Title Priority Date Filing Date
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