CN117476769A - 一种基于二维半导体的神经突触电子器件及其制备方法 - Google Patents
一种基于二维半导体的神经突触电子器件及其制备方法 Download PDFInfo
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Abstract
本发明揭示了一种基于二维半导体的神经突触电子器件及其制备方法。所述神经突触电子器件包括衬底层、栅极层、介质层以及作为沟道材料的二维半导体材料。该神经突触电子器件单元具备三个输出端口,其中源极输出端口标记为电极一,漏极输出端口标记为电极二,而栅极调控端口则被标记为电极三。介质层可位于沟道的底部或顶部,或者形成双栅调控沟道输出(电极四)。沟道与电极之间形成可靠的欧姆接触,而介质层与沟道材料之间的接触优良。此外,该神经突触电子器件具备柔性基底兼容性,且可在其顶部和底部进行封装。本发明还提供了阵列及三维器件构架制备方法。
Description
技术领域
本发明涉及神经突触电子器件及其制备方法,特别是基于二维半导体的神经突触电子器件。这些器件用于构建具有柔性基底兼容性的神经突触电子器件,并且提供了适用于阵列和三维器件构架制备的方法。
背景技术
在过去几年中,数字技术取得了巨大的进步,特别是图形处理单元(GPU)和中央处理单元(CPU)的发展,这极大地推动了人工智能(AI)的发展。然而,这种快速发展带来了对硬件性能的不断增长的需求,已经超出了摩尔定律的预测范围。冯诺依曼计算架构存在一个众所周知的问题,即“内存墙”,这是由于处理单元和内存的物理分离所导致的。为了克服这一瓶颈,神经形态计算已经成为一种有前景的新计算范式,能够在内存中进行大规模并行处理。
开发一种受大脑启发的新型计算机系统,即神经形态系统,有望解决标准冯·诺依曼计算架构的局限性。尽管大规模集成芯片通常使用具有专门计算模型的数字处理器内核,但这些模型并不能准确复制传统冯诺依曼设计中的自然大脑过程。因此,需要采用创新策略的独特计算系统来实现模拟人脑的并行网络,从而实现大规模且节能的处理。最近,一种被称为“忆阻器”的电阻式随机存取存储器(RRAM)器件被认为是一种人工突触,可以同时执行电信号传导和突触权重变化,提供了关键的存储和计算功能。
为了应对这一挑战,研究人员开始着手开发新型二维材料,例如石墨烯(Gr)、过渡金属硫族化合物、六方氮化硼(h-BN)、黑磷(BP)等,这些材料在神经突触电子器件方面具备显著的优势。这主要体现在其原子级薄度、卓越的电子传输性能以及可调控的电学特性上。这使得二维材料能够模拟神经突触的工作原理,实现类似生物神经元之间的信号传递和突触可塑性。此外,二维材料还具备高带宽、低功耗和快速响应等特点,为神经突触电子器件的高性能和低能耗操作提供了理想的平台,有望在人工智能和神经网络等领域发挥重要作用。
然而,目前仍然存在一些挑战,如制备工艺的复杂性、难以实现阵列化集成以及大规模生产等技术问题,这限制了基于各种范德瓦尔斯异质结的二维半导体神经突触电子器件的进一步发展和应用。因此,迫切需要一种基于二维半导体的神经突触电子器件及其制备方法,以简化制备工艺,有利于大规模生产和应用,解决传统方法的复杂性和效率问题。该发明的背景技术涵盖了神经突触电子器件的制备、功能多样性、柔性基底兼容性以及制备方法的改进等方面,为神经突触电子器件领域的发展提供了有前景的解决方案。
发明内容
针对现有技术中的上述不足,本发明涉及一种基于二维半导体的神经突触电子器件及其制备方法。该器件包括衬底层、栅极层、介质层和作为沟道材料的二维半导体材料。神经突触电子器件单元具备三个(或者四个)输出端口,包括源极输出端口(电极一)、漏极输出端口(电极二)和栅极(顶栅和底栅)调控端口(输出端口三或四)。介质层可以位于沟道的底部或顶部,也可以形成双栅调控沟道输出。此外,沟道与电极之间形成可靠的欧姆接触,而介质层与沟道材料之间的接触非常良好。这一神经突触电子器件具备柔性基底兼容性,并且可以在其顶部和底部进行封装。同时,本发明提供了一种制备阵列及三维器件构架的方法。
为实现上述设计目的,本发明解决现有技术问题所采用的关键技术步骤包括以下关键部分:
衬底层:神经突触电子器件的底层,提供支持和稳定性。
栅极层:位于衬底层之上的层,用于控制电流流动和器件的工作状态。
介质层:介质层位于栅极层之上或之下,与二维半导体沟道材料接触。介质层的位置可以根据需要选择,以调控器件性能。
二维半导体材料(沟道材料):作为神经突触电子器件的关键组成部分,二维半导体材料用作电子流的通道。
神经突触电子器件单元包括以下特征:
三(或四个)个输出端口:包括源极输出端口(电极一)、漏极输出端口(电极二)以及栅极(顶或底)调控端口(输出端口三或四),用于控制和调节电子流的行为。
介质层位置:介质层可位于沟道的底部或顶部,或者形成双栅调控沟道输出。这个选择性的位置安排允许对电子流的控制和调节。
欧姆接触:沟道与电极之间形成可靠的欧姆接触,确保电子流的稳定传输。
柔性基底兼容性:该神经突触电子器件具备柔性基底兼容性,使其能够适应各种应用场景,并在柔性电子设备中得以使用。
封装能力:该神经突触电子器件可在其顶部和底部进行封装,提供保护和稳定性。
此外,本发明还提供了一种制备该神经突触电子器件的方法,包括以下步骤:
形成栅极层:在衬底层上形成栅极层,以用于控制电子流。
形成介质层:在栅极层上形成介质层,这一层可以选择位于沟道的底部或顶部,或形成双栅调控沟道输出,以满足器件性能需求。
形成二维半导体材料:在介质层上形成二维半导体材料,用作电子流的通道。
形成电极一和电极二:形成源极和漏极,以在二维半导体材料上形成电子流的输入和输出。
形成输出端口三:形成栅极调控端口,用于调节电子流的行为。
形成透明封装层:最后,形成透明封装层,分别封装器件的顶部和底部,提供保护和稳定性。
综上所述,本发明具有以下优点:
基于二维半导体材料:采用二维半导体材料作为沟道材料,具备出色的电子特性,有助于提高神经突触电子器件的性能。
多输出端口设计:神经突触电子器件单元配置三个输出端口,包括源极输出端口(电极一)、漏极输出端口(电极二)以及栅极(顶或底)调控端口(输出端口三或四),使器件更加多功能化。
介质层的灵活性:介质层可位于沟道的底部或顶部,或形成双栅调控沟道输出,为器件的电子性能调控提供了更多可能性。
可靠的欧姆接触:沟道与电极之间形成可靠的欧姆接触,有助于提高电子传输效率,从而增强器件性能。
优良的材料接触性:介质层与沟道材料之间的接触优良,确保了材料之间的有效能量传输和信息交互。
柔性基底兼容性:本发明的神经突触电子器件具备柔性基底兼容性,可适应多种应用场景,包括柔性电子设备领域。
封装性能:该器件可在顶部和底部进行封装,增强其稳定性和保护性,有助于延长器件的寿命。
制备方法简单:本发明提供了制备方法,具备操作简单、易于实施等特点,有望促进大规模生产和广泛应用。
总的来说,本发明的神经突触电子器件及其制备方法综合了多种优点,为光电子学和信息技术领域带来了重要的创新。
附图说明
图1为基于二维半导体的神经突触电子器件单元的示意图;
图2为基于二维半导体的神经突触电子器件阵列化的示意图;
图3为基于二维半导体的神经突触电子器件3维堆叠的示意图;
图4为实施例1所得基于二维半导体的神经突触电子器件单元-1V到1V的I-V扫描结果;
其中,1、底栅衬底层;2、底栅电极;3、底栅介质层;4、源漏电极一;5、二维材料导电沟道;6、源漏电极二;7、顶栅介质层;8、顶栅电极;9、顶栅衬底层;10、透明封装层。
具体实施方式
实施例1
一种基于二维半导体的神经突触电子器件3维阵列,包括若干神经突触电子器件单元,神经突触电子器件单元包括底栅衬底层1,底栅衬底层1上设置有底栅电极2,底栅电极2上设置有含底栅介质层3,底栅介质层3上一侧部设置有源漏电极一5,底栅介质层3上中间设置有二维材料导电沟道,底栅介质层3上另一侧部设置有源漏电极二6,6上部设置有顶栅介质层7,顶栅介质层7上部设置有顶栅电极8,顶栅电极8上部设置有顶栅衬底层9,顶栅衬底层9上设置有透明封装层10。
上述可集成的一种基于二维半导体的神经突触电子器件,依次包括以下步骤:
1.在Si/SiO2衬底上制备金属底栅电极。首先,使用光刻工艺定义底(或顶)栅金属电极的掩膜图形,并通过电子束蒸发沉积5nm的Cr和35nm的Au薄膜。随后,进行金属剥离工艺,以获得图形化的底栅电极。
2.制备绝缘底介质层。首先,在衬底上生长30nm厚的SiO2介质薄膜,然后在300℃下进行1.5小时的退火,以形成接触良好的绝缘介质层。
3.湿法转移和图形化CVD石墨烯。首先,在CVD合成的Cu基石墨烯薄膜上旋涂PMMA溶液,经过刻蚀后将石墨烯转移到目标衬底。然后,用丙酮清洗去除PMMA,使用光刻工艺制备阵列化的石墨烯沟道掩膜图形,然后使用氧等离子体去胶机刻蚀未受保护的区域,最后去除光刻胶,得到图形化的石墨烯导电沟道阵列。
4.制备源漏电极。使用光刻工艺在含有石墨烯阵列的衬底上制备金属电极图形,然后以的速率分别沉积5nm的Ti和35nm的Au薄膜。通过电子束蒸镀设备制备金属源漏电极一和源漏电极二。
5.制备绝缘顶介质层。首先,在衬底上生长30nm厚的SiO2介质薄膜,然后在300℃下进行1.5小时的退火,以形成接触良好的绝缘介质层。
6.电子束蒸发沉积5nm的Ti和35nm的Au薄膜。随后,进行金属剥离工艺,以获得图形化的顶栅电极。然后,采用原子层沉积设备在沟道上方沉积35nm厚的Al2O3保护层。
7.使用引线键合机将源漏电极、底和顶栅电极与外部电路相连,完成基于二维半导体的神经突触电子器件阵列的制备。这个实施例的神经突触电子器件具有出色的柔性基底兼容性,可以在顶部和底部进行封装,适用于各种柔性电子设备。
这些步骤描述了制备基于二维半导体的神经突触电子器件的方法,该方法允许集成多个器件单元以及阵列化的构架。
实施例2
一种基于二维半导体的神经突触电子器件3维阵列,包括若干神经突触电子器件单元,神经突触电子器件单元包括底栅衬底层1,底栅衬底层1上设置有底栅电极2,底栅电极2上设置有含底栅介质层3,底栅介质层3上一侧部设置有源漏电极一5,底栅介质层3上中间设置有二维材料导电沟道,底栅介质层3上另一侧部设置有源漏电极二6,6上部设置有顶栅介质层7,顶栅介质层7上部设置有顶栅电极8,顶栅电极8上部设置有顶栅衬底层9,顶栅衬底层9上设置有透明封装层10。
上述发明揭示了一种基于二维半导体的神经突触电子器件及其制备方法。所述神经突触电子器件的制备方法依次包括以下步骤:
1.在Si/SiO2衬底上制备金属底栅电极,通过电子束蒸发镀膜设备在衬底上分别沉积5nm和35nm厚的Cr和Au薄膜,以形成图形化的底栅电极。
2.制备绝缘介质层,采用射频溅射设备在衬底上制得260nm厚的SiO2介质层薄膜,然后进行300℃的退火1.5小时,以确保表面平整并具有良好的接触性。
3.实现CVT AgBiP2Se6的干法转移和图形化,包括将AgBiP2Se6块体材料机械剥离并转移到底部介质层上,然后利用光刻工艺制备出阵列化的AgBiP2Se6导电沟道掩膜图形,并通过氧等离子体去胶机去除未受保护的部分。
4.制备源漏电极,通过光刻工艺制备金属电极掩膜图形,然后使用电子束蒸镀设备以的速率沉积5nm和35nm厚的Cr和Au薄膜,随后进行lift-off工艺,以得到金属源漏电极一和源漏电极二。
5.制备具有透明的封装材料,首先在CVD合成的大面积连续Cu基h-BN薄膜上旋涂一层PMMA,并在烘干后置于FeCl3溶液中以去除Cu,然后将h-BN转移到目标衬底,最后使用丙酮溶液清洗以封装和保护器件。
6.采用引线键合机将源漏电极和底栅电极与外电路相连,以制备基于二维半导体的神经突触电子器件。
这一制备方法可用于制备基于二维半导体的神经突触电子器件,该器件具备优良的性能,并且具有柔性基底兼容性,可在顶部和底部进行封装。因此,本发明为制备工艺简单、易于集成的二维半导体的神经突触电子器件提供了一种有效的方法。
通过同时施加源漏电压,对实施例1中所得的基于二维半导体的神经突触电子器件单元进行了测试。其I-V测试结果如图4所示,为二维忆阻器器件的阵列集成和稳定测试应用提供了可能性。这些图表证明了电场可以有效地实现对器件的调控,从而增加了该器件的应用范围。
实施例3
一种基于二维半导体的神经突触电子器件3维阵列,包括若干神经突触电子器件单元,神经突触电子器件单元包括底栅衬底层1,底栅衬底层1上设置有底栅电极2,底栅电极2上设置有含底栅介质层3,底栅介质层3上一侧部设置有源漏电极一5,底栅介质层3上中间设置有二维材料导电沟道,底栅介质层3上另一侧部设置有源漏电极二6,6上部设置有顶栅介质层7,顶栅介质层7上部设置有顶栅电极8,顶栅电极8上部设置有顶栅衬底层9,顶栅衬底层9上设置有透明封装层10。
上述发明揭示了一种基于二维半导体的神经突触电子器件及其制备方法。所述神经突触电子器件的制备方法依次包括以下步骤:
1.在涤纶树脂PET柔性衬底上制备金属底栅,首先将硬质掩膜版放置在涤纶树脂PET柔性衬底上,使用热蒸发镀膜设备以的速率直接沉积35nm厚的Ti薄膜,形成图形化的底栅电极。
2.制备h-BN薄膜的干法转移底栅层,制备10%质量分数的PVA水溶液并制得PVA膜,将其放置在粘附于透明玻璃片一端的PDMS衬底上,形成PVA干法转移膜。然后,使用PVA转移膜将机械剥离于SiO2衬底上的h-BN单层或少层薄膜缓慢粘起。将涤纶树脂PET目标衬底加热至55℃,将PVA膜上的样品对准目标位置缓慢均匀压下,5分钟后提起玻璃片,实现h-BN薄膜到图形化的底栅电极的定位转移,获得h-BN底部介质层。
3.制备WS2薄膜的干法转移,制备步骤同步骤2,实现WS2薄膜到目标衬底的定位转移,形成图形化的WS2导电沟道阵列。
4.制备源漏电极,通过光刻工艺在步骤3获得的衬底上制备电极掩膜图形。然后,使用电子束蒸镀设备以的速率分别沉积5nm和35nm厚的Ti和Au薄膜。
5.制备h-BN薄膜的干法转移顶栅层,制备步骤同步骤2,实现h-BN薄膜到图形化的顶栅电极的定位转移,得到h-BN顶部介质层。
6.利用热蒸发镀膜设备,在涤纶树脂PET柔性衬底上直接沉积35nm厚的Ti薄膜,形成图形化的顶栅电极。
7.利用原子层沉积设备,在沟道上方沉积一层30nm厚的Al2O3封装保护层。
8.使用键合器将源漏电极,底和顶栅电极与外电路相连,制备基于二维半导体的神经突触电子器件阵列。
这些步骤描述了基于二维半导体的神经突触电子器件的制备方法,其中包括金属底栅的制备、h-BN薄膜和WS2薄膜的干法转移、源漏电极的制备、h-BN顶栅的制备、封装保护层的沉积以及电路连接等关键步骤。
虽然已经详细描述了本发明的具体实施方式,但请注意,这些描述并不应被解释为对本专利的保护范围进行了限定。在权利要求书所陈述的范围内,本领域的技术专家可以进行各种修改和变形,而无需进行创造性劳动,这些修改和变形仍然属于本专利的保护范围。
Claims (11)
1.一种基于二维半导体的神经突触电子器件,包括:
1.1衬底层,该衬底包含二氧化硅(SiO2)、氮化硅(Si3N4)、蓝宝石(Sapphire)、氧化铝(Al2O3)、硅碳化(Silicon Carbide)、氮化镓(Gallium Nitride)、云母(Mica)、氮化铝(AlN)、高介电常数绝缘材料和聚合物绝缘材料等。
1.2栅极层,该栅极层可以是金属(Metals)如:铝(Al)、铜(Cu)、铬(Cr)、钨(W)等;多晶硅(Polysilicon);硅基复合材料(Silicon-Based Compounds)如:如氮化硅(SiliconNitride)和氧化硅(Silicon Dioxide);导电高分子材料(Conductive Polymers)如:聚咔唑(Polycarbazole)和聚苯乙烯(Polystyrene);石墨烯(Graphene);二维材料如:二硫化钼(Molybdenum Disulfide,MoS2)和二硫化钨(Tungsten Disulfide,WS2)等;金属氧化物(Metal Oxides)如:氧化铝(Aluminum Oxide,Al2O3)和氧化铌(Niobium Oxide,Nb2O5)。
1.3介质层,该介质层可以是氧化硅(Silicon Dioxide,SiO2);氮化硅(SiliconNitride,Si3N4);高介电常数材料(High-K Dielectrics)如:高介电常数材料(High-KDielectrics);氮化铝(Aluminum Nitride,AlN);有机聚合物(Organic Polymers);玻璃(Glass);硅氮化物(Silicon Nitride-Silicon Oxide Composite)和氮掺杂二氧化硅(Nitrogen-Doped Silicon Dioxide),介质层位于栅极层之上或之下。
1.4二维半导体材料,作为沟道材料,沟道材料位于介质层之上或之下。
1.5神经突触电子器件单元,神经突触电子器件单元具备以下特征:
1.5.1三个(或者四)输出端口,其中源极输出端口被标记为电极一,漏极输出端口被标记为电极二,栅极调控端口被标记为电极三,双栅时另一个栅极标记为电极四。
1.5.2介质层可位于沟道的底部或沟道的顶部。
1.5.3沟道与电极之间形成可靠的欧姆接触。
1.5.4介质层与沟道材料之间的接触优良。
1.5.5具备柔性基底兼容性,该柔性基底包括聚合物基底如:聚烯烃等;聚酰亚胺(Polyimide,PI);聚酯(Polyester);聚酰胺(Polyamide,PA);聚氨酯(Polyurethane,PU);硅基柔性基底;金属薄膜基底;纸张和纤维基底;聚合物复合材料和弹性基底。
1.5.6可在其顶部和底部进行封装。
2.根据权利要求1所述的神经突触电子器件,其中所述的二维半导体材料包括石墨烯(Graphene);过渡金属二硫化物(Transition Metal Dichalcogenides,TMDs)如:钼二硫化物(MoS2)、硒化钨(WSe2)、硫化钼(MoSe2)等;磷化硅(Silicene);磷化氮(Phosphorene);黑磷(Black Phosphorus);二硫化钼硒化钼合金(MoSe2-WSe2 Alloy);碳化硅(SiliconCarbide,SiC)和多元二维材料如:三元二维材料氮磷化硼(BP3N3)和硫化钨二钼(W2MoS4),四元二维材料"CuInP2S6"和"AgBiP2Se6"材料,五元二维材料如二硫化锗碲(GeTe2Sb2Te3)等和多元掺杂二维材料如Cu:AgBiP2Se6等。
3.根据权利要求1所述的神经突触电子器件,其中所述的介质层位于沟道的底部。
4.根据权利要求1所述的神经突触电子器件,其中所述的介质层位于沟道的顶部。
5.根据权利要求1所述的神经突触电子器件,其中所述的沟道材料为半导体材料。
6.根据权利要求1所述的神经突触电子器件,其中所述的沟道材料为导电性半导体材料。
7.根据权利要求1所述的神经突触电子器件,其中所述的神经突触电子器件单元的输出端口三(或四)用于栅极调控。
8.一种基于二维半导体的神经突触电子器件的制备方法,包括以下步骤:
8.1在衬底层上形成栅极层。
8.2在栅极层上形成介质层。
8.3在介质层上形成二维半导体材料作为沟道材料。
8.4形成电极一和电极二,以在二维半导体材料上形成源极和漏极。
8.5形成输出端口三或者四,用于(顶或者底或者同时存在)栅极调控。
8.6形成透明封装层,分别封装器件的顶部和底部。
9.根据权利要求8所述的制备方法,其中步骤8.3中的二维半导体材料包括二维材料。
10.根据权利要求8所述的制备方法,其中步骤8.2中的介质层位于沟道的底部。
11.根据权利要求8所述的制备方法,其中步骤8.2中的介质层位于沟道的顶部。
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