CN117434993B - Current-limiting value clamping voltage generation circuit related to slope compensation voltage - Google Patents
Current-limiting value clamping voltage generation circuit related to slope compensation voltage Download PDFInfo
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- CN117434993B CN117434993B CN202311367936.3A CN202311367936A CN117434993B CN 117434993 B CN117434993 B CN 117434993B CN 202311367936 A CN202311367936 A CN 202311367936A CN 117434993 B CN117434993 B CN 117434993B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
A current-limiting value clamping voltage generating circuit related to slope compensation voltage relates to the technical field of direct-current voltage conversion circuits, and has the structure that: the non-inverting input end of the first amplifier is connected with the voltage V SLOPE1, the inverting input end of the first amplifier is connected with the drain electrode of the twelfth NMOS tube, and the output end of the first amplifier is connected with the source electrode of the third NMOS tube to form a reference point H; the non-inverting input end of the second amplifier is connected with the current source IN2, and the inverting input end of the second amplifier is connected with the output end of the second amplifier to form a reference point F; the reference point F is connected with the VO output end and is also connected with a current mirror through a third resistor; the drain electrode of the twelfth NMOS tube is connected with the reference point F through the second resistor, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the reference point H; the drain electrode of the third NMOS tube is connected with a current source IN2, and the grid electrode is IN short circuit with the source electrode; the drain electrode of the fourth NMOS tube is connected with the current source IN2, the drain electrode is grounded through the first resistor and the first capacitor IN turn, the grid electrode of the fourth NMOS tube is connected with the chip turn-off signal ENN, and the source electrode of the fourth NMOS tube is grounded. The invention solves the problem that the overcurrent value is reduced due to the existence of the slope compensation voltage under the condition of large duty ratio.
Description
Technical Field
The invention relates to the technical field of direct-current voltage conversion circuits, in particular to a current-limiting value clamping voltage generating circuit related to slope compensation voltage.
Background
The traditional current mode DC-DC adopts a slope compensation technology to realize the stability of a current loop under a high duty ratio. The principle of slope compensation is to subtract a voltage with a slope of Sen from the control voltage VC or to add a voltage with a slope of Sen to the detected inductor current signal, and the instability of duty cycle greater than 50% will be improved after adding slope compensation. However, the slope compensation brings additional non-ideal factors, namely that the current limit value of the DC-DC under the large duty ratio is reduced due to the existence of the slope voltage, namely that the current limit value of the DC-DC under the small duty ratio is larger than the current limit value under the large duty ratio.
As shown in fig. 3, in the overcurrent state of the conventional current mode DC-DC converter, the different duty cycle overcurrent values are different due to the addition of the slope compensation. The over-current clamping voltage VEA LIMIT output by the error amplifier is a fixed voltage, the voltage is subtracted by the ramp voltage to generate VEA LIMIT -Sen voltage in the figure (solid line voltage in the figure), the over-current voltage is I LIMIT1 when the DC-DC works in the small duty ratio (D1 in the figure), and the over-current voltage is I LIMIT2 when the DC-DC works in the large duty ratio (D2 in the figure), because the action I LIMIT2 of the ramp is smaller than I LIMIT1, the over-current value is non-uniform.
Disclosure of Invention
The invention aims to provide a current-limiting value clamping voltage generating circuit related to a slope compensation voltage, when a load is overweight and reaches a current-limiting state, the output of an error amplifier is clamped by the clamping voltage, and the clamping voltage is increased along with the increase of the slope compensation voltage in one working period, so that the problem that the overcurrent value is reduced due to the existence of the slope compensation voltage under a large duty ratio is solved.
In order to achieve the above purpose, the invention adopts the following technical scheme: a current-limiting value clamping voltage generating circuit related to slope compensation voltage has the structure as follows: the circuit comprises a first amplifier, a second amplifier and a current mirror;
The non-inverting input end of the first amplifier is connected with the voltage V SLOPE1, the inverting input end of the first amplifier is connected with the drain electrode of the twelfth NMOS tube to form a reference point M, and the output end of the first amplifier is connected with the source electrode of the third NMOS tube to form a reference point H;
the non-inverting input end of the second amplifier is connected with a current source IN2; the inverting input end of the device is connected with the output end of the device to form a reference point F; the reference point F is connected with the VO output end;
The reference point F is also connected with the current mirror through a third resistor;
The drain electrode of the twelfth NMOS tube is connected with the reference point F through the second resistor, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the reference point H;
The drain electrode of the third NMOS tube is connected with a current source IN2, and the grid electrode is IN short circuit with the source electrode;
The drain electrode of the fourth NMOS tube is connected with the current source IN2, the drain electrode is grounded through the first resistor and the first capacitor IN turn, the grid electrode of the fourth NMOS tube is connected with the chip off signal ENN, when the chip off signal ENN is high, the electric charge on the capacitor of the first capacitor C1 is discharged, and the source electrode of the fourth NMOS tube is grounded.
Further, the first amplifier is composed of a first PMOS tube, a second PMOS tube, a thirteenth NMOS tube, a first NMOS tube, a second NMOS tube, a seventh NMOS tube and an eighth NMOS tube, wherein:
the source electrode of the first PMOS tube is connected with the power supply voltage VIN, the grid electrode is in short circuit with the drain electrode, and the drain electrode is also connected with the drain electrode of the first NMOS tube;
the source electrode of the second PMOS tube is connected with the power supply voltage VIN, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the grid electrode of the thirteenth NMOS tube and the drain electrode of the second NMOS tube;
the drain electrode of the thirteenth NMOS tube is connected with the power supply voltage VIN, and the source electrode of the thirteenth NMOS tube is connected with the drain electrode of the eighth NMOS tube to be used as the output end of the first amplifier to be connected with the source electrode of the third NMOS tube together so as to form a reference point H;
The grid electrode of the first NMOS tube is used as the non-inverting input end of the first amplifier to be connected with the voltage V SLOPE1, and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and the drain electrode of the seventh NMOS tube;
The grid electrode of the second NMOS tube is used as the inverting input end of the first amplifier to be connected with the drain electrode of the twelfth NMOS tube to form a reference point M;
The second amplifier is composed of a third PMOS tube, a fourth PMOS tube, a fourteenth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a ninth NMOS tube and a tenth NMOS tube, wherein:
the source electrode of the third PMOS tube is connected with the power supply voltage VIN, the grid electrode is in short circuit with the drain electrode, and the drain electrode is also connected with the drain electrode of the fifth NMOS tube;
The source electrode of the fourth PMOS tube is connected with the power supply voltage VIN, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the grid electrode of the fourteenth NMOS tube and the drain electrode of the sixth NMOS tube;
the drain electrode of the fourteenth NMOS tube is connected with the power supply voltage VIN, and the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the tenth NMOS tube and is commonly used as the output end of the second amplifier;
The grid electrode of the fifth NMOS tube is used as the non-inverting input end of the second amplifier to be connected with a current source IN2, and the source electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and the drain electrode of the ninth NMOS tube;
The grid electrode of the sixth NMOS tube is used as the inverting input end of the second amplifier to be connected with the source electrode of the fourteenth NMOS tube to form a reference point F; the reference point F is simultaneously connected with the drain electrode of the tenth NMOS tube;
The seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube also form a current mirror together with the eleventh NMOS tube, wherein:
The gates of the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are connected with the gate of the eleventh NMOS tube, and the source is grounded;
The drain electrode of the eleventh NMOS tube is connected with the reference point F through the third resistor, and the source electrode of the eleventh NMOS tube is grounded.
The beneficial effects of the invention are as follows:
the problem that the overcurrent value is reduced due to the existence of slope compensation voltage under a large duty ratio is solved, and the accuracy of the overcurrent value is improved.
Drawings
FIG. 1 is a circuit block diagram of an embodiment of the present invention;
FIG. 2 is a circuit diagram of an embodiment of the present invention;
FIG. 3 is a graph showing the difference of current limiting values due to conventional current-mode DC-DC ramp compensation;
FIG. 4 is a schematic illustration of the present invention to solve the problem of inconsistent over-current values;
fig. 5 is a waveform diagram of the over-current clamp voltage obtained by the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Fig. 1 and 2 show a specific embodiment of the present invention, which is a current limit value clamping voltage generating circuit related to a slope compensation voltage, and the structure thereof is as follows: comprises a first amplifier 1, a second amplifier 2 and a current mirror 3;
the non-inverting input end of the first amplifier 1 is connected with the voltage V SLOPE1, the inverting input end of the first amplifier is connected with the drain electrode of the twelfth NMOS tube MN12 to form a reference point M, and the output end of the first amplifier is connected with the source electrode of the third NMOS tube MN3 to form a reference point H;
The non-inverting input end of the second amplifier 2 is connected with a current source IN2; the inverting input end of the device is connected with the output end of the device to form a reference point F; the reference point F is connected with the VO output end;
the reference point F is also connected with the current mirror 3 through a third resistor R3;
The drain electrode of the twelfth NMOS tube MN12 is connected with a reference point F through a second resistor R2, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with a reference point H;
The drain electrode of the third NMOS tube MN3 is connected with a current source IN2, and the grid electrode is IN short circuit with the source electrode;
The drain electrode of the fourth NMOS tube MN4 is connected with the current source IN2, the drain electrode is grounded through the first resistor R1 and the first capacitor C1 IN sequence, the grid electrode of the fourth NMOS tube is connected with the chip off signal ENN, when the chip off signal ENN is high, the electric charge on the capacitor of the first capacitor C1 is discharged, and the source electrode of the fourth NMOS tube is grounded.
In this embodiment, the first amplifier 1 is composed of a first PMOS transistor MP1, a second PMOS transistor MP2, a thirteenth NMOS transistor MN13, a first NMOS transistor MN1, a second NMOS transistor MN2, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8, wherein:
The source electrode of the first PMOS tube MP1 is connected with the power supply voltage VIN, the grid electrode is in short circuit with the drain electrode, and the drain electrode is also connected with the drain electrode of the first NMOS tube MN 1;
the source electrode of the second PMOS tube MP2 is connected with the power supply voltage VIN, the grid electrode of the second PMOS tube MP1 is connected with the grid electrode of the thirteenth NMOS tube MN13, and the drain electrode of the second NMOS tube MN 2;
the drain electrode of the thirteenth NMOS tube MN13 is connected with the power supply voltage VIN, the source electrode of the thirteenth NMOS tube MN13 is connected with the drain electrode of the eighth NMOS tube MN8 to be used as the output end of the first amplifier 1 to be connected with the source electrode of the third NMOS tube MN3 together so as to form a reference point H;
The grid electrode of the first NMOS tube MN1 is used as the non-inverting input end of the first amplifier 1 to be connected with the voltage V SLOPE1, and the source electrode of the first NMOS tube MN1 is connected with the source electrode of the second NMOS tube MN2 and the drain electrode of the seventh NMOS tube MN 7;
The grid electrode of the second NMOS tube MN2 is used as the inverting input end of the first amplifier 1 to be connected with the drain electrode of the twelfth NMOS tube MN12 to form a reference point M;
The second amplifier 2 is composed of a third PMOS MP3, a fourth PMOS MP4, a fourteenth NMOS MN14, a fifth NMOS MN5, a sixth NMOS MN6, a ninth NMOS MN9, and a tenth NMOS MN10, wherein:
the source electrode of the third PMOS tube MP3 is connected with the power supply voltage VIN, the grid electrode is in short circuit with the drain electrode, and the drain electrode is also connected with the drain electrode of the fifth NMOS tube MN 5;
The source electrode of the fourth PMOS tube MP4 is connected with the power supply voltage VIN, the grid electrode of the fourth PMOS tube MP3 is connected with the grid electrode of the fourteenth NMOS tube MN14 and the drain electrode of the sixth NMOS tube MN 6;
The drain electrode of the fourteenth NMOS tube MN14 is connected with the power supply voltage VIN, and the source electrode of the fourteenth NMOS tube MN14 is connected with the drain electrode of the tenth NMOS tube MN10 to be used as the output end of the second amplifier 2 together;
the grid electrode of the fifth NMOS tube MN5 is used as the non-inverting input end of the second amplifier 2 to be connected with the current source IN2, and the source electrode is connected with the source electrode of the sixth NMOS tube MN6 and the drain electrode of the ninth NMOS tube MN 9;
the grid electrode of the sixth NMOS tube MN6 is used as the inverting input end of the second amplifier 2 to be connected with the source electrode of the fourteenth NMOS tube MN14 to form a reference point F; the reference point F is simultaneously connected with the drain electrode of the tenth NMOS tube MN 10;
the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 further form a current mirror 3 together with the eleventh NMOS transistor MN11, where:
The gates of the seventh NMOS tube MN7, the eighth NMOS tube MN8, the ninth NMOS tube MN9 and the tenth NMOS tube MN10 are connected with the gate of the eleventh NMOS tube MN11, and the source is grounded;
the drain of the eleventh NMOS transistor MN11 is connected to the reference point F through the third resistor R3, and the source is grounded.
The invention provides a solution to the non-ideal factor in the traditional current-mode DC-DC converter slope compensation technology shown in fig. 3, namely, the fixed current-limiting value clamping voltage VEA LIMIT is changed into a voltage which changes along with the slope compensation voltage, and the change of the voltage compensates the inconsistent overcurrent value caused by the slope compensation voltage. The working principle is shown in fig. 4, VEA LIMIT is the clamping voltage of the overcurrent value, and VEA LIMIT minus the slope compensation voltage Sen generates voltage V C,VC, and the voltage is constant during the conduction period of the high-side tube in the DC-DC converter, so that the overcurrent value of the DC-DC is consistent no matter how the duty ratio is changed.
The clamp voltage generation principle of the circuit is as follows:
When V SLOPE1 is a ramp stage (i.e., a high-side tube conduction stage, which is a ramp-up stage), the first amplifier 1 and the second amplifier 2 both operate in a modulation state, and the non-inverting input terminal of the first amplifier 1, i.e., the gate voltage of MN1, is equal to the inverting input terminal of the first amplifier 1, i.e., the gate voltage of MN2, and is equal to the VO voltage. This operating state modulates the voltage at reference point H to an output of V TH that is one V SLOPE2 voltage higher than V SLOPE2 voltage, such that the V SLOPE2 voltage is equal to the VO voltage and follows the output voltage of V SLOPE1, such that the current limit voltage is a direct current level plus the slope compensation voltage, i.e., is related to the slope compensation voltage.
When the high-side tube is turned off and the slope voltage is not needed to carry out stability compensation, the voltage of V SLOPE1 is rapidly reduced to 0, (the function of the function is that a switching tube is turned on through an upper circuit to discharge the charge on a capacitor corresponding to V SLOPE1), the voltage reduction speed of a reference point M is slower, at the moment, the first amplifier 1 enters a comparator mode, the reference point H outputs a low level, the connection between the first amplifier 1 and the second amplifier 2 is cut off, the second amplifier 2 independently works IN a modulation mode, and a current source IN2 flowing to the ground slowly discharges a part of the voltage of V SLOPE2 to prepare for following of the next period. The resulting current limit voltage VO is as shown in fig. 5: the dashed line is the preset dc voltage V EA0, the solid line curve is the V SLOPE1 voltage (the slope compensation voltage corresponds to the Sen voltage in fig. 4), and the dotted line curve is the V SLOPE2 voltage (corresponds to the VEA LIMIT voltage in fig. 4).
Claims (2)
1. A current limit clamp voltage generation circuit associated with a slope compensation voltage, comprising: comprises a first amplifier (1), a second amplifier (2) and a current mirror (3);
the non-inverting input end of the first amplifier (1) is connected with the voltage V SLOPE1, the inverting input end of the first amplifier is connected with the drain electrode of the twelfth NMOS tube (MN 12) to form a reference point M, and the output end of the first amplifier is connected with the source electrode of the third NMOS tube (MN 3) to form a reference point H;
The non-inverting input end of the second amplifier (2) is connected with a current source IN2; the inverting input end of the device is connected with the output end of the device to form a reference point F; the reference point F is connected with the VO output end;
the reference point F is also connected with the current mirror (3) through a third resistor (R3);
The drain electrode of the twelfth NMOS tube (MN 12) is connected with a reference point F through a second resistor (R2), the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with a reference point H;
the drain electrode of the third NMOS tube (MN 3) is connected with a current source IN2, and the grid electrode is IN short circuit with the source electrode;
the drain electrode of the fourth NMOS tube (MN 4) is connected with the current source IN2, the drain electrode is grounded through the first resistor (R1) and the first capacitor (C1) IN sequence, the grid electrode is connected with the chip off signal ENN, and the source electrode is grounded.
2. The current-limited clamp voltage generation circuit associated with a slope compensation voltage of claim 1, wherein:
the first amplifier (1) is composed of a first PMOS tube (MP 1), a second PMOS tube (MP 2), a thirteenth NMOS tube (MN 13), a first NMOS tube (MN 1), a second NMOS tube (MN 2), a seventh NMOS tube (MN 7) and an eighth NMOS tube (MN 8), wherein:
the source electrode of the first PMOS tube (MP 1) is connected with the power supply voltage VIN, the grid electrode is in short circuit with the drain electrode, and the drain electrode is also connected with the drain electrode of the first NMOS tube (MN 1);
the source electrode of the second PMOS tube (MP 2) is connected with the power supply voltage VIN, the grid electrode of the second PMOS tube (MP 1) is connected with the grid electrode of the thirteenth NMOS tube (MN 13) and the drain electrode of the second NMOS tube (MN 2);
The drain electrode of the thirteenth NMOS tube (MN 13) is connected with the power supply voltage VIN, the source electrode of the thirteenth NMOS tube (MN 13) is connected with the drain electrode of the eighth NMOS tube (MN 8) to be used as the output end of the first amplifier (1) and connected with the source electrode of the third NMOS tube (MN 3) together to form a reference point H;
The grid electrode of the first NMOS tube (MN 1) is used as the non-inverting input end of the first amplifier (1) to be connected with the voltage V SLOPE1, and the source electrode of the first NMOS tube (MN 2) is connected with the source electrode of the seventh NMOS tube (MN 7);
the grid electrode of the second NMOS tube (MN 2) is used as the inverting input end of the first amplifier (1) to be connected with the drain electrode of the twelfth NMOS tube (MN 12) to form a reference point M;
the second amplifier (2) is composed of a third PMOS tube (MP 3), a fourth PMOS tube (MP 4), a fourteenth NMOS tube (MN 14), a fifth NMOS tube (MN 5), a sixth NMOS tube (MN 6), a ninth NMOS tube (MN 9) and a tenth NMOS tube (MN 10), wherein:
The source electrode of the third PMOS tube (MP 3) is connected with the power supply voltage VIN, the grid electrode is in short circuit with the drain electrode, and the drain electrode is also connected with the drain electrode of the fifth NMOS tube (MN 5);
the source electrode of the fourth PMOS tube (MP 4) is connected with the power supply voltage VIN, the grid electrode of the fourth PMOS tube (MP 3) is connected with the grid electrode of the fourteenth NMOS tube (MN 14) and the drain electrode of the sixth NMOS tube (MN 6);
the drain electrode of the fourteenth NMOS tube (MN 14) is connected with the power supply voltage VIN, and the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the tenth NMOS tube (MN 10) to be used as the output end of the second amplifier (2) together;
The grid electrode of the fifth NMOS tube (MN 5) is used as the non-inverting input end of the second amplifier (2) to be connected with a current source IN2, and the source electrode of the fifth NMOS tube (MN 6) is connected with the source electrode of the ninth NMOS tube (MN 9);
the grid electrode of the sixth NMOS tube (MN 6) is used as the inverting input end of the second amplifier (2) to be connected with the source electrode of the fourteenth NMOS tube (MN 14) to form a reference point F; the reference point F is simultaneously connected with the drain electrode of the tenth NMOS tube (MN 10);
The seventh NMOS tube (MN 7), the eighth NMOS tube (MN 8), the ninth NMOS tube (MN 9) and the tenth NMOS tube (MN 10) also form a current mirror (3) together with the eleventh NMOS tube (MN 11), wherein:
The gates of the seventh NMOS tube (MN 7), the eighth NMOS tube (MN 8), the ninth NMOS tube (MN 9) and the tenth NMOS tube (MN 10) are connected with the gate of the eleventh NMOS tube (MN 11), and the source is grounded;
the drain electrode of the eleventh NMOS tube (MN 11) is connected with the reference point F through the third resistor (R3), and the source electrode is grounded.
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| CN202311367936.3A CN117434993B (en) | 2023-10-20 | 2023-10-20 | Current-limiting value clamping voltage generation circuit related to slope compensation voltage |
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| CN202311367936.3A CN117434993B (en) | 2023-10-20 | 2023-10-20 | Current-limiting value clamping voltage generation circuit related to slope compensation voltage |
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| CN117434993B true CN117434993B (en) | 2024-06-14 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108599566A (en) * | 2018-05-08 | 2018-09-28 | 电子科技大学 | A kind of buck DC-DC converter self-adaptable slop compensation circuit |
| CN108649800A (en) * | 2018-05-31 | 2018-10-12 | 电子科技大学 | A kind of self-adaptable slop compensation circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6498466B1 (en) * | 2000-05-23 | 2002-12-24 | Linear Technology Corp. | Cancellation of slope compensation effect on current limit |
| KR101105681B1 (en) * | 2010-06-25 | 2012-01-18 | (주)실리콘인사이드 | The Control Circuit for Currnet Progammed Control Swiching Mode DC-DC Converter |
| CN116418210A (en) * | 2021-12-30 | 2023-07-11 | 圣邦微电子（北京）股份有限公司 | Circuit for realizing that peak current mode BOOST current limiting value does not change along with duty ratio by dynamic clamping |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108599566A (en) * | 2018-05-08 | 2018-09-28 | 电子科技大学 | A kind of buck DC-DC converter self-adaptable slop compensation circuit |
| CN108649800A (en) * | 2018-05-31 | 2018-10-12 | 电子科技大学 | A kind of self-adaptable slop compensation circuit |
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Inventor after: Feng Wenjie Inventor after: Zhao Zhengchao Inventor after: Li Gen Inventor after: Fang Haiyan Inventor before: Feng Wenjie Inventor before: Hong Ting Inventor before: Zhao Zhengchao Inventor before: Li Gen Inventor before: Fang Haiyan |
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