CN102420520B - Current limiting protection circuit and direct current (DC)-DC converter integrated with current limiting protection circuit - Google Patents
Current limiting protection circuit and direct current (DC)-DC converter integrated with current limiting protection circuit Download PDFInfo
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- CN102420520B CN102420520B CN201110393505.5A CN201110393505A CN102420520B CN 102420520 B CN102420520 B CN 102420520B CN 201110393505 A CN201110393505 A CN 201110393505A CN 102420520 B CN102420520 B CN 102420520B
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Abstract
The invention discloses a current limiting protection circuit and a direct current (DC)-DC converter integrated with the current limiting protection circuit. By the current limiting protection circuit, the DC-DC converter can control the output voltage of an error amplifier not to exceed a preset voltage value under a slight overload condition, so that a pulse width modulation (PWM) comparator can normally control the on/off of a control tube and further limit a peak value of inductance current; and under a severe overload or output short circuit condition, adverse impact caused by a transmission delay can be weakened by prolonging output square wave and slope compensation saw tooth wave cycles of an oscillator, thereby effectively preventing large current tails and protecting the converter from damage in any fault state. Moreover, the output frequency of the current limiting protection circuit is linearly changed, the phenomenon of state locking can be avoided in a starting process, and the converter can work normally.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of design of the current-limiting protection circuit for DC-DC transducer.
Background technology
Switching Power Supply has the advantages such as efficiency is high, output current is large, volume is little, has become the class Important Circuit in power management chip.
Existing a kind of typical BUCK adjuster structure as shown in Figure 1, by adjusting pipe M0, electric capacity L, voltage stabilizing didoe D1, the feedback network that resistance R 1, R2 form, error amplifier, PWM comparator, drive circuit Driver, rest-set flip-flop, current limit circuit, current sampling circuit Ri and load resistance R and load capacitance C form.Under normal circumstances, clock signal clk is controlled M0 unlatching in the meeting that starts of one-period, inductance L electric current starts to increase, when the sampled voltage of current sampling circuit surpasses the output voltage of error amplifier, the input terminal voltage in the same way of PWM comparator is greater than reverse input end voltage, and output high level is closed thereby adjust pipe M0, discharging in the loop that inductance L consists of diode D1, load resistance R, makes the electric current can be not excessive and damage circuit; Under abnormal condition, under short-circuit conditions, output voltage V
outbe zero, error amplifier output high level, PWM comparator can not be closed M0 pipe normally, now the input terminal voltage in the same way of current limit circuit is higher than reverse input end voltage, can close adjustment pipe M0 by high level of output, thereby Limited Current peak value can be not excessive, avoided the damage of transducer.
But in side circuit, at current peak, reach to close to adjust the Current Limits of pipe and adjust pipe M0 and have a transmission delay between turn-offing.Under normal circumstances, adjust pipe M0 ON time long, propagation delay time is less with respect to adjusting pipe M0 ON time, can ignore, but under heavy duty or short-circuit conditions, owing to adjusting, pipe M0 ON time is very short, propagation delay time can be comparable with adjustment pipe M0 ON time, inductance L is increased current rise time, and now inductance L Current rise slope VIN/L is very large, and electric current descending slope-V
d/ L is very little, thereby causes each cycle inductive current constantly cumulative, forms a very large current tail, causes the damage of transducer.In prior art, for this problem, some solutions have been proposed, such as electric current foldback technique, this technology is under heavy duty or short-circuit conditions, reduce the damage that allows current peak to avoid transducer, but the nonlinear load impact during due to startup, may in circuit start process, cause state locking phenomena, make Switching Power Supply cisco unity malfunction.
Summary of the invention
The object of the invention is the problem existing in order to solve existing DC-DC transducer Limited Current peak value, proposed a kind of current-limiting protection circuit.
Technical scheme of the present invention is: a kind of current-limiting protection circuit, comprise: a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe and an electric capacity and a comparator, concrete annexation is, the one PMOS pipe, the grid of the 2nd PMOS pipe all connects the drain electrode of a PMOS pipe, drain electrode connects respectively a NMOS pipe, the drain electrode of the 2nd NMOS pipe, the source electrode of the one PMOS pipe connects the first outside reference voltage, the source electrode of the 2nd PMOS pipe is as the voltage clamping output of current-limiting protection circuit, the grid of the one NMOS pipe, the 2nd NMOS pipe all connects the first outside bias voltage, and source electrode all connects ground, the grid of the 3rd NMOS pipe connects the drain electrode of the 2nd NMOS pipe, and drain electrode connects the source electrode of the 2nd PMOS pipe, and source electrode connects ground, the grid of the 3rd PMOS pipe, the 4th PMOS pipe all connects the second outside bias voltage, the drain electrode of the 3rd PMOS pipe connects the source electrode of the 5th PMOS pipe and the 6th PMOS pipe, the drain electrode of the 4th PMOS pipe connects the drain electrode of the 7th NMOS pipe, and the source electrode of the 3rd PMOS pipe, the 4th PMOS pipe all connects the first power supply, the grid of the 5th PMOS pipe connects the grid of the second outside reference voltage, the 6th PMOS pipe as the input terminal of current-limiting protection circuit, and the drain electrode of the 5th PMOS pipe, the 6th PMOS pipe connects respectively the drain electrode of the 4th NMOS pipe, the 5th NMOS pipe, the grid of the 4th NMOS pipe, the 5th NMOS pipe all connects the drain electrode of the 4th NMOS pipe, and the source electrode of the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe all connects ground, the grid of the 6th NMOS pipe, the 7th NMOS pipe all connects the drain electrode of the 6th NMOS pipe, and the drain electrode of the 6th NMOS pipe is connected with the drain electrode of the 6th PMOS pipe, the grid of the 8th NMOS pipe connects the output of comparator, and drain electrode connects the drain electrode of the 7th NMOS pipe and the input in the same way of comparator and as the sawtooth waveforms output of current-limiting protection circuit, source electrode connects ground, one end of electric capacity connects the drain electrode of the 7th NMOS pipe, and the other end connects ground, the reverse input end of comparator connects the 3rd outside reference voltage, and output is as the square wave output of current-limiting protection circuit.
The DC-DC transducer that the invention allows for a kind of integrated above-mentioned current-limiting protection circuit, also comprises: adjust pipe, an inductance, a diode, current sampling circuit, feedback network, error amplifier, PWM comparator, voltage adder, rest-set flip-flop, wherein, the drain electrode of adjusting pipe connects an input of current sampling circuit, and source electrode connects diode cathode, and grid connects the output Q end of rest-set flip-flop; The another one input of sample circuit connects outside second source, and output connects an input of voltage adder; Another input of voltage adder connects the sawtooth waveforms output of current-limiting protection circuit, and the output of voltage adder connects the input in the same way of PWM comparator; The reverse input end of PWM comparator connects the output of error amplifier and the voltage clamping output of current-limiting protection circuit, and the output of PWM comparator connects the R input of rest-set flip-flop; The S input of rest-set flip-flop connects the square wave output of current-limiting protection circuit; The input terminal of current-limiting protection circuit connects the output of feedback network and the reverse input end of error amplifier; The input in the same way of error amplifier connects the 4th outside reference voltage; The input of feedback network is connected with one end of inductance and as the output of DC-DC transducer; The other end of inductance is connected to the negative pole of diode, the plus earth of diode.
Beneficial effect of the present invention: the current-limiting protection circuit that the present invention proposes, compare with existing protective circuit of switch power source, under slight overload situations, output voltage by current-limiting protection circuit departure amplifier is no more than predeterminated voltage value, thereby PWM comparator can normally be controlled, adjust pipe opening and closing, then limit the peak value of inductive current; In severe overload or output short-circuit situation; by current-limiting protection circuit, increase oscillator output square wave and slope compensation sawtooth period weakens the negative effect that transmission delay causes; thereby effectively prevented that large current tail from producing; protected under transducer what malfunction in office and can not be damaged; and because the output frequency of current-limiting protection circuit is linear change; in start-up course, can not produce state locking phenomena, transducer can be worked.
Accompanying drawing explanation
The existing BUCK circuit topological structure of Fig. 1 figure.
Fig. 2 current-limiting protection circuit schematic diagram of the present invention.
The middle comparator schematic diagram of the current-limiting protection circuit of Fig. 3 embodiment of the present invention.
The BUCK circuit topological structure figure of Fig. 4 embodiment of the present invention.
The Boost circuit topological structure figure of Fig. 5 embodiment of the present invention.
In Fig. 6 the present invention, current-limiting protection circuit output frequency is with input voltage V
fBthe simulation waveform curve chart changing.
Each parameters simulation oscillogram that Fig. 7 increases in time gradually without the BUCK adjuster output overloading of current-limiting protection circuit.
Each parameters simulation oscillogram that Fig. 8 increases in time gradually with the BUCK adjuster output overloading of current-limiting protection circuit.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the invention will be further elaborated.
The problem existing for existing DC-DC transducer Limited Current peak value; the present invention proposes a kind of current-limiting protection circuit for DC-DC transducer; specifically as shown in Figure 2, comprise 6 PMOS pipes MP1, MP2, MP3, MP4, MP5, MP6 and 8 NMOS pipe MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and capacitor C 1 and comparator C OMP.Wherein, the grid of PMOS pipe MP1, MP2 all connects the drain electrode of MP1 pipe, and drain electrode connects respectively the drain electrode of MN1, MN2 pipe, and the source electrode of MP1 connects respectively the first outside reference voltage V
bIAS, the source electrode of MP2 is as the voltage clamping output of current-limiting protection circuit; The grid of NMOS pipe MN1, MN2 all connects the first outside bias voltage V
b1, the grid of NMOS pipe MN3 connects the drain electrode of MN2 and MP2, and drain electrode connects the source electrode of MP2, and source electrode connects ground V
sS.The grid of PMOS pipe MP3, MP4 all connects the second outside bias voltage V
b2, the drain electrode of transistor MP3 connects the source electrode of MP5 and MP6, and the drain electrode of transistor MP4 connects the drain electrode of MN7, and transistor MP3, MP4 source electrode all connect the first power supply V
dD; The grid of PMOS pipe MP5 connects respectively the second outside reference voltage V
07, MP6 grid as the input terminal of current-limiting protection circuit, drain electrode connects respectively the drain electrode of MN4, MN5, source electrode all connects respectively the drain electrode of MP3; The grid of NMOS pipe MN4, MN5 all connects the drain electrode of MN4, and drain electrode connects respectively the drain electrode of MP5, MP6, and source electrode all connects ground V
sS; The grid of NMOS pipe MN6, MN7 all connects the drain electrode of MN6, and the drain electrode of MN6 is connected with the drain electrode of MP6 and MN5, and the drain electrode of MN7 is connected with the drain electrode of MP4, and the source electrode of MN6, MN7 all connects ground V
sS; The grid of NMOS pipe MN8 connects the output of comparator C OMP, and drain electrode connects the drain electrode of MN7 and the input in the same way of comparator, and source electrode connects ground V
sS; The forward end of capacitor C 1 connects the NMOS pipe drain electrode of MN7 and the input in the same way of comparator, and backward end connects ground V
sS; The end in the same way of comparator C OMP connects the drain electrode of NMOS pipe MN7 and MN8 and as the sawtooth waveforms output OSCb of current-limiting protection circuit, one end of capacitor C 1 connects the drain electrode of NMOS pipe MN7, and the other end connects ground; The reverse input end of comparator connects the 3rd outside reference voltage V
22, output is as the square wave output OSCa of current-limiting protection circuit.
Comparator C OMP in above-mentioned current-limiting protection circuit can adopt following a kind of execution mode, specifically as shown in Figure 3, comprises three PMOS pipes MP7, MP8, MP9 and six NMOS pipe MN9, MN10, MP11, MN12, MN13, MN14 and inverter INV.Wherein, the grid of PMOS pipe MP7, MP8 all connects the drain electrode of MP7, and drain electrode connects respectively the drain electrode of MN9, MN10, and source electrode all connects the first outside power supply V
dD; The grid of PMOS pipe MP9 connects MP8 and the drain electrode of MN10 and the grid of MN13, and drain electrode connects the drain electrode of MN13 and the input of inverter INV, and source electrode connects the first power supply V
dD; The grid difference of NMOS pipe MN9, MN10 is the V of input in the same way of device COMP as a comparison
iNP, reverse input end V
iNN, drain electrode connects respectively the drain electrode of MP7, MP8, and source electrode all connects the drain electrode of MN11; The drain electrode of NMOS pipe MN11 source electrode and MN12 is connected, and the grid of MN11 and MN12 is all connected the 3rd bias voltage V
b3, the drain electrode of MN11 connects the source electrode of MN9 and MN10, and the source electrode of MN12 connects ground V
sS; The grid of NMOS pipe MN13 connects the grid of MP9 and the drain electrode of MP8 and MN10, and drain electrode connects drain electrode and the inverter INV input of MP9, and source electrode connects the drain and gate of MN14; The grid of NMOS pipe MN14 is all connected the source electrode of MN13 with draining, and the source electrode of MN14 connects ground V
sS; The input of inverter INV connects the drain electrode of MP9 and MN13, and output is the lead-out terminal of device as a comparison.
Here, transistor MP1, MP2, MN1, MN2, MN3 form one-level current-limiting protection circuit, for clamped V
cOMPvoltage is not higher than predeterminated voltage V
bIAS; PMOS pipe MP3, MP4, MP5, MP6 and NMOS pipe MN4, MN5, MN6, MN7, MN8 and capacitor C 1, comparator C OMP form secondary current-limiting protection circuit, control the frequency of clock for changing output.
The operation principle of the present embodiment current-limiting protection circuit and effect for convenience of explanation, the BUCK circuit of take is below specifically described as example.
As shown in Figure 4, comprising: adjust pipe M0, an inductance L, a diode D1, current sampling circuit, feedback network, error amplifier, PWM comparator, voltage adder, rest-set flip-flop and current-limiting protection circuit, wherein, the drain electrode of adjusting pipe M0 connects an input of current sampling circuit, and source electrode connects diode cathode, and grid connects the output Q end of rest-set flip-flop; The another one input of sample circuit connects outside second source V
iN, output connects an input of voltage adder; Another input of voltage adder connects the sawtooth waveforms output OSCb of current-limiting protection circuit, and the output of voltage adder connects the input in the same way of PWM comparator; The reverse input end of PWM comparator connects the output of error amplifier and the output of current-limiting protection circuit, and the output of PWM comparator connects the R input of rest-set flip-flop; The S input of rest-set flip-flop connects current-limiting protection circuit square wave output OSCa; The input terminal of current-limiting protection circuit connects the output V of feedback network
fBand the reverse input end of error amplifier; The input in the same way of error amplifier connects the 4th outside reference voltage V
ref; The input of feedback network is connected with one end of inductance L and as the output end vo ut of DC-DC transducer; The other end of inductance L is connected to the negative pole of diode D1, the plus earth of diode D1.
It should be noted that: the first power supply V in low pressure applications
dDwith outside second source V
iNidentical, in high-voltage applications, V
dDand V
iNdifference, V
dDbe less than V
iN, general V
dDcan be by V
iNby inner LDO, produce.
V in one-level current-limiting protection circuit
bIASfor preset reference voltage, be used for determining error amplifier output V
compclamped voltage.This module is that the output voltage for clamped error amplifier is no more than predeterminated voltage value V
bIASthereby, can under slight overload situations, make the opening and closing of the normal power ratio control pipe of PWM comparator M0, guarantee that the current peak of inductance L can not surpass predetermined value, reach the object of protection transducer.
The voltage clamping principle of this circuit is as follows: due to the drain current I of transistor MN1
1drain current I with transistor MN2 pipe
2equate, so the poor V of gate source voltage of PMOS pipe MP1 and MP2
gsequate, work as V
compvoltage is less than V
bIAStime, PMOS pipe MP2 is turned off, but under slight overload, output voltage declines, V
compby loop adjustment meeting, along with rising, work as V
compmagnitude of voltage increases to and is greater than V
bIAStime, PMOS pipe MP2 opens, now V
compvoltage is arrived and predeterminated voltage V by clamped
bIASequate.And transistor MN3, MP2 and MN2 form a super source follower, thereby reduce output resistance, than W/L and the electric current I of passing through to increase source follower
2reduce the method for output resistance, saving chip area, has reduced cost.
When adjusting the increase of pipe M0 current spike, the voltage V sampling by current sampling circuit
sENSEreduce, if adjustment tube current spike increases to, make sampled voltage V
sENSEbe reduced to lower than clamped voltage V
comp, the output of PWM comparator will produce R that a low level is input to rest-set flip-flop and bring in to control and adjust closing of pipe M0, therefore uses one-level current-limiting protection circuit can realize the object that limits periodic current spike under slight overload situations.
The input in the same way of the differential pair of secondary current-limiting protection circuit is inputted the second reference voltage V
07for 0.7V reference voltage, the reverse input end of comparator the 3rd reference voltage V
22for 2.2V reference voltage.This secondary current-limiting protection circuit forms a concussion cycle with transducer feedback network output voltage V
fBthe oscillator changing.Under severe overload situations, output current continues to increase, particularly in output short-circuit situation, this module weakens the impact of transmission delay on inductive current peak by increasing the oscillator output cycle, makes the inductive current peak can be not excessive, thereby avoids the damage of transducer.
The V of input terminal voltage in the same way of comparator while starting working
pduring lower than 2.2V, differential amplifier is to capacitor C 1 charging, C1 voltage V
pcan, along with increase, work as V
pwhen voltage is greater than 2.2V, comparator output high level makes NMOS pipe MN8 conducting, thereby capacitor C 1 is discharged by transistor MN8, because the repid discharge characteristic of transistor MN8 switch, so can ignore comparator output low level subsequently discharge time, start the process of next cycle to capacitor C 1 charging, thereby the output at comparator produces square wave, and the input in the same way of comparator produces sawtooth waveforms, and their cycle is specially:
Under normal condition or slight overload situations, V
fBvoltage ratio is larger, is greater than the grid voltage V of transistor MP3
07so the drain current of tail current source MP3 almost all flow into transistor MP5, so the drain current I of MN7
fREQbe almost 0, now the frequency of oscillator is maximum, at this design peak frequency, is 340KHz.
Along with the increase of transducer load, V
fBvoltage reduces, as 0.5V < V
fBduring < 0.7V, can obtain:
i
MP6＝g
MP6v
ID/2
i
MP5＝-g
MP5v
ID/2
v
ID＝v
07-v
FB g
MP5＝g
MP6＝g
m
I
FREQ＝i
MP6-i
MP5＝(g
MP6+g
MP5)v
ID/2＝g
mv
ID
Wherein, g
mrepresent the mutual conductance of transistor MP5 and MP6.
Joint line resistant frequency foldback circuit frequency formula can see, the frequency of oscillator is linear change within the scope of this feedback voltage.
If feedback voltage continues to reduce, work as V
fBvoltage is during lower than 0.5V, and the drain current of differential-pair tail current source MP3 is no better than the drain current of transistor MP4, thus I
fREQbe approximately equal to the drain current of differential-pair tail current source MP3, from the frequency formula of oscillator, can obtain, now frequency is minimum, is set to 110KHz here.
From upper surface analysis, can obtain; current-limiting protection circuit output frequency changes along with the variation of transducer resistance-feedback network output voltage; in severe overload or output short-circuit situation, frequency of oscillation linearity reduces; thereby weakened the negative effect that the propagation delay time causes; reduce inductive current peak; and because the process that reduces of frequency of oscillation is linearizing, thus startup stage there will not be state locking phenomena, guaranteed the normal operation of Switching Power Supply.
Without secondary current-limiting protection circuit and with each parameters simulation waveform of secondary current-limiting protection circuit as shown in Figure 7 and Figure 8, therefrom can see, under slight overload situations, comparator output terminal V
cOMPvoltage is clamped below 2V by one-level current-limiting protection circuit, and inductive current peak is 4.5A left and right; Under severe overload situations, V
cOMPvoltage is all clamped to 2V by one-level current-limiting protection circuit; the inductive current peak of the BUCK adjuster of integrated secondary current-limiting protection circuit is smaller; by secondary current-limiting protection circuit, be limited in below 5.2A; the inductive current peak with the BUCK adjuster of secondary current-limiting protection circuit does not reach 16A; and along with the increase of time, its value is still rising.In addition, from current-limiting protection circuit output frequency with input voltage V
fBin the simulation waveform curve chart 6 changing, can see, along with reducing of transducer resistance feedback voltage, current-limiting protection circuit output frequency linearity reduces, thereby can not cause the generation of state locking phenomena in start-up course.
The present invention can be used in other DC-DC transducers, such as Boost circuit.As shown in Figure 5, Boost circuit structure, principle and BUCK circuit are similar, are no longer specifically described for Boost circuit topological structure figure.
In summary it can be seen, the current-limiting protection circuit that the present invention proposes, what make can protect transducer not damaged under Switching Power Supply fault state in office, this current-limiting protection circuit is by the clamped technology of use error amplifier output voltage and linear frequency foldback technique, make Switching Power Supply under slight overload situations, by the clamped mode of output voltage error amplifier, come departure amplifier output voltage to be no more than predeterminated voltage value, thereby the output valve of Limited Current sample circuit, make PWM comparator can control normally the opening and closing of adjusting pipe, then limit inductive current peak, and the in the situation that of severe overload or output short-circuit, by increasing cycle oscillator, weaken the negative effect that transmission delay causes, and then solved existing transducer larger hangover current phenomena of causing in overload or output short-circuit situation, effectively controlled under transducer what malfunction in office, output current can be not excessive, avoided the damage of transducer, and because the output frequency of current-limiting protection circuit is linear change, in start-up course, can not produce state locking phenomena, transducer can be worked.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not depart from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (1)
1. a DC-DC transducer, is characterized in that, comprising: current-limiting protection circuit, adjustment pipe, and an inductance, a diode, current sampling circuit, feedback network, error amplifier, PWM comparator, voltage adder, rest-set flip-flop, wherein,
Described current-limiting protection circuit, comprise: a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe and an electric capacity and a comparator, concrete annexation is: a PMOS pipe, the grid of the 2nd PMOS pipe all connects the drain electrode of a PMOS pipe, drain electrode connects respectively a NMOS pipe, the drain electrode of the 2nd NMOS pipe, the source electrode of the one PMOS pipe connects the first outside reference voltage, the source electrode of the 2nd PMOS pipe is as the voltage clamping output of current-limiting protection circuit, the grid of the one NMOS pipe, the 2nd NMOS pipe all connects the first outside bias voltage, and source electrode all connects ground, the grid of the 3rd NMOS pipe connects the drain electrode of the 2nd NMOS pipe, and drain electrode connects the source electrode of the 2nd PMOS pipe, and source electrode connects ground, the grid of the 3rd PMOS pipe, the 4th PMOS pipe all connects the second outside bias voltage, the drain electrode of the 3rd PMOS pipe connects the source electrode of the 5th PMOS pipe and the 6th PMOS pipe, the drain electrode of the 4th PMOS pipe connects the drain electrode of the 7th NMOS pipe, and the source electrode of the 3rd PMOS pipe, the 4th PMOS pipe all connects the first power supply, the grid of the 5th PMOS pipe connects the grid of the second outside reference voltage, the 6th PMOS pipe as the input terminal of current-limiting protection circuit, and the drain electrode of the 5th PMOS pipe, the 6th PMOS pipe connects respectively the drain electrode of the 4th NMOS pipe, the 5th NMOS pipe, the grid of the 4th NMOS pipe, the 5th NMOS pipe all connects the drain electrode of the 4th NMOS pipe, and the source electrode of the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe all connects ground, the grid of the 6th NMOS pipe, the 7th NMOS pipe all connects the drain electrode of the 6th NMOS pipe, and the drain electrode of the 6th NMOS pipe is connected with the drain electrode of the 6th PMOS pipe, the grid of the 8th NMOS pipe connects the output of comparator, and drain electrode connects the drain electrode of the 7th NMOS pipe and the input in the same way of comparator and as the sawtooth waveforms output of current-limiting protection circuit, source electrode connects ground, one end of electric capacity connects the drain electrode of the 7th NMOS pipe, and the other end connects ground, the reverse input end of comparator connects the 3rd outside reference voltage, and output is as the square wave output of current-limiting protection circuit,
The drain electrode of adjusting pipe connects an input of current sampling circuit, and source electrode connects diode cathode, and grid connects the output Q end of rest-set flip-flop; The another one input of sample circuit connects outside second source, and output connects an input of voltage adder; Another input of voltage adder connects the sawtooth waveforms output of current-limiting protection circuit, and the output of voltage adder connects the input in the same way of PWM comparator; The reverse input end of PWM comparator connects the output of error amplifier and the voltage clamping output of current-limiting protection circuit, and the output of PWM comparator connects the R input of rest-set flip-flop; The S input of rest-set flip-flop connects the square wave output of current-limiting protection circuit; The input terminal of current-limiting protection circuit connects the output of feedback network and the reverse input end of error amplifier; The input in the same way of error amplifier connects the 4th outside reference voltage; The input of feedback network is connected with one end of inductance and as the output of DC-DC transducer; The other end of inductance is connected to the negative pole of diode, the plus earth of diode.
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| CN201110393505.5A CN102420520B (en) | 2011-12-02 | 2011-12-02 | Current limiting protection circuit and direct current (DC)-DC converter integrated with current limiting protection circuit |
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| CN101061631A (en) * | 2004-09-28 | 2007-10-24 | 德克萨斯仪器股份有限公司 | Current limiting circuit for high-speed low-side driver outputs |
| GB2437556A (en) * | 2006-04-26 | 2007-10-31 | Wolfson Microelectronics Plc | Current mode switching regulator |
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2011
- 2011-12-02 CN CN201110393505.5A patent/CN102420520B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101061631A (en) * | 2004-09-28 | 2007-10-24 | 德克萨斯仪器股份有限公司 | Current limiting circuit for high-speed low-side driver outputs |
| GB2437556A (en) * | 2006-04-26 | 2007-10-31 | Wolfson Microelectronics Plc | Current mode switching regulator |
Non-Patent Citations (5)
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| Zekun Zhou.etc.A High-performance PWM controller with adjustable current limit.《ASIC，2011 IEEE 9th international conference》.2011,100-103. * |
| 一种具有过流保护功能的振荡器涉及;王慧芳等;《中国集成电路》;20111031(第149期);39-42 * |
| 一种应用于DC/DC转换器的高效PWM控制电路的设计;陈程等;《中国集成电路》;20110831(第147期);46-52 * |
| 王慧芳等.一种具有过流保护功能的振荡器涉及.《中国集成电路》.2011,(第149期),39-42. |
| 陈程等.一种应用于DC/DC转换器的高效PWM控制电路的设计.《中国集成电路》.2011,(第147期),46-52. |
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| Publication number | Publication date |
|---|---|
| CN102420520A (en) | 2012-04-18 |
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