CN117406660A - Data acquisition system based on FPGA and AD9280 - Google Patents

Abstract

The invention discloses a data acquisition system based on FPGA and AD9280, and relates to the technical field of data acquisition, and the system comprises: the device comprises a data acquisition module, a data frame conversion module and a level conversion module; the data frame conversion module provides a working clock for the data acquisition module; the data acquisition module acquires a signal to be acquired under a working clock and converts the signal to be acquired into a first digital signal; the data frame conversion module is also used for converting the first digital signal into a second digital signal according to the rs232 frame structure; the level conversion module converts TTL level of the second digital signal into rs232 level and sends the second digital signal after level conversion to the upper computer, so that the corresponding numerical value of the signal to be acquired is displayed. The invention omits complicated debugging and improves the universality.

Description

Data acquisition system based on FPGA and AD9280

Technical Field

The invention relates to the technical field of data acquisition, in particular to a data acquisition system based on FPGA and AD 9280.

Background

In various computing and control systems of industrial control, data acquisition and transmission are fundamental, so that an independent, self-organized and concise data acquisition system is built, and the system can be expanded and extended on the basis, so that other functions are realized, and the system development efficiency is improved.

Disclosure of Invention

The invention aims to provide a data acquisition system based on an FPGA and an AD9280, which omits complicated debugging, is easy to expand and can be conveniently applied to occasions needing data transmission and processing.

In order to achieve the above object, the present invention provides the following solutions:

a data acquisition system based on FPGA and AD9280, comprising: the device comprises a data acquisition module, a data frame conversion module and a level conversion module; the data output end of the data acquisition module is connected with the data input end of the data frame conversion module, the data output end of the data frame conversion module is connected with the data input end of the level conversion module, and the control output end of the data frame conversion module is connected with the control input end of the data acquisition module;

the data frame conversion module is used for providing a working clock for the data acquisition module;

the data acquisition module is used for acquiring a signal to be acquired under the working clock and converting the signal to be acquired into a first digital signal; the signal to be acquired is an analog signal, and the first digital signal is an 8-bit binary signal;

the data frame conversion module is further used for converting the first digital signal into a second digital signal according to an rs232 frame structure; the second digital signal is a 10-bit binary signal;

the level conversion module is used for converting the TTL level of the second digital signal into rs232 level and sending the second digital signal after level conversion to an upper computer so as to display the numerical value corresponding to the signal to be acquired.

Optionally, the data acquisition module includes: an analog-to-digital conversion sub-module;

the data output end of the analog-to-digital conversion sub-module is connected with the data input end of the data frame conversion module, and the control output end of the data frame conversion module is connected with the control input end of the analog-to-digital conversion sub-module;

the analog-to-digital conversion submodule is used for collecting the signal to be collected under the working clock and carrying out analog-to-digital conversion on the signal to be collected to obtain the first digital signal.

Optionally, the data acquisition module further includes: an attenuation sub-module; the attenuation submodule is integrated on the analog-digital conversion submodule;

the attenuation submodule is used for expanding the range of the analog-to-digital conversion submodule.

Optionally, the data frame conversion module is an FPGA chip.

Optionally, the analog-to-digital conversion sub-module is an AD9280 chip.

Optionally, the attenuation submodule is an operational amplifier AD8650.

Optionally, the FPGA chip includes: the system comprises a top layer module, a control module, a data acquisition module and a serial port sending module;

the top layer module is used for defining an input/output interface and instantiating the control module, the data acquisition module and the serial port sending module;

the control module is used for providing the working clock for the data acquisition module;

the data acquisition module is used for acquiring the first digital signal and converting the first digital signal into the second digital signal according to an rs232 frame structure;

the serial port transmitting module is used for converting the second digital signal into a serial data form and transmitting the serial data to the level converting module.

Optionally, the level conversion module is an SP3232 chip.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention discloses a data acquisition system based on FPGA and AD9280, which comprises: the device comprises a data acquisition module, a data frame conversion module and a level conversion module; the data output end of the data acquisition module is connected with the data input end of the data frame conversion module, the data output end of the data frame conversion module is connected with the data input end of the level conversion module, and the control output end of the data frame conversion module is connected with the control input end of the data acquisition module; the data frame conversion module provides a working clock for the data acquisition module; the data acquisition module acquires a signal to be acquired under a working clock and converts the signal to be acquired into a first digital signal; the data frame conversion module is also used for converting the first digital signal into a second digital signal according to the rs232 frame structure; the level conversion module converts TTL level of the second digital signal into rs232 level and sends the second digital signal after level conversion to the upper computer, so that the corresponding numerical value of the signal to be acquired is displayed. The invention omits complicated debugging, is easy to expand, can be conveniently applied to occasions needing data transmission and processing, and improves the universality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a data acquisition system based on FPGA and AD9280 provided in embodiment 1 of the present invention;

FIG. 2 is a block diagram of the overall system design;

FIG. 3 is a block diagram of an AD9280 chip;

FIG. 4 is a timing diagram of the operation of the AD9280 chip;

FIG. 5 is a rtl view of an FPGA;

FIG. 6 is a diagram of an rs232 data frame structure;

FIG. 7 is an electrical diagram of SP3232 operation;

fig. 8 is a diagram of an upper computer data acquisition interface when the measured value is 3.220V.

Symbol description:

the system comprises a data acquisition module-1, a data frame conversion module-2, a level conversion module-3 and an upper computer-4.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention aims to provide a data acquisition system based on an FPGA and an AD9280, which aims to omit complicated debugging and improve universality.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Example 1

Fig. 1 is a schematic structural diagram of a data acquisition system based on FPGA and AD9280 according to embodiment 1 of the present invention. As shown in fig. 1, the data acquisition system based on FPGA and AD9280 in this embodiment includes: the device comprises a data acquisition module 1, a data frame conversion module 2 and a level conversion module 3; the data output end of the data acquisition module 1 is connected with the data input end of the data frame conversion module 2, the data output end of the data frame conversion module 2 is connected with the data input end of the level conversion module 3, and the control output end of the data frame conversion module 2 is connected with the control input end of the data acquisition module 1.

The data frame conversion module 2 is used for providing an operating clock for the data acquisition module 1.

The data acquisition module 1 is used for acquiring a signal to be acquired under a working clock and converting the signal to be acquired into a first digital signal; the signal to be acquired is an analog signal, and the first digital signal is an 8-bit binary signal.

The data frame conversion module 2 is further configured to convert the first digital signal into a second digital signal according to an rs232 frame structure; the second digital signal is a 10-bit binary signal.

The level conversion module 3 is configured to convert the TTL level of the second digital signal into rs232 level, and send the second digital signal after level conversion to the upper computer 4, so as to display a numerical value corresponding to the signal to be acquired.

As an alternative embodiment, the data acquisition module 1 comprises: and an analog-to-digital conversion sub-module.

The data output end of the analog-to-digital conversion sub-module is connected with the data input end of the data frame conversion module 2, and the control output end of the data frame conversion module 2 is connected with the control input end of the analog-to-digital conversion sub-module.

The analog-to-digital conversion sub-module is used for collecting signals to be collected under the working clock and carrying out analog-to-digital conversion on the signals to be collected to obtain first digital signals.

As an alternative embodiment, the data acquisition module 1 further comprises: an attenuation sub-module; the attenuation submodule is integrated on the analog-to-digital conversion submodule.

The attenuation submodule is used for expanding the range of the analog-digital conversion submodule.

As an alternative embodiment, the data frame conversion module 2 is an FPGA chip.

As an alternative embodiment, the analog-to-digital conversion sub-module is an AD9280 chip.

As an alternative embodiment, the attenuation submodule is an op amp AD8650.

As an alternative embodiment, the FPGA chip includes: the device comprises a top layer module, a control module, a data acquisition module and a serial port sending module.

The top layer module is used for defining an input/output interface, and instantiating a control module, a data acquisition module and a serial port sending module.

The control module is used for providing an operating clock for the data acquisition module 1.

The data acquisition module is used for acquiring a first digital signal and converting the first digital signal into a second digital signal according to an rs232 frame structure.

The serial port transmitting module is used for converting the second digital signal into a serial data form and transmitting the serial data form to the level converting module 3.

As an alternative embodiment, the level conversion module 3 is an SP3232 chip.

The system provided by the invention is illustrated in terms of both hardware and software, and the overall system design block diagram shown in fig. 2 is described in terms of signal flow in 4 parts.

1. Analog-to-digital conversion circuit scheme

1.1 attenuation Circuit (attenuator Module)

In order to improve the expansibility of the system, a modularized AD (namely, a data acquisition module 1) is adopted, an attenuation circuit (namely, an attenuation submodule) is integrated on the data acquisition module 1 besides the AD9280, the attenuation circuit is formed by an operational amplifier AD8650 and is used for expanding the range of the AD9280, and when the analog signals to be detected of-5V to +5V are acquired, the conversion formula from the input signals to the AD8650 is as follows: vad=vin×1/5+1, when an input signal (i.e., analog signal to be measured) vin=5v, a signal vad=2v input to AD 8650; when the input signal vin= -5V, the signal vad=0v input to the AD8650 can meet the input requirement that the input terminal of the AD9280 is 0-2V.

1.2 analog-to-digital conversion sub-module

The AD9280 chip is a single channel, an analog-to-digital conversion chip with 8-bit resolution, which is proposed by AD (Analog Devices) company, the normal conversion rate can reach 32MSPS (Million Samples Per Second, sampling millions per second), and the sampling rate can reach 135MHz under the condition of undersampling. A block diagram of an AD9280 chip is shown in fig. 3. The ports used in the normal mode are a clock input port CLK, an analog signal input port VINA, and 8-bit parallel output ports D7-D0.

The AD9280 chip is easy to use, no internal register is needed to be configured, the working clock is provided by the FPGA, and when the clock signal is lower than 32MHz, the output port [ D7 ] is output after the delay of 25ns is added in three clock cycles: d0] has data output, and the working sequence is shown in fig. 4.

2. FPGA internal circuit design scheme

The FPGA used in the system is a Cyclone II chip of ALTERA company, which has 68416 logic units (LE), provides 138 available input/output pins and 1.1 Mbit embedded registers, and adopts 50MHz crystal oscillator as driving clock. The Cyclone II series has a wide application space due to high performance and low power consumption despite a long push-out time.

The FPGA function mainly provides a proper working clock for the AD9280 chip, acquires data of the AD9280 and sends the data to the upper computer in a protocol form of rs232, and is mainly realized by 4 internal modules, namely a top module ad_fpga, three sub-modules ad_ctrl (AD control module), ad_acq (AD data acquisition module) and uart_tx (serial port sending module). A view rtl is shown in fig. 5. IN the top module ad_fpga, sys_clk is a system clock provided by a 50M crystal oscillator, sys_rst_n is a reset signal, IN [7:0] is an output signal of the AD9280, ad_clk is a system clock provided to the AD9280 after the FPGA divides the system clock, and tx is a serial output; the ad_acq is a data acquisition module, and has the function of outputting an rx_flag output data flag signal every 55000 clock cycles and outputting 8-bit wide parallel data rx_data [7:0]; uart_tx is a serial port transmit module that converts parallel input data into serial data output, pi_flag is an input flag signal, and pi_data [7:0] is input data.

2.1 Top-level Module ad_fpga

The top layer module ad_fpga mainly defines input/output interfaces, and instantiates three sub-modules, namely ad_ctrl, ad_acq and uart_tx.

2.2ad control Module ad_ctrl

The AD9280 is easy to use, an internal register is not required to be configured, the AD9280 can normally work when the clock signal is lower than 32MHz, and the AD_ctrl module obtains a 12.5M clock signal to drive the AD9280 to work after dividing the system clock by 4.

2.3 data acquisition Module ad_acq

The ad_acq module has two functions: 1. collecting an output signal of the AD 9280; 2. and outputting the acquired signals to a uart_tx module.

2.3.1 As can be seen from FIG. 4, the output signal of AD9280 is not synchronized with the system clock sys_clk, so direct sampling can cause erroneous sampling due to metastability, three register variables rx_reg1, rx_reg2, rx_reg3 are defined inside the ad_acq module to input signal IN [7: and 0 is output after three beats are made, so that the clock can be synchronized with the system clock, and when IN [7:0] when the output result is 8' hDA, the rx_reg1 beats one beat on the basis, the clock period is delayed, the rx_reg2 beats one beat on the basis of the rx_reg1, and the rx_reg3 beats one beat on the basis of the rx_reg2, so that the accuracy and reliability of the acquired data are ensured.

2.3.2 in the present invention, a simple method of generating rs232 data frames is employed. Since the protocol format of rs232 is known, each frame of data is composed of 10 bits, the 1 st bit is a low level start bit, the 2 nd to 9 th bits are data bits, and the 10 th bit is a stop bit, and is represented by a high level. The rs232 data frame structure is shown in fig. 6.

In the system of the invention, 10 bits of data are output at 9600 baud rate, the duration of each 1 bit of data is 5208 clock cycles (50000000/9600=5208) under the 50M system clock, a high level rx_flag of a clock is generated at the beginning of each 1 bit and is used as a flag signal of the bit of data, and meanwhile, the value of rx_reg3 is assigned to rx_data, the output of the ten bits of data takes 52080 (5208×10= 52080) clock cycles, a 55000 counter baud_cnt is defined in the ad_acq, an acquired 8 bits of data and a flag signal are transmitted to the uart_tx module every 55000 clock cycles, and the rest work is completed by the uart_tx, so that the uart_tx module can ensure that the last received data is sent to an upper computer during each transmission.

2.4 serial port transmitting Module uart_tx

The uart_tx module converts parallel data sent by the ad_acq module into serial data, the serial data is sent to an upper computer in an rs232 format 9600 baud rate, the core function is to convert the parallel data into the serial data, the function is mainly realized through a bit counter bit_cnt from 0 to 9, when the bit_cnt is equal to 1 to 8, the current bit is sent out every 5208 clock cycles, and then the bit_cnt is added with 1.

3. Level shifting scheme

The TTL level output by the FPGA is different from the standard of rs 232. The TTL circuit operates at 5V and its output may be either high (3.6V) or low (0.3V). RS232 adopts a negative logic level, i.e., -15V to-3V represent logic "1", and +3v to +15v represent logic "0". The level here is the voltage of the signal line with respect to Ground (GND), so the output result of the FPGA cannot be directly transmitted to the PC host computer for display, and level conversion is necessary to ensure consistency of the data logic. The SP3232 chip is used for level conversion, the SP3232 operation electrical diagram is shown in fig. 7, when the SP3232 operation electrical diagram is output outwards, the LOGIC INPUTS interface is connected with TTL level input, the RS-232OUTPUTS is an output interface, and the SP3232 operation electrical diagram is connected with an upper computer through an RS-232 cable.

4. Design scheme of upper computer

The upper computer program is written in the Visual Studio environment by C# and adopts a Windows window application (. NET FRAMEWORK) template, and mainly uses a Label (Label), a Button (Button), a comboBox (comboBox), a serial port component (SerialPort), a Panel (Panel), a radio Button (radio Button) and a text box (TextBox) in a toolbox to form the upper computer.

In order to improve usability of the upper computer, a default value is set in the window loading function, so that the condition that the upper computer is set every time is avoided.

To verify the system in example 1, a test was performed. The analog signal of the test is provided by an LM 2596S-ADJ adjustable voltage-reducing and stabilizing module, the input voltage range of the module is 3.2-40V, and the output voltage range is 1.25-35V, so that the experimental requirement can be met. The experimental contrast measuring instrument is a Fluke 101 type universal meter, the accuracy of measuring direct current voltage is 0.5%, and the resolution ratio is 0.001V when the measuring range is 6V.

The calculation formula for conversion from the input analog voltage V to the hexadecimal theoretical value R is: r= (V/5+1)/2×256.

When the input voltage is 3.220V, the input voltage is obtained 210 according to a conversion formula, is converted into hexadecimal D2, and accords with the received data 0xD2 of the upper computer. The upper computer data is shown in fig. 8.

The working principle of the system in the invention comprises the following steps:

step 1: after the analog signal to be tested enters the system, the AD9280 module performs sampling conversion, and the converted result is output to the FPGA in parallel in an 8-bit binary form.

Step 2: the FPGA acquires the data of the AD9280 and transmits the data to the level conversion chip SP3232 in the form of rs232 protocol.

The FPGA is internally composed of 4 modules, namely a top layer module ad_fpga, three sub-modules ad_ctrl (ad control module), ad_acq (ad data acquisition module) and uart_tx (serial port sending module). The ad_acq module sends 8-bit parallel data to a serial port sending module uart_tx in the FPGA according to the sequence of 9600 baud rate according to an rs232 frame structure (1-bit start bit, 8-bit data bit and 1-bit stop bit), and the uart_tx module converts the parallel data into serial data and sends the serial data to the SP3232.

Step 3: the SP3232 chip converts TTL level to rs232 level.

Step 4: and displaying the result by an upper computer running on the PC.

The system in the invention does not need complex configuration, from hardware to software, all parameters are properly configured, and correct results can be obtained only by running, so that complicated debugging is omitted, the system is easy to expand, can be conveniently applied to occasions needing data transmission and processing, and provides a convenient and easy-to-use template for engineering technicians.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the system of the present invention and its core ideas; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.

Claims (8)

1. A data acquisition system based on FPGA and AD9280, the system comprising: the device comprises a data acquisition module, a data frame conversion module and a level conversion module; the data output end of the data acquisition module is connected with the data input end of the data frame conversion module, the data output end of the data frame conversion module is connected with the data input end of the level conversion module, and the control output end of the data frame conversion module is connected with the control input end of the data acquisition module;

the data frame conversion module is used for providing a working clock for the data acquisition module;

the data acquisition module is used for acquiring a signal to be acquired under the working clock and converting the signal to be acquired into a first digital signal; the signal to be acquired is an analog signal, and the first digital signal is an 8-bit binary signal;

the data frame conversion module is further used for converting the first digital signal into a second digital signal according to an rs232 frame structure; the second digital signal is a 10-bit binary signal;

the level conversion module is used for converting the TTL level of the second digital signal into rs232 level and sending the second digital signal after level conversion to an upper computer so as to display the numerical value corresponding to the signal to be acquired.

2. The FPGA and AD9280 based data acquisition system of claim 1, wherein the data acquisition module comprises: an analog-to-digital conversion sub-module;

the data output end of the analog-to-digital conversion sub-module is connected with the data input end of the data frame conversion module, and the control output end of the data frame conversion module is connected with the control input end of the analog-to-digital conversion sub-module;

the analog-to-digital conversion submodule is used for collecting the signal to be collected under the working clock and carrying out analog-to-digital conversion on the signal to be collected to obtain the first digital signal.

3. The FPGA and AD9280 based data acquisition system of claim 2, wherein the data acquisition module further comprises: an attenuation sub-module; the attenuation submodule is integrated on the analog-digital conversion submodule;

the attenuation submodule is used for expanding the range of the analog-to-digital conversion submodule.

4. The data acquisition system based on FPGA and AD9280 of claim 1, wherein the data frame conversion module is an FPGA chip.

5. The data acquisition system based on FPGA and AD9280 of claim 2, wherein the analog to digital conversion sub-module is an AD9280 chip.

6. The data acquisition system based on FPGA and AD9280 of claim 3, wherein the attenuation submodule is an op amp AD8650.

7. The FPGA and AD9280 based data acquisition system of claim 4, wherein the FPGA chip comprises: the system comprises a top layer module, a control module, a data acquisition module and a serial port sending module;

the top layer module is used for defining an input/output interface and instantiating the control module, the data acquisition module and the serial port sending module;

the control module is used for providing the working clock for the data acquisition module;

the data acquisition module is used for acquiring the first digital signal and converting the first digital signal into the second digital signal according to an rs232 frame structure;

the serial port transmitting module is used for converting the second digital signal into a serial data form and transmitting the serial data to the level converting module.

8. The FPGA and AD9280 based data acquisition system of claim 7, wherein the level conversion module is an SP3232 chip.