CN211787076U

CN211787076U - Multi-protocol analyzer based on FPGA

Info

Publication number: CN211787076U
Application number: CN202020684831.6U
Authority: CN
Inventors: 陆帅帅
Original assignee: CIG Shanghai Co Ltd
Current assignee: CIG Shanghai Co Ltd
Priority date: 2020-04-28
Filing date: 2020-04-28
Publication date: 2020-10-27
Anticipated expiration: 2030-04-28

Abstract

The utility model discloses a multi-protocol analyzer based on FPGA, include: the system comprises an FPGA, a low-speed connector, a high-speed connector, a switch, a buffer, a PC and a DDR; the low-speed connector is switchably connected to one end of the buffer or a first I/O port of the FPGA through the switch, the other end of the buffer is connected to a second I/O port of the FPGA, the high-speed connector is connected to a third I/O port of the FPGA, the FPGA is connected with the PC through a USB interface, and the FPGA is connected with the DDR; the low-speed connector and the high-speed connector are respectively used for receiving signals to be tested of different protocols. The acquisition and analysis functions of multiple protocols are integrated in one instrument, and data capture of signals of the multiple protocols is supported. Meanwhile, compared with a plurality of special protocol analyzers, the cost of the multi-protocol analyzer provided by the embodiment is greatly reduced.

Description

Multi-protocol analyzer based on FPGA

Technical Field

The utility model relates to a computer technology Field, in particular to multi-protocol analyzer based on FPGA (Field programmable gate Array).

Background

With the continuous enhancement of the functions of electronic devices, more and more peripheral interfaces are provided, and multiple communication protocols may be included in the same system. However, due to the requirements of system integration and size, the redundancy of the whole routing becomes smaller and smaller. If the corresponding routing is not processed during PCB design, the phenomena of abnormal communication and the like easily occur at the later stage. At this time, a corresponding Debug instrument, such as an oscilloscope, a protocol analyzer, or the like, is required. However, the storage depth and price of the oscilloscope, the single function of the protocol analyzer, the price and other factors often cause the limitation of the analysis means.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is to overcome above-mentioned defect among the prior art, provide a multiprotocol analyzer based on FPGA.

The utility model discloses a solve above-mentioned technical problem through following technical scheme:

an FPGA-based multi-protocol analyzer, comprising: FPGA, low speed connector, high speed connector, switch, buffer, PC (Personal Computer), and DDR (double data rate synchronous dynamic random access memory);

the low-speed connector is switchably connected to one end of the buffer or a first I/O port of the FPGA through the switch, the other end of the buffer is connected to a second I/O port of the FPGA, the high-speed connector is connected to a third I/O port of the FPGA, the FPGA is connected with the PC through a USB interface, and the FPGA is connected with the DDR;

the low-speed connector and the high-speed connector are respectively used for receiving signals to be tested of different protocols.

Preferably, the low-speed connector is configured to receive an I2C (Inter-Integrated Circuit) signal or an SPI (Serial Peripheral Interface) signal.

Preferably, the high-speed connector is configured to receive an LVDS (Low-Voltage Differential Signaling) signal.

Preferably, the FPGA is configured to output different control signals to the switch according to a voltage of a signal to be measured, so as to control the switch to be switchably connected to one end of the buffer or the first I/O port of the FPGA.

On the basis of the common knowledge in the field, the above preferred conditions can be combined at will to obtain the preferred embodiments of the present invention.

The utility model discloses an actively advance the effect and lie in: through setting up low-speed connector and high-speed connector to and the low-speed connector passes through the switch switchably is connected to the one end of buffer or FPGA's first IO mouth, the other end of buffer is connected to FPGA's second IO mouth, high-speed connector is connected to FPGA's third IO mouth, FPGA pass through the USB interface with the PC is connected, FPGA with the DDR is connected, has realized the collection analysis function of integrated multiple agreement in an instrument, supports the data of multiple agreement signal to snatch. Meanwhile, compared with a plurality of special protocol analyzers, the cost of the multi-protocol analyzer provided by the embodiment is greatly reduced.

Drawings

Fig. 1 is a block diagram of a multi-protocol analyzer based on FPGA according to an embodiment of the present invention.

Detailed Description

The present invention is further illustrated by way of the following examples, which are not intended to limit the scope of the invention.

The present embodiment provides a multi-protocol analyzer based on FPGA, as shown in fig. 1, including: FPGA, low speed connector, high speed connector, switch, buffer, PC and DDR.

The low-speed connector is connected to one end of the buffer or a first I/O port of the FPGA in a switchable mode through the switch, the other end of the buffer is connected to a second I/O port of the FPGA, the high-speed connector is connected to a third I/O port of the FPGA, the FPGA is connected with the PC through a USB interface, and the FPGA is connected with the DDR.

The low-speed connector and the high-speed connector are respectively used for receiving signals to be tested of different protocols. In specific implementation, a protocol corresponding to a received signal to be detected is determined through setting of a cap skip or a dial switch.

In this embodiment, the signal to be detected received by the low-speed connector is directly connected to the first I/O port of the FPGA, or is connected to the second I/O port of the FPGA through the buffer. And the first I/O port and the second I/O port of the FPGA are both low-speed I/O ports. For the signal to be measured which is not directly connected to the FPGA through the buffer, the voltage of the corresponding BANK needs to be adjusted before power-on, that is, the level of the first I/O port is configured to be consistent with the level of the signal to be measured. For the signal to be tested connected to the FPGA through the buffer, the signal to be tested may be connected to any low-speed I/O port of the FPGA, that is, the second I/O port may be a low-speed I/O port of any level. And the signal to be detected received by the high-speed connector is directly connected to a third I/O port of the FPGA, wherein the third I/O port of the FPGA is the high-speed I/O port.

Compared with the prior art, the embodiment utilizes the flexible programmable characteristic of the FPGA, realizes the collection and analysis functions of integrating multiple protocols in one instrument, and supports the data capture of multiple protocol signals. Meanwhile, compared with a plurality of special protocol analyzers, the cost of the multi-protocol analyzer provided by the embodiment is greatly reduced.

The FPGA receives the signal to be detected, then carries out sampling analysis processing on the signal to be detected, stores the signal to be detected in the DDR, and then sends the signal to the PC through the USB interface, and the PC is used for displaying the captured data. In specific implementation, DDR with different capacities can be configured according to the requirement of data capture length, and flexibility and convenience are achieved.

In an alternative embodiment, the low speed connector is configured to receive either the I2C signal or the SPI signal.

In an alternative embodiment, the high-speed connector is configured to receive LVDS signals. LVDS is a low-amplitude differential signaling technique that uses very low-amplitude signals (about 350mV) to transmit data through a pair of differential PCB traces or balanced cables, which can carry serial data at speeds up to thousands of Mbps.

In an alternative embodiment, the user may manually control the switch according to a known signal to be tested, so that the signal to be tested is directly connected to the FPGA, or the signal to be tested is connected to the FPGA through the buffer.

In an alternative embodiment, the switch is automatically controlled by an FPGA. Specifically, the FPGA is configured to output different control signals to the switch according to a voltage of a signal to be measured, so as to control the switch to be switchably connected to one end of the buffer or the first I/O port of the FPGA. In a specific implementation, if the FPGA detects that the signal to be detected is weak, for example, the voltage is low, the FPGA outputs a first control signal to the switch to control the switch to be connected to the buffer; and if the FPGA detects that the signal to be detected is stronger, for example, the voltage is high enough, a second control signal is output to the switch so as to control the switch to be directly connected to the FPGA.

Although particular embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are examples only and that the scope of the present invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and the principles of the present invention, and these changes and modifications are all within the scope of the present invention.

Claims

1. An FPGA-based multi-protocol analyzer, comprising: the system comprises an FPGA, a low-speed connector, a high-speed connector, a switch, a buffer, a PC and a DDR;

2. The multi-protocol analyzer of claim 1, wherein the low speed connector is configured to receive an I2C signal or an SPI signal.

3. The multi-protocol analyzer of claim 1, wherein the high-speed connector is to receive LVDS signals.

4. The multi-protocol analyzer of claim 1, wherein the FPGA is configured to output different control signals to the switch according to a voltage of a signal to be measured to control the switch to be switchably connected to one end of the buffer or the first I/O port of the FPGA.