CN113434444A - Data acquisition card and data acquisition method - Google Patents
Data acquisition card and data acquisition method Download PDFInfo
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- CN113434444A CN113434444A CN202110709448.0A CN202110709448A CN113434444A CN 113434444 A CN113434444 A CN 113434444A CN 202110709448 A CN202110709448 A CN 202110709448A CN 113434444 A CN113434444 A CN 113434444A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Abstract
The invention discloses a data acquisition card and a data acquisition method, wherein the data acquisition card comprises: the device comprises a multifunctional digital I/O module, an analog acquisition module, an analog output module, a digital signal processing module, a high-speed transmission module and a power management module; the digital signal processing module is respectively connected with the multifunctional digital I/O module, the analog acquisition module, the analog output module, the high-speed transmission module and the power management module. The invention can synchronously acquire analog signals of partial channels and single-ended signals and differential signals at the same time, can realize acquisition and analysis of differential signals and common-mode signals at the same time, realizes the effect of synchronous data acquisition, and has the sampling rate shared by all channels, thereby facilitating the subsequent data processing.
Description
Technical Field
The invention relates to the technical field of industrial testing, in particular to a data acquisition card and a data acquisition method.
Background
The data acquisition refers to the automatic acquisition of analog or digital signals to be measured of the equipment and the transmission of the signals to an upper computer for analysis and processing.
In the technical field of industrial testing, the existing USB data acquisition card has the following problems:
the middle-low end USB acquisition card is asynchronous data acquisition, the data acquisition is time-sharing acquisition, input signals cannot be acquired simultaneously, and the sampling rate is shared by all channels; the USB synchronous acquisition card has low sampling rate, the maximum sampling rate is only 500KSPS, and the price is high; for the same analog input channel, only single-ended input or differential input can be configured, and differential signals can not be acquired while single-ended signals are acquired for the same signals.
Disclosure of Invention
The invention provides a data acquisition card and a data acquisition method, wherein the data acquisition card can simultaneously acquire single-ended voltage and differential voltage, so that the data detection efficiency is improved, and the detection cost is reduced.
A first aspect of an embodiment of the present invention provides a data acquisition card, including: the device comprises a multifunctional digital I/O module, an analog acquisition module, an analog output module, a digital signal processing module, a high-speed transmission module and a power management module;
the digital signal processing module is respectively connected with the multifunctional digital I/O module, the analog acquisition module, the analog output module, the high-speed transmission module and the power management module;
the multifunctional digital I/O module is used for detecting the I/O level state of an external user or detecting the period and positive pulse width of an external data signal when the multifunctional digital I/O module is used as input, or converting and outputting a digital level when the multifunctional digital I/O module is used as output;
the analog acquisition module is used for acquiring an externally input analog signal;
the analog output module is used for outputting a periodic waveform or a direct current signal defined by a user;
the digital signal processing module is used for carrying out data processing, caching and transmission on an externally input analog signal or level state or external data signal period and positive pulse width;
the high-speed transmission module is used for carrying out data transmission with an external upper computer;
and the power supply management module is used for supplying power to the multifunctional digital I/O module, the analog acquisition module, the analog output module, the digital signal processing module and the high-speed transmission module.
In a possible implementation manner of the first aspect, the analog acquisition module includes: 3 ADC acquisition chips, namely ADC1, ADC2 and ADC3 are adopted;
wherein, the 8 channels of the ADC1 and the ADC3 adopt a pseudo-differential input connection mode;
the 8 channels of the ADC2 are connected using differential analog inputs.
In a possible implementation manner of the first aspect, the ADC1, the ADC2, and the ADC3 are respectively connected to external analog signal terminals, wherein the ADC1 and the ADC3 acquire single-ended signals, and the ADC2 acquires differential signals.
In a possible implementation manner of the first aspect, the digital signal processing module adopts an FPGA structure.
In a possible implementation manner of the first aspect, the FPGA structure includes: the system comprises a main controller, an ADC (analog to digital converter) drive, a DAC (digital to analog converter) drive, a USB (universal serial bus) drive, a DIO (digital to analog) drive and an LED (light-emitting diode) drive;
the main controller is respectively connected with the ADC drive, the DAC drive, the USB drive, the DIO drive and the LED drive;
the main controller is used for instruction analysis, data caching, processing and data transmission;
and the ADC driver is used for communicating with the ADC chip, starting acquisition and the like, and caching and preprocessing acquired data. And all ADC drives run in parallel;
and the DAC drive is used for communicating with the DAC chip, starting output and the like, caching data to be output and preprocessing the data. And all DAC drives run in parallel;
the USB driver is used for data transmission with an upper computer;
the DIO drive is used for controlling multifunctional digital IO, and realizing programmable input and output, a counter function and square wave output with adjustable duty ratio;
and the LED driver is used for indicating the working state of the acquisition card.
In a possible implementation manner of the first aspect, the digital signal processing module is provided with three sets of SPI communication circuits, each set of SPI communication circuit is connected with one ADC acquisition chip, and the SPI communication circuit is an SPI sequential control circuit developed by an FPGA structure.
In one possible implementation manner of the first aspect, the SPI communication circuit includes: and the gate circuit and the trigger are connected with each other.
In a possible implementation manner of the first aspect, a working level of the multifunctional digital I/O module is 0-3.3V;
and the conversion output digital level of the multifunctional digital I/O is square wave with adjustable duty ratio.
A second aspect of the embodiments of the present invention provides a data acquisition method, which is applied to the data acquisition card described above, and the method includes:
reading the configuration information of the data acquisition card;
when the configuration information is successfully read, setting an acquisition channel matched with the data acquisition card and acquiring detection data;
performing data analysis on the detection data and generating an analysis result;
and feeding back the analysis result to a preset connection terminal.
In a possible implementation manner of the second aspect, the performing data analysis on the detection data includes:
carrying out Fourier transform on the detection data to obtain transform data;
amplitude and frequency are calculated based on the transform data.
Compared with the prior art, the data acquisition card and the data acquisition method provided by the embodiment of the invention have the beneficial effects that: the invention can synchronously acquire analog signals of partial channels and single-ended signals and differential signals at the same time, can realize acquisition and analysis of differential signals and common-mode signals at the same moment, realizes the effect of synchronous data acquisition, has the sampling rate shared by all channels, is convenient for subsequent data processing, and is simultaneously based on a 16-bit ADC chip, has low price and can further reduce the product cost.
Drawings
Fig. 1 is a schematic structural diagram of a data acquisition card according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a data acquisition card according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an analog acquisition module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of data acquisition of an analog acquisition module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a digital signal processing module according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a digital signal processing module according to an embodiment of the present invention;
FIG. 7 is a circuit schematic of a multi-function digital I/O module provided by one embodiment of the present invention;
fig. 8 is a schematic structural diagram of a high-speed transmission module according to an embodiment of the present invention;
FIG. 9 is a schematic circuit diagram of a power management module according to an embodiment of the invention;
fig. 10 is a schematic flow chart of a data acquisition method according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of the steps of data analysis according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the technical field of industrial testing, the existing USB data acquisition card has the following problems:
the middle-low end USB acquisition card is asynchronous data acquisition, the data acquisition is time-sharing acquisition, input signals cannot be acquired simultaneously, and the sampling rate is shared by all channels; the USB synchronous acquisition card has low sampling rate, the maximum sampling rate is only 500KSPS, and the price is high; for the same analog input channel, only single-ended input or differential input can be configured, and differential signals can not be acquired while single-ended signals are acquired for the same signals.
In order to solve the above problems, a data acquisition card provided by the embodiments of the present application will be described and illustrated in detail by the following specific embodiments.
Referring to fig. 1-2, a schematic structural diagram of a data acquisition card according to an embodiment of the present invention and a schematic connection diagram of the data acquisition card according to an embodiment of the present invention are respectively shown.
As an example, the data acquisition card may include: a multifunctional digital I/O module (DIO), an analog acquisition module (ADC), an analog output module (DAC), a digital signal processing module (DSP), a high-speed transmission module (USB) and a Power Management module (Power Management);
the digital signal processing module is respectively connected with the multifunctional digital I/O module, the analog acquisition module, the analog output module, the high-speed transmission module and the power management module;
the multifunctional digital I/O module is used for detecting the I/O level state of an external user or detecting the period and positive pulse width of an external data signal when the multifunctional digital I/O module is used as input, or converting and outputting a digital level when the multifunctional digital I/O module is used as output;
the analog acquisition module is used for acquiring an externally input analog signal;
the analog output module is used for outputting a periodic waveform or a direct current signal defined by a user;
the digital signal processing module is used for carrying out data processing, caching and transmission on an externally input analog signal or level state or external data signal period and positive pulse width;
the high-speed transmission module is used for carrying out data transmission with an external upper computer;
and the power supply management module is used for supplying power to the multifunctional digital I/O module, the analog acquisition module, the analog output module, the digital signal processing module and the high-speed transmission module.
Referring to fig. 3, a schematic structural diagram of an analog acquisition module according to an embodiment of the present invention is shown. In this embodiment, the analog acquisition module includes: 3 ADC acquisition chips, namely ADC1, ADC2 and ADC3 are adopted;
wherein, the 8 channels of the ADC1 and the ADC3 adopt a pseudo-differential input connection mode (the negative pole of the differential input is connected with an analog ground);
the 8 channels of the ADC2 are connected using differential analog inputs.
Specifically, the ADC chip is a chip with a maximum sampling rate of 1MSPS, a resolution of 16Bits, and 8 channels.
Referring to fig. 4, a schematic data acquisition diagram of an analog acquisition module according to an embodiment of the present invention is shown.
In practical operation, the ADC1, the ADC2 and the ADC3 are respectively connected to external analog signal terminals, wherein the ADC1 and the ADC3 are configured to acquire single-ended signals, and the ADC2 is configured to acquire differential signals.
Specifically, 3 ADC chips are all provided with a start conversion trigger pin (CNV), and when in use, a trigger signal (for example, a rising edge signal) can be simultaneously generated on the start conversion trigger pin for the 3 ADC chips, and the 3 ADC chips can simultaneously start to collect an analog signal. Because each ADC chip is independently connected, each ADC chip can independently work and simultaneously acquire and convert analog signals. In addition, referring to fig. 4, the differential signal analog input pin and the single-ended signal input pin are shared.
In order to improve the control efficiency of the chip, in this embodiment, the digital signal processing module adopts an FPGA structure.
It should be noted that the input voltage range of each ADC chip is Max: + -10V.
Referring to fig. 5 to 6, a schematic structural diagram of a digital signal processing module according to an embodiment of the present invention and a schematic circuit diagram of the digital signal processing module according to the embodiment of the present invention are respectively shown. In one optional embodiment, the FPGA fabric includes: the system comprises a main controller, an ADC (analog to digital converter) drive, a DAC (digital to analog converter) drive, a USB (universal serial bus) drive, a DIO (digital to analog) drive and an LED (light-emitting diode) drive;
the main controller is respectively connected with the ADC drive, the DAC drive, the USB drive, the DIO drive and the LED drive;
the main controller is used for instruction analysis, data caching, processing and data transmission;
and the ADC driver is used for communicating with the ADC chip, starting acquisition and the like, and caching and preprocessing acquired data. And all ADC drives run in parallel;
and the DAC drive is used for communicating with the DAC chip, starting output and the like, caching data to be output and preprocessing the data. And all DAC drives run in parallel;
the USB driver is used for data transmission with an upper computer;
the DIO drive is used for controlling multifunctional digital IO, and realizing programmable input and output, a counter function and square wave output with adjustable duty ratio;
and the LED driver is used for indicating the working state of the acquisition card.
In order to facilitate independent control of each chip to work independently, in an optional embodiment, the digital signal processing module is provided with three groups of SPI communication circuits, each group of SPI communication circuits is connected with one ADC acquisition chip, and the SPI communication circuit is an SPI sequential control circuit developed by an FPGA structure.
Specifically, the SPI communication circuit includes: the interconnected gate circuit and flip-flop, SPI communication circuit can be equivalent to 3 identical SPI sequential control hardware circuits.
3 groups of independent SPI communication circuits are used for controlling 3 ADC chips to work independently and do not interfere with each other. Meanwhile, as the SPI time sequence control logic is developed by using an FPGA (field programmable gate array), and an SPI time sequence control circuit developed by the FPGA (field programmable gate array), namely a gate circuit, a trigger and the like are combined, the three SPI circuits are independent after the collection is started. In addition, in the process of communicating with the ADC chip, the acquired data can be read and stored in respective independent caches, so that subsequent data analysis and processing are facilitated.
In order to facilitate users to control 3 ADC chips to work independently, 3 groups of starting clocks can be used during specific implementation, and 3 ADCs can be controlled to start sampling simultaneously through 3 groups of starting clocks.
By using the FPGA structure, the programs can be run in parallel, so that all modules work in parallel, and the data processing efficiency can be improved.
In yet another alternative embodiment, the analog output module may be connected to the main controller by using parallel SPI buses, and the two AOs may operate independently, so that data transmission is performed simultaneously.
Referring to fig. 7, a circuit schematic diagram of a multifunctional digital I/O module according to an embodiment of the present invention is shown. In the embodiment, the working level of the multifunctional digital I/O module is 0-3.3V;
the conversion output digital level of the multifunctional digital I/O is square wave with adjustable duty ratio;
the multifunctional digital I/O may also measure the duty cycle, period, etc. of the external square wave.
Referring to fig. 8, a schematic structural diagram of a high-speed transmission module according to an embodiment of the present invention is shown.
In this embodiment, the high-speed transmission module uses a USB high-speed bus to meet the requirement of data transmission with the highest sampling rate.
Referring to fig. 9, a schematic circuit diagram of a power management module according to an embodiment of the present invention is shown.
The power management module can provide power for each module and also can provide overcurrent protection for each module.
In this embodiment, an embodiment of the present invention provides a data acquisition card, which has the following beneficial effects: the invention can synchronously acquire analog signals of partial channels and single-ended signals and differential signals at the same time, can realize acquisition and analysis of differential signals and common-mode signals at the same moment, realizes the effect of synchronous data acquisition, has the sampling rate shared by all channels, is convenient for subsequent data processing, and is simultaneously based on a 16-bit ADC chip, has low price and can further reduce the product cost.
An embodiment of the present invention further provides a data acquisition method, and referring to fig. 10, a flow diagram of the data acquisition method provided in the embodiment of the present invention is shown.
The data acquisition method can be applied to the data acquisition card as described in the above embodiments.
By way of example, the data acquisition method may include:
and S11, reading the configuration information of the data acquisition card.
And the configuration information is the configuration information of the data acquisition card.
In an alternative embodiment, the read configuration information includes: the number of digital IO channels, the channel, range, sampling rate and buffer size of the DAC, the channel, range and sampling rate of the ADC, etc.
The configuration information read out can be displayed in a software equipment information list at the PC side.
And S12, when the configuration information is read successfully, setting an acquisition channel matched with the data acquisition card and acquiring detection data.
When the configuration information is successfully read, the detection data can be acquired. In particular, the detection data may be data and signals collected by a data acquisition card.
And S13, performing data analysis on the detection data and generating an analysis result.
Referring to fig. 11, a schematic diagram of the steps of data analysis according to an embodiment of the present invention is shown. In an alternative embodiment, the step S13 may include the following sub-steps:
and a substep S131 of performing Fourier transform on the detection data to obtain transform data.
Substep S132, calculating amplitude and frequency based on the transformed data.
And S14, feeding back the analysis result to a preset connection terminal.
In particular, the amplitude and frequency may be sent to and displayed in the connected pc terminal for subsequent processing by the user.
Further, an embodiment of the present application further provides an electronic device, including: the data acquisition system comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the data acquisition method according to the embodiment.
Further, an embodiment of the present application also provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to enable a computer to execute the data acquisition method according to the embodiment.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A data acquisition card, said data acquisition card comprising: the device comprises a multifunctional digital I/O module, an analog acquisition module, an analog output module, a digital signal processing module, a high-speed transmission module and a power management module;
the digital signal processing module is respectively connected with the multifunctional digital I/O module, the analog acquisition module, the analog output module, the high-speed transmission module and the power management module;
the multifunctional digital I/O module is used for detecting the I/O level state of an external user or detecting the period and positive pulse width of an external data signal when the multifunctional digital I/O module is used as input, or converting and outputting a digital level when the multifunctional digital I/O module is used as output;
the analog acquisition module is used for acquiring an externally input analog signal;
the analog output module is used for outputting a periodic waveform or a direct current signal defined by a user;
the digital signal processing module is used for carrying out data processing, caching and transmission on an externally input analog signal or level state or external data signal period and positive pulse width;
the high-speed transmission module is used for carrying out data transmission with an external upper computer;
and the power supply management module is used for supplying power to the multifunctional digital I/O module, the analog acquisition module, the analog output module, the digital signal processing module and the high-speed transmission module.
2. The data acquisition card of claim 1, wherein the analog acquisition module comprises: 3 ADC acquisition chips, namely ADC1, ADC2 and ADC3 are adopted;
wherein, the 8 channels of the ADC1 and the ADC3 adopt a pseudo-differential input connection mode;
the 8 channels of the ADC2 are connected using differential analog inputs.
3. The data acquisition card according to claim 2, wherein said ADC1, ADC2 and ADC3 are respectively connected to external analog signal terminals, wherein said ADC1 and ADC3 acquire single-ended signals, and said ADC2 acquires differential signals.
4. The data acquisition card according to claim 2, wherein said digital signal processing module employs an FPGA architecture.
5. The data acquisition card of claim 4, wherein said FPGA structure comprises: the system comprises a main controller, an ADC (analog to digital converter) drive, a DAC (digital to analog converter) drive, a USB (universal serial bus) drive, a DIO (digital to analog) drive and an LED (light-emitting diode) drive;
the main controller is respectively connected with the ADC drive, the DAC drive, the USB drive, the DIO drive and the LED drive;
the main controller is used for instruction analysis, data caching, processing and data transmission;
and the ADC driver is used for communicating with the ADC chip, starting acquisition and the like, and caching and preprocessing acquired data. And all ADC drives run in parallel;
and the DAC drive is used for communicating with the DAC chip, starting output and the like, caching data to be output and preprocessing the data. And all DAC drives run in parallel;
the USB driver is used for data transmission with an upper computer;
the DIO drive is used for controlling multifunctional digital IO, and realizing programmable input and output, a counter function and square wave output with adjustable duty ratio;
and the LED driver is used for indicating the working state of the acquisition card.
6. The data acquisition card of claim 4, wherein the digital signal processing module is provided with three sets of SPI communication circuits, each set of SPI communication circuit is connected with one ADC acquisition chip, and the SPI communication circuit is an SPI time sequence control circuit developed by an FPGA structure.
7. The data acquisition card of claim 6, wherein said SPI communication circuit comprises: and the gate circuit and the trigger are connected with each other.
8. The data acquisition card according to claim 1, wherein the operating level of said multifunctional digital I/O module is 0-3.3V;
and the conversion output digital level of the multifunctional digital I/O is square wave with adjustable duty ratio.
9. A data acquisition method, characterized in that it is applied to a data acquisition card according to any one of claims 1 to 8, said method comprising:
reading the configuration information of the data acquisition card;
when the configuration information is successfully read, setting an acquisition channel matched with the data acquisition card and acquiring detection data;
performing data analysis on the detection data and generating an analysis result;
and feeding back the analysis result to a preset connection terminal.
10. The data acquisition method of claim 9, wherein the performing data analysis on the detection data comprises:
carrying out Fourier transform on the detection data to obtain transform data;
amplitude and frequency are calculated based on the transform data.
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