CN117353765B - Signal transmitting device, tester and signal output method of tester - Google Patents
Signal transmitting device, tester and signal output method of tester Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
- H04B17/0085—Monitoring; Testing using service channels; using auxiliary channels using test signal generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/15—Performance testing
- H04B17/16—Test equipment located at the transmitter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0491—Circuits with frequency synthesizers, frequency converters or modulators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0018—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0083—Signalling arrangements
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Abstract
The application relates to a signal transmitting device, a tester and a signal output method of the tester, wherein the signal transmitting device comprises: the storage module is used for storing the code pattern data; the signal transmitting module comprises a clock phase-locked loop module and a transmitting module, wherein the clock phase-locked loop module is connected with the waveform generating device and the transmitting module, and the transmitting module is connected with the storage module; the clock phase-locked loop module is used for receiving the spread spectrum clock output by the waveform generation device and outputting a clock signal with frequency fluctuation according to the configured frequency division and multiplication coefficient and the spread spectrum clock; the transmitting module outputs the code pattern data according to the clock signal. The spread spectrum clock is used for a signal sending module, a clock signal with frequency fluctuation is output through a clock phase-locked loop module, and the transmitting module outputs code pattern data according to the clock signal. On the premise of not using a shielding technology, the problem of overlarge electromagnetic interference radiation of high-speed digital signals can be effectively solved, and the radiation of emitted signals is reduced on the premise of avoiding influencing the use of a testing machine.
Description
Technical Field
The present disclosure relates to the field of chip testing technologies, and in particular, to a signal transmitting device, a testing machine, and a method for outputting signals from the testing machine.
Background
In the chip production process, a tester is required to test the chip. The signal transmitted by the tester may cause the energy of the signal to radiate too much at a certain frequency location if the energy is too concentrated at its carrier frequency location. EMI (Electromagnetic Interference ) reduction in circuits is usually achieved by shielding, i.e., adding a layer of grounding metal to the circuit, but this approach increases area and weight, which can be inconvenient for use of the tester.
Disclosure of Invention
In view of the above, it is necessary to provide a signal transmission device, a tester, and a tester signal output method that reduce radiation of an emission signal while avoiding affecting the use of the tester.
A signal transmission apparatus comprising:
the storage module is used for storing the code pattern data;
the signal transmitting module comprises a clock phase-locked loop module and a transmitting module, wherein the clock phase-locked loop module is connected with the waveform generating device and the transmitting module, and the transmitting module is connected with the storage module;
the clock phase-locked loop module is used for receiving the spread spectrum clock output by the waveform generation device and outputting a clock signal with frequency fluctuation according to the configured frequency division and multiplication coefficient and the spread spectrum clock; the transmitting module outputs the code pattern data according to the clock signal.
In one embodiment, the clock phase-locked loop module includes a phase discriminator, a loop filter, a voltage-controlled oscillator, a first frequency-dividing frequency multiplier, a second frequency-dividing frequency multiplier, a third frequency-dividing frequency multiplier and a loop lock indicator, wherein the first frequency-dividing frequency multiplier is connected with the waveform generating device, the loop lock indicator and the phase discriminator, the phase discriminator is connected with the loop filter, the voltage-controlled oscillator is connected with the loop filter, the second frequency-dividing frequency multiplier and the transmitting module, the second frequency-dividing frequency multiplier is connected with the third frequency-dividing frequency multiplier, the third frequency-dividing frequency multiplier is connected with the phase discriminator and the loop lock indicator, and the loop lock indicator is connected with the transmitting module; the frequency of the clock signal output by the clock phase-locked loop module is proportional to the frequency of the spread spectrum clock based on the frequency division coefficients of the first frequency division multiplier, the second frequency division multiplier and the third frequency division multiplier.
In one embodiment, the clock phase-locked loop module further includes a charge pump, and the phase detector is connected to the loop filter through the charge pump.
In one embodiment, the signal sending device further includes a buffer module, and the transmitting module is connected with the storage module through the buffer module.
In one embodiment, the signal transmitting device is an FPGA board card, and the signal transmitting module is a gigabit transmitter.
In one embodiment, the spread spectrum clock is a clock with fluctuating frequency, and/or the frequency division coefficient configured by the clock phase-locked loop module is a variable coefficient.
A testing machine comprises a waveform generating device and the signal transmitting device; the waveform generation device outputs a corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file.
In one embodiment, the waveform generating device comprises a logic control unit, a storage unit and a digital-to-analog conversion unit, wherein the logic control unit is connected with the storage unit and the digital-to-analog conversion unit, and the digital-to-analog conversion unit is connected with the clock phase-locked loop module; the logic control unit outputs a digital signal according to the waveform file stored in the storage unit, and the digital-to-analog conversion unit performs digital-to-analog conversion on the digital signal and outputs a corresponding spread spectrum clock.
In one embodiment, the waveform generating device further includes a filtering unit, and the digital-to-analog conversion unit is connected to the clock phase-locked loop module through the filtering unit.
In one embodiment, the testing machine further includes a host computer, where the host computer is connected to the waveform generating device, the storage module, and the clock phase-locked loop module; the upper computer is used for sending code pattern data to the storage module for storage, and carrying out parameter configuration on the waveform generation device and the clock phase-locked loop module.
In one embodiment, the upper computer configures a corresponding relationship between time and frequency according to the received programming parameters, and obtains a configuration table as the waveform file to be issued to the waveform generating device; wherein the programming parameters include center frequency, modulation period, and modulation amplitude.
In one embodiment, the waveform generation module is a direct digital frequency synthesizer or an arbitrary waveform generator.
A method of outputting a signal of a tester, comprising:
a clock phase-locked loop module in the signal transmitting module receives a spread spectrum clock output by the waveform generating device;
the clock phase-locked loop module outputs clock signals with frequency fluctuation according to the configured frequency division and multiplication coefficient and the spread spectrum clock;
the transmitting module in the signal transmitting module outputs the code pattern data stored in the storage module according to the clock signal;
the clock phase-locked loop module is connected with the waveform generation device and the transmitting module, and the transmitting module is connected with the storage module.
In one embodiment, before the clock phase-locked loop module in the signal sending module receives the spread spectrum clock output by the waveform generating device, the method further includes:
the waveform generating device outputs a corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file.
In one embodiment, before the waveform generating device outputs the corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file, the method further includes:
and the upper computer sends code pattern data to the storage module for storage, and performs parameter configuration on the waveform generating device and the clock phase-locked loop module.
In one embodiment, the parameter configuring the waveform generating device and the clock phase-locked loop module includes:
sending a configuration instruction to the clock phase-locked loop module, and configuring the frequency division coefficient of the clock phase-locked loop module;
according to the corresponding relation between the received programming parameter configuration time and frequency, a configuration table is obtained and used as the waveform file to be issued to the waveform generating device; wherein the programming parameters include center frequency, modulation period, and modulation amplitude.
In one embodiment, after the upper computer sends the pattern data to the storage module for storage, the method further includes:
the upper computer sends a code type data selection command to the storage module, and controls the storage module to output code type data or pseudo-random codes to the transmitting module.
According to the signal transmitting device, the testing machine and the signal output method of the testing machine, the clock phase-locked loop module in the signal transmitting module is used for receiving the spread spectrum clock output by the waveform generating device, outputting clock signals with fluctuating frequency according to the configured frequency division and multiplication coefficients and the spread spectrum clock, and outputting code pattern data stored by the storage module according to the clock signals by the transmitting module. The spread spectrum clock is used for a signal sending module, a clock signal with frequency fluctuation is output through a clock phase-locked loop module, and the transmitting module outputs code pattern data according to the clock signal. The signal transmission mode is improved, the problem of overlarge electromagnetic interference radiation of the high-speed digital signal can be effectively solved on the premise of not using a shielding technology, and the radiation of the transmitted signal is reduced on the premise of avoiding influencing the use of the testing machine.
Drawings
FIG. 1 is a block diagram of a signal transmitting apparatus in one embodiment;
FIG. 2 is a schematic diagram of the structure of a signal transmitting apparatus in one embodiment;
FIG. 3 is a block diagram of a waveform generation apparatus in one embodiment;
FIG. 4 is a schematic diagram of the structure of a tester in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In one embodiment, as shown in fig. 1, a signal transmitting apparatus 100 is provided, which includes a storage module 110 and a signal transmitting module 120, where the signal transmitting module 120 includes a clock phase-locked loop module 122 and a transmitting module TX, the clock phase-locked loop module 122 is connected to the waveform generating apparatus 200 and the transmitting module TX, and the transmitting module TX is connected to the storage module 110. The transmitting module TX may be, but not limited to, a radio frequency module, and the storage module 110 is used for storing code pattern data, and in this embodiment, the storage module 110 is a nonvolatile memory, and may be a volatile memory. The clock phase-locked loop module 122 is configured to receive the spread spectrum clock output by the waveform generating device 200, and output a clock signal with a fluctuating frequency according to the configured frequency division and multiplication coefficient and the spread spectrum clock; the transmitting module TX acquires the pattern data stored in the storage module 110 and outputs the pattern data according to the clock signal.
Specifically, the code PATTERN data (PATTERN) may be transmitted to the storage module 110 for storage through an upper computer, which may be various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices, such as smart watches, smart bracelets, headsets, and the like. The type of the signal transmission module 120 may be different according to the type of the signal transmission apparatus 100. In this embodiment, the signal transmitting apparatus 100 is an FPGA (Field-Programmable Gate Array, field programmable gate array), and the signal transmitting module 120 is a gigabit transmitter.
After the host computer edits the pattern data, the pattern data is written into the corresponding address in the memory module 110 by the bus write command, and the signal transmitting apparatus 100 loads the pattern data. The upper computer can also send a code pattern data selection command to select the currently sent code pattern data as the self-defined code pattern data, namely the edited code pattern data, or pseudo-random code PRBS generated in the FPGA, wherein the pseudo-random code PRBS is used as a selection of two or more, is used for simulating and testing a high-speed digital communication link, is used for simulating a real data stream, and can effectively reflect the quality of the high-speed digital link.
Further, the waveform generating apparatus 200 may be further configured by an upper computer, so that the waveform generating apparatus 200 outputs a spread spectrum clock as a reference clock of the signal transmitting module 120, to implement a spread spectrum function. The waveform generation apparatus 200 may employ a direct digital frequency synthesizer (Direct Digital Synthesizer, DDS), an arbitrary waveform generator (Arbitrary Waveform Generator, AWG) or other device. Specifically, taking the waveform generation device 200 as an example, a direct digital frequency synthesizer, i.e. a DDS clock chip, as shown in fig. 2, the upper computer issues a configuration instruction to the global configuration register CFG of the FPGA, and the global configuration register CFG outputs parameters configuring the peripheral DDS clock chip after receiving the configuration instruction of the upper computer, and the DDS clock chip outputs a spread spectrum clock as a reference clock of the signal transmission module 120 after the configuration is successful, so as to realize a spread spectrum function.
In addition, the clock phase-locked loop module 122 in the signal sending module 120 can be configured by an upper computer, and the command for configuring the frequency division coefficient of the clock phase-locked loop module 122 is written according to the bus protocol, so that the clock phase-locked loop module 122 can output clock signals with different frequencies.
Specifically, after the clock phase-locked loop module 122 and the waveform generating device 200 complete configuration, the waveform generating device 200 outputs a spread spectrum clock to the clock phase-locked loop module 122, and the clock phase-locked loop module 122 outputs a clock signal with a fluctuating frequency to the transmitting module TX according to the configured frequency division coefficient and the received spread spectrum clock. After the transmitting module TX acquires the code pattern data stored in the storage module 110, the transmitting module TX outputs the code pattern data according to the clock signal and sends the code pattern data to the chip DUT to be tested in a differential mode, and jitter exists in a data sending interval, so that the phenomenon that the EMI radiation is overlarge due to the fact that signals are concentrated at a certain frequency point is avoided.
In one embodiment, the spread spectrum clock is a frequency fluctuating clock and/or the frequency division coefficient configured by clock phase locked loop module 122 is a varying coefficient. Specifically, the DDS clock chip outputs a frequency-fluctuating spread spectrum clock, so as to keep the frequency-dividing coefficient configured by the clock phase-locked loop module 122 unchanged, and the clock phase-locked loop module 122 receives the frequency-fluctuating spread spectrum clock and outputs a frequency-fluctuating clock signal; the frequency division and multiplication coefficient configured by the clock phase-locked loop module 122 can be changed by outputting a frequency-unchanged spread spectrum clock through the DDS clock chip, so that the clock phase-locked loop module 122 outputs a clock signal with a fluctuating frequency. In addition, the DDS clock chip may output a frequency-fluctuating spread spectrum clock, and meanwhile, the frequency-dividing coefficient configured by the clock phase-locked loop module 122 may be changed, so that the clock phase-locked loop module 122 may output a frequency-fluctuating clock signal.
The function of adding a spread spectrum clock to a signal which is easy to generate EMI is that the signal energy is dispersed within a certain frequency band range, the whole amplitude of the signal energy is obviously reduced, and thus the EMI radiation emission of the signal is effectively restrained, which is the basic principle of restraining the EMI radiation by using the spread spectrum clock.
The application adopts the scheme, improves from the design of the high-speed digital signal, and does not add a metal shielding layer around. On the premise of not using a shielding technology, the problem of overlarge EMI radiation of high-speed digital signals can be effectively solved. Clock phase-locked loop module 122 in the gigabit transmitter can lock the spread spectrum clock and can lock the spread spectrum clock with ±3% spread, which can greatly reduce EMI emissions and spread the energy over a wider frequency domain. By using a spread spectrum clock for the gigabit transmitter, the effect of reducing EMI emissions of high-speed digital signals is achieved.
In the signal transmission device 100, the spread spectrum clock is used in the signal transmission module 120, the clock phase-locked loop module 122 outputs a clock signal with a fluctuating frequency, and the transmission module TX outputs code pattern data according to the clock signal. The signal transmission mode is improved, the problem of overlarge electromagnetic interference radiation of the high-speed digital signal can be effectively solved on the premise of not using a shielding technology, and the radiation of the transmitted signal is reduced on the premise of avoiding influencing the use of the testing machine.
It will be appreciated that the specific structure of the clock phase-locked loop module 122 is not exclusive, and in one embodiment, as shown in fig. 2, the clock phase-locked loop module 122 includes a phase detector PFD, a loop filter LF, a voltage controlled oscillator VCO, a first frequency divider multiplier 21, a second frequency divider multiplier 22, a third frequency divider multiplier 23, and a loop lock indicator LI. Wherein M, N, N2 are frequency division coefficients of the first frequency division multiplier 21, the second frequency division multiplier 22 and the third frequency division multiplier 23, respectively, which are set by the upper computer through an external configuration interface. The first frequency-dividing multiplier 21 is connected with the waveform generating device 200, the loop lock indicator LI and the phase discriminator PFD, the phase discriminator PFD is connected with the loop filter LF, the voltage-controlled oscillator VCO is connected with the loop filter LF, the second frequency-dividing multiplier 22 and the transmitting module TX, the second frequency-dividing multiplier 22 is connected with the third frequency-dividing multiplier 23, the third frequency-dividing multiplier 23 is connected with the phase discriminator PFD and the loop lock indicator LI, and the loop lock indicator LI is connected with the transmitting module TX. The frequency of the clock signal output by the clock phase-locked loop module 122 is proportional to the frequency of the spread spectrum clock based on the division coefficients of the first division multiplier 21, the second division multiplier 22, and the third division multiplier 23. Further, the clock phase-locked loop module 122 further includes a charge pump CP, through which the phase detector PFD is connected to the loop filter LF.
Taking the waveform generation device 200 as an example, the first frequency-dividing multiplier 21 is connected to the DDS clock chip and receives the spread clock pll_clkin output by the DDS clock chip. The phase detector PFD serves to compare the phase of the input signal with the phase of the output signal of the voltage-controlled oscillator VCO and to convert the comparison result into an error voltage Ud (t) which is a function of the phase difference of the two signals. In this embodiment, the clock phase-locked loop module 122 is a charge pump phase-locked loop module, a charge pump CP is added between the phase detector PFD and the loop filter LF, and the charge pump CP drives a capacitor in the loop filter LF to form an integrator, so as to improve the loop gain. The loop filter LF is specifically a low-pass filter, and functions to filter out the high-frequency component in the error voltage Ud (t) to obtain the control voltage Uc (t), and applies the control voltage Uc (t) to the VCO. The VCO is usually composed of a varactor, a reactor, and the like, and the output frequency Fvco of the VCO is controlled by the control voltage Uc (t).
Specifically, the spread spectrum clock pll_clkin is transmitted to the phase detector PFD and the loop lock indicator LI after passing through the first frequency division multiplier 21, the error voltage Ud (t) output by the phase detector PFD sequentially passes through the charge pump CP and the loop filter LF and then reaches the voltage controlled oscillator VCO, the signal output by the voltage controlled oscillator VCO sequentially passes through the second frequency division multiplier 22 and the third frequency division multiplier 23, and the third frequency division multiplier 23 outputs the signal to the phase detector PFD and the loop lock indicator LI. When the frequencies of the input signal and the output signal are the same, the low-frequency component in the output of the phase discriminator PFD is zero, the output of the loop filter LF is also zero, and the oscillation frequency of the voltage-controlled oscillator VCO is not changed; if the frequencies of the input signal and the output signal are not identical, the phase detector PFD will generate a low frequency component and the frequency of the voltage controlled oscillator VCO will be changed by the loop filter LF, which will continuously bring the frequency of the output signal and the frequency of the input signal into agreement, eventually the equal phase difference between the two frequencies will be constant, the output frequency of the voltage controlled oscillator VCO will stop changing, the loop is in a locked state, and the loop LOCK indicator LI outputs a LOCK signal pll_lock to the transmitting module TX. The transmitting module TX acquires pattern data from the storage module 110, and after receiving the LOCK signal pll_lock, outputs a high-speed signal to the chip under test DUT according to the clock signal pll_clkout transmitted by the voltage-controlled oscillator VCO.
The frequency division coefficient configured by the clock phase-locked loop module 122 is kept unchanged by using the spread spectrum clock pll_clkin with the DDS clock chip output frequency fluctuation, when the DDS clock chip outputs a clock with a certain frequency, the clock phase-locked loop module 122 internally performs signal comparison to make the loop in a locked state, and when the DDS clock chip outputs a clock with another frequency, the clock phase-locked loop module 122 internally continues signal comparison according to the newly received clock to make the loop in the locked state again. When the frequency division coefficients M, N, N2 inside the clock phase-locked loop module 122 are fixed, the clock frequency of the spread spectrum clock pll_clkin is changed, so that the change of the clock frequency of the output clock signal pll_clkout can be realized, and the spread spectrum clock function of the output signal is further realized. The upper computer PC can be connected with the DDS clock chip through the global configuration register CFG of the FPGA, and issues a configuration command CMD_PC command to configure the DDS clock chip. The host PC may also issue a configuration command cmd_pc to the clock pll module 122 to configure the clock pll module 122 with the frequency division coefficient. The upper computer PC transmits corresponding code pattern data through the serial port Uart to be written into the storage module 110, after the code pattern data is stored into the storage module 110, the signal transmission module 120 acquires the data of the storage module 110, finally, a high-speed signal is transmitted from the transmission module TX of the signal transmission module 120 and is transmitted to the chip DUT to be tested in a differential mode, jitter exists at a data transmission interval, and the phenomenon that the signal is concentrated at a certain frequency point to cause excessive EMI radiation is avoided. Since the clock signal pll_clkout has a spread spectrum function, the high-speed signal emitted by the transmitting module TX has already achieved the effect of reducing EMI radiation.
In one embodiment, the signal transmitting apparatus 100 further includes a buffer module, through which the transmitting module TX is connected to the storage module 110. Specifically, as shown in fig. 2, the buffer module may employ a FIFO (First Input First Output, first-in-first-out queue) module. In addition, the memory module 110 may be further connected to the external crystal oscillator OSC through the mixed mode clock manager MMCM, and the system clock SYSCLK is output to the memory module 110 through the mixed mode clock manager MMCM. The storage module 110 may specifically include a read-write control unit and a data storage unit, where code pattern data issued by the host PC is received through the read-write control unit and stored in the data storage unit. The read-write control unit also selects the self-defined code pattern data from the data storage unit according to the code pattern data selection command sent by the upper computer PC, or the pseudo-random code PRBS is sent to the FIFO module for caching. The transmitting module TX in the signal transmitting module 120 reads the buffered data from the FIFO module and transmits it in differential form to the chip under test DUT.
In this embodiment, the FIFO module is used for cross-clock processing under different clock domains. The storage module 110 reads data according to the working clock and sends the data to the FIFO module for caching, and the transmitting module TX in the signal sending module 120 reads the cached data from the FIFO module according to the working clock, and when the working clock of the storage module 110 is inconsistent with the working clock of the transmitting module TX, the data is cached through the FIFO module, so that the data reading is convenient.
In one embodiment, there is also provided a testing machine including a waveform generating device and the signal transmitting device described above; the waveform generating device outputs a corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file. Further, the testing machine also comprises an upper computer. The upper computer is connected with the waveform generating device, the storage module and the clock phase-locked loop module; the upper computer is used for sending code pattern data to the storage module for storage, and carrying out parameter configuration on the waveform generation device and the clock phase-locked loop module. It can be understood that the specific manner of outputting the signal by the testing machine is explained in detail in the above signal transmitting device, and will not be described herein.
As shown in fig. 3, the waveform generating apparatus 200 may include a logic control unit 210, a storage unit 220, and a digital-to-analog conversion unit DAC, where the logic control unit 210 is connected to the storage unit 220 and the digital-to-analog conversion unit DAC, and the digital-to-analog conversion unit DAC is connected to the clock phase-locked loop module 122; the storage unit 220 is connected to the global configuration register CFG of the FPGA, after the upper computer edits the configured waveform file, the waveform file is issued to the global configuration register CFG of the FPGA in a mode of a configuration command cmd_pc command, and then the waveform file is imported into the storage unit 220 of the waveform generating apparatus 200 through the global configuration register CFG of the FPGA. The logic control unit 210 outputs a digital signal according to the waveform file stored in the storage unit 220, and the digital-to-analog conversion unit DAC performs digital-to-analog conversion on the digital signal and outputs a corresponding spread spectrum clock.
Further, the waveform generating apparatus 200 further includes a filtering unit F, and the digital-to-analog conversion unit DAC is connected to the clock phase-locked loop module 122 through the filtering unit F. The digital-to-analog conversion unit DAC performs digital-to-analog conversion on the digital signal, and the obtained spread spectrum clock is filtered by the filtering unit F1 and then output to the clock phase-locked loop module 122.
In particular, the digital-to-analog conversion unit DAC may employ a high-speed digital-to-analog converter. The upper computer writes the waveform file into the storage unit 220 through the external configuration interface, after the logic control unit 210 reads the waveform file stored in the storage unit 220, the digital-to-analog conversion unit DAC is configured to output a specific waveform according to the waveform file, and smooth continuous signal waveforms are output after passing through the filtering unit F at the later stage, so that after the storage unit 220 stores a plurality of waveform files with different frequencies, the waveform generating device 200 can output spread spectrum clocks with different frequencies. The waveform file may be imported into the waveform generation apparatus 200 by the host computer and stored. The waveform file characterizes the correspondence of time and frequency of the desired waveform. After the upper computer edits the configured waveform file, the waveform file is issued to the global configuration register CFG of the FPGA in a mode of a configuration command cmd_pc command, and then the waveform file is imported into the storage unit 220 of the waveform generating device 200 through the global configuration register CFG of the FPGA. The logic control unit 210 outputs a corresponding digital signal according to the waveform file stored in the storage unit 220, performs digital-to-analog conversion by the digital-to-analog conversion unit DAC, and then sends the spread spectrum clock to the clock phase-locked loop module 122 after filtering by the filtering unit F. The upper computer configures the corresponding relation between time and frequency according to the received programming parameters, obtains a configuration table as a waveform file and sends the waveform file to the waveform generating device 200; the programming parameters include center frequency, modulation period, and modulation amplitude.
Specifically, when the shortest time of frequency change of the spread spectrum clock is T, the frequency change scale is F, the center frequency is set to be F0, the modulation period is FM, and the modulation amplitude is Mag, the following is calculated:
frequency change number num=fm/T
Frequency change scale f=mag/Num
The maximum value of the modulation period FM cannot exceed the filter bandwidth of the clock pll module 122, so that the maximum value is not filtered out as noise, and normal variation of the output clock signal cannot be realized.
Specifically, the configuration table of the specific spread spectrum clock obtained by the above calculation is shown in table 1, and the continuously variable spread spectrum clock can be output after the configuration table is converted into a waveform file for issuing according to the actual format requirement of the waveform generating device 200. The spread clock output by the waveform generation device 200 shown in table 1 is a triangular waveform, and in other embodiments, the spread clock output by the waveform generation device 200 may be changed to other types of waveforms, proportional sine waveforms, or the like, as required.
TABLE 1
When the spread spectrum clock is actually adjusted, the upper computer firstly reads the edited center frequency F0, the modulation period FM and the modulation amplitude Mag, calculates and generates a configuration table according to the read parameters, and transmits the configuration table as a waveform file to the waveform generating device 200, so that the waveform generating device 200 transmits the spread spectrum clock to the clock phase-locked loop module 122, and further transmits a clock signal to the transmitting module TX through the clock phase-locked loop module 122, the spread spectrum clock has programmable capability, and the spread spectrum clock can be realized by utilizing the existing devices, and a reference method is provided for the spread spectrum clock test of the high-speed signal.
According to the tester, the spread spectrum clock is used for the signal transmission module, the signal transmission mode is improved, the problem that electromagnetic interference radiation of high-speed digital signals is overlarge can be effectively solved on the premise that a shielding technology is not used, and radiation of emission signals is reduced on the premise that the use of the tester is prevented from being influenced.
In one embodiment, there is also provided a method of outputting a tester signal, comprising: a clock phase-locked loop module in the signal transmitting module receives a spread spectrum clock output by the waveform generating device; the clock phase-locked loop module outputs clock signals with fluctuating frequency according to the configured frequency division and multiplication coefficient and the spread spectrum clock; the transmitting module in the signal transmitting module outputs the code pattern data stored in the storage module according to the clock signal; the clock phase-locked loop module is connected with the waveform generating device and the transmitting module, and the transmitting module is connected with the storage module.
In one embodiment, before the clock phase-locked loop module in the signal sending module receives the spread spectrum clock output by the waveform generating device, the method further includes: the waveform generating device outputs a corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file.
In one embodiment, before the waveform generating device outputs the corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file, the method further includes: the upper computer sends code pattern data to the storage module for storage, and parameter configuration is carried out on the waveform generation device and the clock phase-locked loop module.
In one embodiment, parameter configuration is performed on the waveform generation device and the clock phase-locked loop module, including: transmitting a configuration instruction to a clock phase-locked loop module, and configuring the frequency division coefficient of the clock phase-locked loop module; according to the received corresponding relation between the programming parameter configuration time and the frequency, a configuration table is obtained and is used as a waveform file to be issued to a waveform generating device; wherein the programming parameters include center frequency, modulation period, and modulation amplitude.
In one embodiment, after the upper computer sends the pattern data to the storage module for storage, the method further includes: the upper computer sends a code type data selection command to the storage module, and controls the storage module to output code type data or pseudo-random codes to the transmitting module.
As shown in fig. 4, the upper computer PC edits and issues patterm content to the storage module 110 of the FPGA, and the signal transmission apparatus 100 loads patterm. The upper computer PC may also send a patterm selection command to the storage module 110 to perform patterm source selection, for example, select the currently sent patterm from the storage module 110 to be the self-defined code PATTERN data, or send the pseudo random code PRBS generated in the FPGA to the FIFO module to be buffered. Further, the configuration instruction is issued by the upper computer PC to transmit the waveform file to the global configuration register CFG of the FPGA, the waveform file is led into the storage unit 220 of the waveform generating device 200 through the global configuration register CFG, the logic control unit 210 outputs a corresponding digital signal according to the waveform file stored in the storage unit 220, the digital-to-analog conversion unit DAC performs digital-to-analog conversion, and the filtering unit F filters the digital-to-analog conversion signal to transmit the spread spectrum clock to the clock phase-locked loop module 122. The waveform generating apparatus 200 may specifically use a DDS clock chip, and after the configuration is successful, the DDS clock chip outputs a spread spectrum clock as a reference clock of the signal transmitting module 120, and in this embodiment, the signal transmitting module 120 is a gigabit transmitter GTH. After the clock phase-locked loop module 122 in the gigabit transmitter GTH is configured by the host PC, the clock phase-locked loop module 122 outputs a clock signal with a frequency fluctuation to the transmitting module TX according to the configured frequency division coefficient and the received spread spectrum clock, and in this embodiment, the clock phase-locked loop module 122 is a PLL (Phase Locked Loop, phase-locked loop). After the transmitting module TX reads the cached PATTERN data from the FIFO module, the PATTERN data is output according to a clock signal and is transmitted to the chip DUT to be tested in a differential mode, jitter exists in a data transmission interval, and the phenomenon that the EMI radiation is overlarge due to the fact that signals are concentrated at a certain frequency point is avoided.
Similarly, the specific embodiments of the signal output method of the testing machine are explained in detail in the signal sending device and the testing machine, and are not repeated here.
According to the signal output method of the tester, the clock phase-locked loop module in the signal sending module receives the spread spectrum clock output by the waveform generating device, locks the spread spectrum clock according to the configured frequency division and multiplication coefficient, outputs a clock signal with a corresponding frequency, and then outputs code pattern data stored by the storage module according to the clock signal by the transmitting module. The spread spectrum clock is used for a signal sending module, a clock signal with frequency fluctuation is output through a clock phase-locked loop module, and the transmitting module outputs code pattern data according to the clock signal. The signal transmission mode is improved, the problem of overlarge electromagnetic interference radiation of the high-speed digital signal can be effectively solved on the premise of not using a shielding technology, and the radiation of the transmitted signal is reduced on the premise of avoiding influencing the use of the testing machine.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (15)
1. A signal transmission apparatus, comprising:
the storage module is used for storing the code pattern data;
the signal transmitting module comprises a clock phase-locked loop module and a transmitting module, wherein the clock phase-locked loop module is connected with the waveform generating device and the transmitting module, and the transmitting module is connected with the storage module; the signal transmitting device is an FPGA, and the signal transmitting module is a gigabit transmitter;
the clock phase-locked loop module is used for receiving the spread spectrum clock output by the waveform generation device and outputting a clock signal with frequency fluctuation according to the configured frequency division and multiplication coefficient and the spread spectrum clock; the transmitting module outputs the code pattern data according to the clock signal; the spread spectrum clock is a clock with frequency fluctuation, and/or the frequency division coefficient configured by the clock phase-locked loop module is a variable coefficient;
the clock phase-locked loop module comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled oscillator, a first frequency division frequency multiplier, a second frequency division frequency multiplier, a third frequency division frequency multiplier and a loop locking indicator, wherein the first frequency division frequency multiplier is connected with the waveform generating device, the loop locking indicator and the phase discriminator, the phase discriminator is connected with the loop filter through the charge pump, the voltage-controlled oscillator is connected with the loop filter, the second frequency division frequency multiplier and the transmitting module, the second frequency division frequency multiplier is connected with the third frequency division frequency multiplier, the third frequency division frequency multiplier is connected with the phase discriminator and the loop locking indicator, and the loop locking indicator is connected with the transmitting module; the frequency of the clock signal output by the clock phase-locked loop module is proportional to the frequency of the spread spectrum clock based on the frequency division coefficients of the first frequency division multiplier, the second frequency division multiplier and the third frequency division multiplier; the loop filter is a low-pass filter;
the phase discriminator is used for comparing the phase of an input signal with the phase of an output signal of the voltage-controlled oscillator and converting the comparison result into an error voltage; the spread spectrum clock is transmitted to the phase detector and the loop locking indicator after passing through the first frequency division frequency multiplier, error voltage output by the phase detector sequentially passes through the charge pump and the loop filter and then reaches the voltage-controlled oscillator, signals output by the voltage-controlled oscillator sequentially pass through the second frequency division frequency multiplier and the third frequency division frequency multiplier, and signals output by the third frequency division frequency multiplier are transmitted to the phase detector and the loop locking indicator; when the frequencies of the input signal and the output signal are the same, the low-frequency component in the output of the phase discriminator is zero, the output of the loop filter is also zero, and the oscillation frequency of the voltage-controlled oscillator is not changed; if the frequencies of the input signal and the output signal are inconsistent, the phase discriminator generates a low-frequency component, the frequency of the voltage-controlled oscillator is changed through the loop filter, the frequency of the output signal and the frequency of the input signal are continuously consistent, and finally the equal phase difference between the frequencies is constant, the output frequency of the voltage-controlled oscillator is stopped to be changed, the loop is in a locking state, and the loop locking indicator outputs a locking signal to the transmitting module;
the transmitting module acquires code pattern data from the storage module, outputs the code pattern data according to a clock signal sent by the voltage-controlled oscillator after receiving the locking signal, and sends the code pattern data to a chip to be tested in a differential mode.
2. The signaling device of claim 1, wherein the transmitting module is a radio frequency module and the storage module is a non-volatile memory or a volatile memory.
3. The signal transmission apparatus according to claim 2, wherein the waveform generation means is a direct digital frequency synthesizer or an arbitrary waveform generator.
4. The signaling device of claim 1, further comprising a buffer module, wherein the transmitting module is coupled to the storage module through the buffer module.
5. The signaling apparatus of claim 4 wherein the buffer module is a FIFO module.
6. A test machine comprising waveform generating means and signal transmitting means as claimed in any one of claims 1 to 5; the waveform generation device outputs a corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file.
7. The tester according to claim 6, wherein the waveform generating device comprises a logic control unit, a storage unit and a digital-to-analog conversion unit, the logic control unit is connected with the storage unit and the digital-to-analog conversion unit, and the digital-to-analog conversion unit is connected with the clock phase-locked loop module; the logic control unit outputs a digital signal according to the waveform file stored in the storage unit, and the digital-to-analog conversion unit performs digital-to-analog conversion on the digital signal and outputs a corresponding spread spectrum clock.
8. The tester according to claim 7, wherein the waveform generating device further comprises a filtering unit, and the digital-to-analog conversion unit is connected to the clock phase-locked loop module through the filtering unit.
9. The tester according to claim 6, further comprising a host computer connected to the waveform generation device, the storage module, and the clock phase-locked loop module; the upper computer is used for sending code pattern data to the storage module for storage, and carrying out parameter configuration on the waveform generation device and the clock phase-locked loop module.
10. The test machine according to claim 9, wherein the upper computer configures a correspondence between time and frequency according to the received programming parameters, and obtains a configuration table as the waveform file to be issued to the waveform generating device; wherein the programming parameters include center frequency, modulation period, and modulation amplitude.
11. The signal output method of the tester is characterized by being used for testing the chip to be tested by the tester; the method comprises the following steps:
a clock phase-locked loop module in the signal transmitting module receives a spread spectrum clock output by the waveform generating device;
the clock phase-locked loop module outputs clock signals with frequency fluctuation according to the configured frequency division and multiplication coefficient and the spread spectrum clock;
the transmitting module in the signal transmitting module outputs the code pattern data stored in the storage module according to the clock signal;
the clock phase-locked loop module is connected with the waveform generating device and the transmitting module, and the transmitting module is connected with the storage module; the spread spectrum clock is a clock with frequency fluctuation, and/or the frequency division coefficient configured by the clock phase-locked loop module is a variable coefficient; the signal transmitting device is an FPGA, and the signal transmitting module is a gigabit transmitter;
the clock phase-locked loop module comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled oscillator, a first frequency division frequency multiplier, a second frequency division frequency multiplier, a third frequency division frequency multiplier and a loop locking indicator, wherein the first frequency division frequency multiplier is connected with the waveform generating device, the loop locking indicator and the phase discriminator, the phase discriminator is connected with the loop filter through the charge pump, the voltage-controlled oscillator is connected with the loop filter, the second frequency division frequency multiplier and the transmitting module, the second frequency division frequency multiplier is connected with the third frequency division frequency multiplier, the third frequency division frequency multiplier is connected with the phase discriminator and the loop locking indicator, and the loop locking indicator is connected with the transmitting module; the frequency of the clock signal output by the clock phase-locked loop module is proportional to the frequency of the spread spectrum clock based on the frequency division coefficients of the first frequency division multiplier, the second frequency division multiplier and the third frequency division multiplier; the loop filter is a low-pass filter;
the phase discriminator is used for comparing the phase of an input signal with the phase of an output signal of the voltage-controlled oscillator and converting the comparison result into an error voltage; the spread spectrum clock is transmitted to the phase detector and the loop locking indicator after passing through the first frequency division frequency multiplier, error voltage output by the phase detector sequentially passes through the charge pump and the loop filter and then reaches the voltage-controlled oscillator, signals output by the voltage-controlled oscillator sequentially pass through the second frequency division frequency multiplier and the third frequency division frequency multiplier, and signals output by the third frequency division frequency multiplier are transmitted to the phase detector and the loop locking indicator; when the frequencies of the input signal and the output signal are the same, the low-frequency component in the output of the phase discriminator is zero, the output of the loop filter is also zero, and the oscillation frequency of the voltage-controlled oscillator is not changed; if the frequencies of the input signal and the output signal are inconsistent, the phase discriminator generates a low-frequency component, the frequency of the voltage-controlled oscillator is changed through the loop filter, the frequency of the output signal and the frequency of the input signal are continuously consistent, and finally the equal phase difference between the frequencies is constant, the output frequency of the voltage-controlled oscillator is stopped to be changed, the loop is in a locking state, and the loop locking indicator outputs a locking signal to the transmitting module;
the transmitting module acquires code pattern data from the storage module, outputs the code pattern data according to a clock signal sent by the voltage-controlled oscillator after receiving the locking signal, and sends the code pattern data to a chip to be tested in a differential mode.
12. The method of claim 11, wherein the clock phase-locked loop module in the signal transmission module further comprises, before receiving the spread spectrum clock output by the waveform generation device:
the waveform generating device outputs a corresponding spread spectrum clock to the clock phase-locked loop module according to the configured waveform file.
13. The method of claim 12, wherein the waveform generation device further comprises, before outputting the corresponding spread spectrum clock to the clock phase locked loop module according to the configured waveform file:
and the upper computer sends code pattern data to the storage module for storage, and performs parameter configuration on the waveform generating device and the clock phase-locked loop module.
14. The method of claim 13, wherein said parameter configuring said waveform generation means and said clock phase locked loop module comprises:
sending a configuration instruction to the clock phase-locked loop module, and configuring the frequency division coefficient of the clock phase-locked loop module;
according to the corresponding relation between the received programming parameter configuration time and frequency, a configuration table is obtained and used as the waveform file to be issued to the waveform generating device; wherein the programming parameters include center frequency, modulation period, and modulation amplitude.
15. The method of claim 13, wherein after the host computer sends the pattern data to the storage module for storage, further comprising:
the upper computer sends a code type data selection command to the storage module, and controls the storage module to output code type data or pseudo-random codes to the transmitting module.
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