CN117930143A - OFDM-LFM signal generating circuit based on phase-locked loop - Google Patents

Abstract

The invention discloses an OFDM-LFM signal generating circuit based on a phase-locked loop, and belongs to the field of electronic information systems. The circuit adopts a plurality of decimal frequency division PLLs based on sigma-delta fast modulation to generate subcarriers of the LFM; the high-stability crystal oscillator is adopted, and the phase relativity of each channel is ensured by using power distribution as a reference clock of the PLL; and a singlechip is used as a control core to send waveform control parameters and transmit trigger signals to the PLL. The circuit greatly reduces the complexity of the MIMO radar adopting the OFDM-LFM signal system, saves resources, and has obvious advantages in link simplicity under the condition of more subcarriers.

Description

OFDM-LFM signal generating circuit based on phase-locked loop

Technical Field

The invention belongs to the field of electronic information systems, and particularly relates to an OFDM-LFM signal generating circuit based on a phase-locked loop.

Background

With the development of millimeter wave radar and new generation wireless communication, the radar and communication need larger bandwidth to realize high resolution and high speed, so that spectrum resources are increasingly deficient, and therefore, the integration of radar communication waveforms to realize spectrum sharing is an effective means, and meanwhile, the integration of radar communication loads is facilitated. The radar and the communication system generally adopt a MIMO (multiple input multiple output) system to realize higher flexibility, and an OFDM-LFM (orthogonal frequency division multiplexing-linear frequency modulation) waveform is the most commonly used MIMO waveform, so that the radar and the communication system have the advantages of flexible subcarrier modulation, high spectrum utilization rate, convenience in synchronization and equalization and the like, and have the advantages of large bandwidth, simpler signal processing, convenience in realization and the like for the radar. The definition of OFDM-LFM waveforms is similar to frequency stepping signals, in that orthogonalization between transmit waveforms is achieved by transmitting wavelets of different frequency bands through multiple channels.

In the existing MIMO system, OFDM-LFM signals are usually generated by using a multi-channel DAC, and if the required frequency of the transmission signal is relatively high, up-conversion is required to be performed by matching with a phase-locked loop local oscillator or the like. An FPGA (programmable logic device) controls a plurality of DACs or a plurality of channels of the DACs to generate baseband subcarrier signals of the LFM, and the baseband subcarrier signals are mixed with a phase-locked local oscillator source to generate high-frequency multichannel MIMO transmitting subcarriers. The conventional DAC-based OFDM-LFM signal generation scheme suffers from several drawbacks: (1) The signal link is longer, an additional vibration source is needed, and the complexity is higher; the traditional OFDM-LFM signal generation scheme based on DAC needs FPGA control and a reference signal source (usually more than GHz) with higher frequency, and meanwhile, an additional up-conversion link and a local oscillator source are needed for generating the high-frequency signal with the frequency above the S band, when the number of channels is more, the number of devices of the up-conversion link is greatly increased, and the consistency is difficult to ensure. (2) the resource consumption is high; the traditional DAC-based OFDM-LFM signal generation scheme needs multiple independent DAC signal generation channels, meanwhile, an FPGA is needed for waveform storage and parameter control (additional memory chips are needed to be added for waveform long-term storage), and particularly under the condition that the number of channels is more, the requirements can be met by combining a plurality of digital boards, the size and the power consumption are often larger, and meanwhile, the cost is also greatly increased. (3) the presence of an environmentally-friendly short panel; the common digital devices such as high-frequency DAC and high-speed FPGA are generally commercial or industrial devices, the stable working temperature range is-40-85 ℃, and the self power consumption is large, so that unstable working can occur at the temperature above 60 ℃.

Disclosure of Invention

In order to solve the technical problems, the invention provides an OFDM-LFM signal generating circuit based on a phase-locked loop (PLL), which solves the defects of higher complexity, high resource consumption, poor environmental adaptability and the like of the traditional DAC generating method. Generating subcarriers of the LFM using a plurality of sigma-delta fast modulation based fractional frequency PLLs; the high-stability crystal oscillator is adopted, and the phase relativity of each channel is ensured by using power distribution as a reference clock of the PLL; and a singlechip is used as a control core to send waveform control parameters and transmit trigger signals to the PLL.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

an OFDM-LFM signal generating circuit based on a phase-locked loop comprises a singlechip, a plurality of decimal frequency division PLL based on sigma-delta fast modulation and a crystal oscillator;

the singlechip is used as a control core to directly control a plurality of decimal frequency division PLLs based on sigma-delta fast modulation, and issues waveform control parameters and emission trigger signals for the plurality of decimal frequency division PLLs based on the sigma-delta fast modulation;

The crystal oscillator is used for generating a clock signal, distributing power to the clock signal to output a plurality of reference clock signals, and inputting the plurality of reference clock signals into a plurality of decimal frequency division PLLs based on sigma-delta fast modulation in a one-to-one correspondence and parallel manner;

and the plurality of decimal frequency division PLL based on sigma-delta fast modulation receive a plurality of reference clock signals of the crystal oscillator after power distribution, and generate a plurality of OFDM-LFM sub-carriers meeting the waveform and time sequence requirements according to waveform control parameters and transmitting trigger signals issued by the singlechip.

The invention has the beneficial effects that:

1) The invention uses a plurality of PLLs as cores to generate LFM subcarrier signals, controls a PLL register through a singlechip to realize waveform issuing and playing, and uses a unique crystal oscillator as a reference signal through power distribution to enable the PLLs to keep phase synchronization. The new design concept greatly reduces the complexity of the MIMO radar adopting the OFDM-LFM signal system, and is particularly beneficial to the application of the multichannel MIMO radar.

2) Compared with the traditional DAC mode, the invention can directly generate the high-frequency signal without up-conversion processing such as frequency multiplication, frequency conversion and the like, and has obvious advantages in link simplicity under the condition of more subcarriers.

3) The invention has less requirements on digital control resources, only needs to carry out register configuration on the PLL, and does not need to store complex waveform data in advance, so that the invention can be realized by adopting a mature low-cost singlechip, and saves resources compared with a control mode of an FPGA.

Drawings

Fig. 1 is a schematic diagram of an OFDM-LFM signal generating circuit based on a phase locked loop according to the present invention;

Fig. 2 is a schematic diagram of generating OFDM-LFM subcarriers based on the inventive circuit.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, a schematic diagram of an OFDM-LFM signal generating circuit based on a phase-locked loop (PLL) according to the present invention, which generates subcarriers of an LFM (i.e., MIMO transmit subcarrier 1, MIMO transmit subcarrier 2,..mimo transmit subcarrier n) using a plurality of fractional-division PLLs (PLL 1, PLL2,.. PLLn) based on sigma-delta fast modulation; generating a clock signal by adopting a high-stability crystal oscillator, performing power distribution on the clock signal to output a plurality of reference clock signals, and taking the plurality of reference clock signals as reference clocks of a plurality of fractional frequency division PLLs (phase locked loops) to ensure the relativity of all channels; a singlechip is used as a control core, and waveform control parameters and transmitting trigger signals are issued to a plurality of fractional frequency PLLs. The specific configuration of the phase-locked loop and the singlechip and the OFDM-LFM generation mode are sequentially introduced.

1 Phase Locked Loop (PLL)

With continued reference to fig. 1, a fractional frequency PLL, i.e. a phase locked loop, is mainly composed of a phase frequency detector 1 (PFD), a loop filter 2 (LPF), a voltage controlled oscillator 3 (VCO) and a sigma-delta frequency divider 4. The working principle of the frequency divider is consistent with that of a traditional fractional frequency division PLL, namely an oscillation frequency is generated by a voltage-controlled oscillator VCO, the oscillation frequency is divided by a sigma-delta frequency divider after output, and a crystal oscillator reference signal is input into a PFD at the same time, and the PFD outputs an electric signal (a current signal is output by a charge pump in common at present) through comparing the frequency and the phase difference of the two signals, and the electric signal is converted into a voltage signal through LPF filtering to control the VCO to change the frequency of the VCO. This forms a negative feedback loop where the VCO output will settle and its accuracy and stability of the output frequency will lock onto the reference frequency.

Conventional PLLs can only generate dot frequency or frequency step signals, and are generally used as variable frequency local oscillators. The generation of the chirp signal requires the use of a DAC, DDS, or the like, but the system has high complexity and large power consumption. The decimal frequency division PLL can be used for modulating the sigma-delta frequency divider in a digital control mode to rapidly change according to requirements, so that an output signal is increased or decreased at a high speed to form Linear Frequency Modulation (LFM) signal output. The method can utilize the phase-locked loop to generate the LFM signal with high frequency, large bandwidth and good linearity on the premise of not adding additional devices.

2, Singlechip

Because the digital control part required by the invention is simpler, only the register of the fractional frequency division PLL is required to be read and written, the corresponding control word is written into the fractional frequency division PLL according to different subcarrier waveform data, and the working state of the fractional frequency division PLL can be inquired, and the resource requirement is less, so that the invention can be completed by adopting a mature low-cost singlechip. In the conventional scheme, the waveform file of the DAC needs to be separately stored in an additional storage device, and meanwhile, the waveform configuration of the DAC needs to be supported by a large logic resource, so that the DAC is generally controlled by an FPGA.

3, OFDM-LFM waveform generation

As shown in fig. 2, a schematic diagram of the subcarrier of the OFDM-LFM generation of the present invention is given, in which the horizontal axis represents the signal generation time t and the vertical axis represents the signal frequency f of each transmission subcarrier. Transmitting subcarrier 1, transmitting subcarrier 2,. Transmitting subcarrier n has consistent pulse repetition times, fromIn turn to/>While the frequency bands of the transmitted subcarriers 1 to n are/>, respectivelyTo/>The center frequencies are different, and the bandwidths are the same but do not overlap. So that it only needs to generate a saw tooth chirp signal of the same frequency for each PLL. Through reasonable frequency band division, LFM signals generated by each PLL correspond to OFDM signal subcarriers to jointly form an OFDM-LFM signal.

The method utilizes the advantage of the PLL to generate the high-frequency signal, directly generates the radio frequency LFM signal required by transmission, and solves the technical problem that the traditional method has complex links because the DAC can only generate the low-frequency baseband signal and up-convert the signals in the modes of frequency multiplication, frequency mixing and the like when generating the high-frequency signals above the S wave band.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.

Claims (2)

1. The OFDM-LFM signal generating circuit based on the phase-locked loop is characterized by comprising a singlechip, a plurality of decimal frequency division PLL based on sigma-delta fast modulation and a crystal oscillator;

the singlechip is used as a control core to directly control a plurality of decimal frequency division PLLs based on sigma-delta fast modulation, and issues waveform control parameters and emission trigger signals for the plurality of decimal frequency division PLLs based on the sigma-delta fast modulation;

The crystal oscillator is used for generating a clock signal, distributing power to the clock signal to output a plurality of reference clock signals, and inputting the plurality of reference clock signals into a plurality of decimal frequency division PLLs based on sigma-delta fast modulation in a one-to-one correspondence and parallel manner;

and the plurality of decimal frequency division PLL based on sigma-delta fast modulation receive a plurality of reference clock signals of the crystal oscillator after power distribution, and generate a plurality of OFDM-LFM sub-carriers meeting the waveform and time sequence requirements according to waveform control parameters and transmitting trigger signals issued by the singlechip.

2. The phase-locked loop based OFDM-LFM signal generating circuit according to claim 1, wherein each of the plurality of sigma-delta fast modulation based fractional-division PLLs comprises a phase frequency detector, a loop filter, a voltage controlled oscillator and a sigma-delta frequency divider, wherein an oscillation frequency signal generated by the voltage controlled oscillator is outputted and then divided by the sigma-delta frequency divider, and an electrical signal outputted after the phase frequency detector is inputted simultaneously with a crystal oscillator reference clock signal and then is filtered by the loop filter and converted into a voltage signal, and the voltage signal controls a frequency change of the voltage controlled oscillator.