CN220020189U - DDS of ku to Ka wave band of large instantaneous bandwidth - Google Patents

Abstract

The utility model relates to the technical field of electronic information, and particularly discloses a DDS with ku-Ka wave bands and large instantaneous bandwidth, which comprises a clock input assembly, a network port chip, a 16-bit DAC, FPGA, X frequency multiplier and a switch filter bank, wherein the network port chip is electrically connected with an FPGA, the 16-bit DAC is electrically connected with the FPGA, the X8 frequency multiplier is electrically connected with the FPGA, the switch filter bank is electrically connected with the X8 frequency multiplier, and the output end of the clock input assembly is respectively electrically connected with the FPGA and the 16-bit DAC. The DDS signals of 18-40 GHz can be generated, the frequency modulation signals with the instantaneous bandwidth larger than 4GHz are generated, the frequency modulation signals with the instantaneous bandwidth of 2GHz are generated based on the mode of FPGA and 16-bit DAC, and the frequency spreading from the baseband signals of 2-5 GHz to the millimeter wave signals of 18-40 GHz is realized.

Description

DDS of ku to Ka wave band of large instantaneous bandwidth

Technical Field

The utility model relates to the technical field of electronic information, in particular to a DDS with ku-Ka wave bands and large instantaneous bandwidth.

Background

At present, the method is mainly applied to the fields of communication, navigation, radar remote control and remote measurement and electronic countermeasure in the fields of wide relative bandwidth, short frequency conversion time, high frequency resolution, continuous output phase, broadband orthogonal signals and other complex modulation signals.

However, in the prior art, the phase continuity cannot be realized, the frequency modulation speed is low, the complex frequency modulation signal is difficult to process, the later secondary development and upgrading are not easy to realize, the frequency stability of the traditional analog signal generator is poor, the reliability is poor, the function is single, and the modulation of complex waveforms cannot be realized.

Disclosure of Invention

The utility model aims to provide a DDS with a ku-Ka wave band and a large instantaneous bandwidth, which aims to solve the technical problems that in the prior art, phase continuity cannot be realized, the frequency modulation speed is low, complex frequency modulation signals are difficult to process, later development and upgrading are difficult to realize, and the traditional analog signal generator has poor frequency stability, poor reliability and single function and cannot realize modulation of complex waveforms.

In order to achieve the above purpose, the DDS with ku to Ka wave bands with large instantaneous bandwidth adopted by the utility model comprises a clock input assembly, a network port chip, a 16-bit DAC, FPGA, X frequency multiplier and a switch filter bank, wherein the network port chip is electrically connected with the FPGA, the 16-bit DAC is electrically connected with the FPGA, the X8 frequency multiplier is electrically connected with the FPGA, the switch filter bank is electrically connected with the X8 frequency multiplier, and the output end of the clock input assembly is respectively electrically connected with the FPGA and the 16-bit DAC.

The DDS with the ku-Ka wave band with the large instantaneous bandwidth further comprises a 64bits_DDR3 memory, and the 64bits_DDR3 memory is electrically connected with the FPGA.

The clock input assembly comprises a medium phase-locked oscillator and a phase-locked loop, the phase-locked loop is electrically connected with the FPGA, and the output end of the medium phase-locked oscillator is electrically connected with the phase-locked loop and the 16-bit DAC respectively.

The DDS with the ku-Ka wave band with the large instantaneous bandwidth has the beneficial effects that: the method can generate a DDS signal of 18-40 GHz, generate a frequency modulation signal with instantaneous bandwidth larger than 4GHz, generate a frequency modulation signal with instantaneous bandwidth of 2GHz based on the mode of adding the 16-bit DAC by the FPGA, and realize the spread spectrum from a 2-5 GHz baseband signal to a 18-40 GHz millimeter wave signal.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of the structure of a ku to Ka band DDS with a large instantaneous bandwidth according to the present utility model.

1-medium phase-locked oscillator, 2-phase-locked loop, 3-network port chip, 4-16 bit DAC, 5-FPGA, 6-X8 frequency multiplier, 7-switch filter bank, 8-64bits_DDR3 memory.

Detailed Description

Referring to fig. 1, the present utility model provides a DDS with ku-Ka band having a large instantaneous bandwidth, which includes a clock input component, a network port chip 3, a 16-bit DAC4, an FPGA5, an X8 frequency multiplier 6, and a switch filter bank 7, wherein the network port chip 3 is electrically connected with the FPGA5, the 16-bit DAC4 is electrically connected with the FPGA5, the X8 frequency multiplier 6 is electrically connected with the FPGA5, the switch filter bank 7 is electrically connected with the X8 frequency multiplier 6, and the output end of the clock input component is respectively electrically connected with the FPGA5 and the 16-bit DAC 4.

Further, the DDS with ku to Ka bands with large instantaneous bandwidth further includes a 64bits_ddr3 memory 8, and the 64bits_ddr3 memory 8 is electrically connected to the FPGA 5.

Further, the clock input assembly includes a dielectric phase-locked oscillator 1 and a phase-locked loop 2, the phase-locked loop 2 is electrically connected with the FPGA5, and an output end of the dielectric phase-locked oscillator 1 is electrically connected with the phase-locked loop 2 and the 16-bit DAC4 respectively.

In this embodiment, during operation, firstly, a network port receives a signal generated command and data issued by a terminal, the PFGA is internally embedded with the NIOS to receive and analyze message data, main parameters include a start frequency, an end frequency, a scanning time and a repetition period, a multi-phase NCO module in the FPGA5 generates I, Q two paths of orthogonal signals, the digital intermediate frequency signal generated by the PFGA is sent to the 16-bit DAC4 through the JESD204B, the two paths of signals are output by the multi-phase NCO in the PFGA to adjust, thereby controlling the modulation directions of the digital intermediate frequency signal generated by the FPGA5 and the 16-bit DAC4, the digital NCO in the 16-bit DAC4 can modulate a baseband signal to a required output signal frequency of the 16-bit DAC4, the NCO frequency in the utility model is set to be 2.5-3.5 GHz, and the 16-bit DAC4 uses an NCO modulation function to realize frequency shifting;

the linear frequency modulation signal generating circuit is designed in the FPGA5, so that typical output signals required by a module can be generated, custom waveform data can be downloaded to the 64bits_DDR3 memory 8 by a terminal computer, custom arbitrary waveforms are generated by reading the custom data by the FPGA5, the 16-bit DAC4 working clock is calculated by 5GHz, the speed of the 64bits_DDR3 memory 8 is 5/4=1.25 GHz, and the clock speed of the DDR3 circuit is 1866MHz, so that the requirements can be met;

in order to generate 2.5 GHz-5 GHz linear frequency modulation signals, by utilizing the modulation function of DAC digital NCO, the FPGA5 generates 0-500 MHz digital intermediate frequency signals by utilizing multiphase NCO, the DAC digital NCO is set to be 2-5 GHz, and the modulation directions of the digital intermediate frequency signals and the DAC digital NCO produced by the FPGA5 are controlled, so that 2GHz instantaneous bandwidth signal generation in the frequency range of 2 GHz-5 GHz is realized;

the method comprises the steps of inputting an external 100MHz clock, generating a 5GHz signal through the medium phase-locked oscillator 1, providing clocks for the FPGA5 and the 16-bit DAC4, sending a control instruction to the FPGA5 through the network port chip 3 by an external network, processing the instruction by the FPGA5, controlling the 16-bit DAC4 to output a baseband signal according to an algorithm, downloading custom waveform data by a terminal computer to be stored in the 64bits_DDR3 memory 8, processing the instruction by the FPGA5 to read the custom data to generate a custom arbitrary waveform, generating a baseband signal of 2-5 GHz by the 16-bit DAC4, spreading the baseband signal to 16-40 GHz by the X8 frequency multiplier 6, and carrying out sectional filtering on the 16-40 GHz signal by the switch filter bank 7 to inhibit spurious and harmonic waves, thereby realizing output and amplification of the 16-40 GHz signal.

The above disclosure is only a preferred embodiment of the present utility model, and it should be understood that the scope of the utility model is not limited thereto, and those skilled in the art will appreciate that all or part of the procedures described above can be performed according to the equivalent changes of the claims, and still fall within the scope of the present utility model.

Claims (3)

1. A DDS of ku to Ka band of large instantaneous bandwidth, characterized in that,

the digital signal processing device comprises a clock input assembly, a network port chip, a 16-bit DAC, FPGA, X frequency multiplier and a switch filter bank, wherein the network port chip is electrically connected with the FPGA, the 16-bit DAC is electrically connected with the FPGA, the X8 frequency multiplier is electrically connected with the FPGA, the switch filter bank is electrically connected with the X8 frequency multiplier, and the output end of the clock input assembly is electrically connected with the FPGA and the 16-bit DAC respectively.

2. A ku-to-Ka band DDS of large instantaneous bandwidth as set forth in claim 1,

the DDS from ku to Ka wave band with large instantaneous bandwidth further comprises a 64bits_DDR3 memory, and the 64bits_DDR3 memory is electrically connected with the FPGA.

3. A ku-to-Ka band DDS of large instantaneous bandwidth as set forth in claim 2,

the clock input assembly comprises a medium phase-locked oscillator and a phase-locked loop, the phase-locked loop is electrically connected with the FPGA, and the output end of the medium phase-locked oscillator is electrically connected with the phase-locked loop and the 16-bit DAC respectively.