JP2001331236A - Digital type programmable spectrum clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital type spread spectrum clock generator capable of reducing jitter. SOLUTION: This generator is constituted of a digital waveform generator (20) adapted for generating the sequence of digital words indicating a preliminarily decided variable waveform and an accumulator (21). The accumulator includes a first two-input adder and a second two-input adder, and the second adder is provided with an output stored so as to be supplied to the first input of the second adder, and the first two-input adder is adapted for receiving a control word by the first input, and for receiving the sequence of the digital words by the second input, and for providing the added output, and the output is supplied to the second input of the second adder. One of the output bits of the second adder is made available as a spread spectrum clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital programmable spread spectrum clock generator for generating a clock signal with a defined lower spectral density to reduce electromagnetic interference with very low noise and jitter. Regarding the realization of.

[0002]

2. Description of the Related Art Today's electronic products exhibit increasingly higher performance as new and individual digital technologies are introduced, causing problems for both consumers and businesses. As products become faster and more complex, electromagnetic interference (EM
The amount of radiated electromagnetic waves increases in the form of I (Electromagnetic Interference). One type or another type of processor is often an integral part of an electronic device or device. The processor is a microprocessor (μP) and a digital signal processor (DSP)
r) or microcontroller (μC: Microcontrolle
Regardless of r), each requires one or more synchronization clock signals.

The performance of devices using these processors has increased very rapidly, and currently state-of-the-art devices, such as high-performance personal computers (PCs), use processors with performance of 200 MHz or higher. I have. Clock speeds of 60-100 MHz are required for this type of equipment. However, 30-40
Even μP with clock speeds in the MHz range are common today for digital electronics.

In the United States, the Federal Communications Commission (FCC)
l Communications Commission) sets and enforces maximum allowable EMI levels. These regulations are becoming more stringent with new equipment expected to exceed 1 GHz. In Germany, the German Association of Electronics Engineers (VDE: V
erband Deutscher Elektroyechniker) has set EMI limits. Balance of the world
Is Comite International Special Des Pertabations Ra
It follows the radiation standards set by dioelectriques (CISPR). Electronics manufacturers need to meet these standards to be able to sell in markets controlled by these organizations.

[0005] In order to meet governmental limits on EMI emissions, several methods have been used to minimize EMI levels. Common methods of reducing EMI in electronic devices include providing shielding, careful signal path considerations, slowing clock rise and fall times, and filtering. However, each has issues such as price, required space and required engineering time.

[0006] Spread-spectrum (SS), a crystal-controlled oscillation, proves to be an effective solution for providing a reliable clock with reduced emissions to current and new high-performance electronics. It has become. Spread-spectrum techniques intentionally "broadband" a signal, which is usually narrowband, and spread the energy contained in the signal over a wider bandwidth. A frequency domain representation of an unmodulated narrowband input clock and a modulated "spread" wideband output clock signal is shown in FIG. US Patent No. 5,491,4
No. 58, entitled "Apparatus and method for spreading signal spectrum" (APPARATUS FOR SPREADING THE SP
ECTRUM OF A SIGNAL AND METHOD THEREFOR), 1996
With reference to the February 13, 2008 publication, a phase modulation for spreading the spectrum of the emitted radiation of a clock signal is described.

The spread spectrum oscillator uses a phase lock loop (PLL) technique to obtain a wide dispersion and crystal accuracy at a high frequency such as 135 MHz. Frequency modulation (FM) has been used to spread the clock signal. For a discussion of this method, see "Spread Spectrum Clock Generation to Reduce Emitted Radiation," Hardin, Fessler, and Bush.
h) Author, IEEE International Symposium on Electromagnetic Compatibility, pp. 227-231, Catalog No. # 9
4CH3347-2, ISBN0-7803-1398
-4. EMI is reduced at the center frequency by "spreading" the bandwidth of the clock signal, effectively reducing the EMI measured at the specified frequency. Note that the total radiant energy, or EMI, remains unchanged, however, being "spread" over a wider bandwidth than the original narrowband signal.

There are several ways to implement the spectral variance, or spread spectrum, of a signal. Both frequency and phase modulation are used. However, where low jitter is required, frequency modulation provides a preferred solution. For electronics, there are two commonly used techniques that use frequency modulation on spread spectrum oscillation to reduce EMI without degrading clock performance: 1) Divider modulation And 2) direct modulation of the voltage controlled oscillator (VCO). Both techniques use a PLL to generate a frequency modulated clock.

Both of these techniques use a PLL and are well known in the art and will only be briefly described here. The PLL is a circuit that synchronizes an output signal with a frequency and a phase with reference to an input signal. P
For a more detailed description of LL, see Linear PLL, Roland
Roland E. Best, Chapter 2, Phase-Locked Loops: Design, Simulation and Application, McGraw-Hill, Third Edition, 1997.

A spread spectrum clock generator (SSCG) showing the two techniques described above.
k generator) is shown in Fig. 2 in the sense of comparison.
Is shown in Both technologies use a VCO 10. In both techniques, a clock input 12 is provided to an input of a phase detector (PD) 14. The output of the phase detector 14 is a loop filter (F) 1
6. In the first technique, the output of the loop filter 16 is supplied to the VCO 18. In the second technique, the output of the loop filter 16 is supplied to an adder 20, and the other input of the adder 20 is a frequency modulator 2
2 which provides a variable voltage corresponding to the frequency modulation of VCO 18 and, together with the output of adder 20,
18 inputs. In both cases, V
The output of CO18 is the output of SSCG, and the divider (D
IV) The input of the phase detector 14 is supplied to an input of the phase detector 14, and the output of the divider 24 is supplied to another input of the phase detector 14. However, in the second technique, the frequency modulator 26 modulates the output frequency of the divider 24. PD 14 compares the frequency and phase of the input clock waveform with the output waveform from VCO 18 and indicates whether the error signal indicates that the feedback signal is behind or ahead of the reference input signal and is proportional to the phase difference between the two signals. Generated in the form of a series of pulses having a width.

In step F16, unnecessary harmonic components are removed from the PD error signal by a filter, and the voltage level of the input signal is integrated. The resulting output signal is then provided to VCO 18 as a control signal. The VCO 18 control signal is adjusted with a positive or negative signal, which is repeated until the output of VCO 18 matches the input clock signal. VCO18
Is set to oscillate at the specified frequency,
This depends on the output clock frequency required by the system. If this frequency is greater than the input or reference frequency, the PLL will appear to multiply the output by its frequency. In this case, a divider is needed in the feedback circuit from the VCO output to the PD, to reduce its frequency back to the original input signal.

Therefore, two common prior art electronics techniques that modulate the SSCG output from the PLL and also to achieve reduced emissions are: 1) PLL and frequency modulation and summing of the VCO input signal. SSC used
G, and 2) SSCG using frequency modulation of a PLL and a divider. The first detailed description of these two techniques is found in U.S. Pat. No. 5,488,627, entitled "Spread Spectrum Clock Generator and Related Methods",
It is described in the January 30, 1996 issue. This technique is hereafter referred to as the direct modulation of the VCO (DIR.MOD.) Method.

A second, more detailed description of these two techniques is found in the literature titled "Frequency Modulation of the System Clock for EMI Reduction", Cornelis D. Hoekstra, Hewlett-Packard Journal (Hewlett-Packard Journal), 1997
August issue, Reference 13, pages 1-7.
This technique has since become known as divider modulation (DIV.MO).
D. ) Called the law.

In order to understand the background of the present invention, DIR. MOD. It is instructive to note that the method capacitively adds the modulating signal onto the input signal to the VCO. This method works effectively when the modulation frequency exceeds 2X times the natural loop PLL loop bandwidth. When the modulation frequency greatly exceeds the PLL bandwidth,
The output frequency deviation (spectral width) can be approximated as:

[0015]

(Equation 1) Where K _v is the sensitivity of the VCO in Hz / v, F _FTER is the transfer function of the modulation port to the VCO input line in voltage / voltage, and V _FMOD is the modulation signal in voltage.

If the modulation frequency is less than one half of the loop bandwidth, the loop adjusts and removes a large portion of the applied modulation. Therefore, the desired peak deviation is reduced. Also, temperature, semiconductor manufacturing process, and other variables have an adverse effect on output. This is a significant drawback with this type of spread spectrum method because SSCG designs typically use modulation frequencies in the range of 30 to 200 KHz. This range is inside the loop bandwidth of many PLLs included in complex LSI integrated circuits. Typical loop bandwidths of 1 MHz or more are common in low phase noise integrated circuit PLLs. DI
R. DIR. The technique produces symmetric modulation and cannot produce the one-sided FM needed to maintain set-up and margin in timing-critical circuits. This restriction is solved by shifting the offset center frequency. However, in many cases this is not an option due to system requirements, and generating unique frequencies is expensive. This also tends to increase jitter.

The divider modulation (DIV.MOD.) Method is P
The divider in LL is modulated to obtain the desired spread spectrum. As an example, if the divider is originally set to N = 10 and the input reference frequency is 1 MHz, then the output frequency should be set to the VCO as 10 MHz.
Here, if the divider is changed to 9, the frequency output becomes 11.
It should be 11 MHz. Therefore, the divider N = 1
When modulated back and forth with a 100 KHz square wave between 0 and N = 9, the output of the PLL is 10 and 11.11 MHz.
Should circulate at a rate of 100 KHz. The generated spectrum is centered at 10.555 MHz and has a number of 100 KHz offset sidebands. The flexibility of this method of selecting the desired frequency output is a problem. As can be seen, the modulation is limited to two integers, in this case between 9 and 10. If another frequency that cannot be obtained by these integers is specified, another PLL is required, which causes an unnecessary increase in price.

[0018] Often, spread spectrum clock systems have input clock frequencies that are determined by inexpensive crystal oscillators, and are not comparable or DIV. MO
D. Requires a specific spread spectrum output frequency that is easily obtained by the method. As an example, if the required spread spectrum clock output is 66 MHz and the input is 1 MHz and the peak-to-peak frequency deviation is 4 MHz, the PLL divider cannot change the integers to fulfill these requirements.

DIV. MOD. The method can be thought of as a square wave modulation because the PLL is required to jump from one frequency to another instantaneously. However, the actual PLL does not respond instantaneously. The resulting frequency modulation waveform is spectrally flatter than square wave frequency modulation.

As is known, inter-period jitter has a range of 0.5% to 2% in practical designs. This is too expensive for some systems. Thus, triangular wave modulation, rather than square wave modulation, has been attempted with some success in reducing jitter.

The purpose of the SSCG clock output is to approach 0% jitter. The less jitter in the SSCG method, the longer the designer can tolerate the delay before re-clocking the system. DIV. MOD. Modulo 0.
Even if jitter less than 5% can be achieved, a significant improvement as shown in the present invention is desirable.

[0022]

SUMMARY OF THE INVENTION The present invention provides a digital spread spectrum
Provide a clock generator. The generator includes a digital waveform generator and an accumulator adapted to generate a sequence of digital words representing a predetermined variable waveform. The accumulator includes a first two-input adder and a second two-input adder, the second adder storing its output and supplying it to a first input of the second adder. The first two-input adder is adapted to receive a control word at its first input, receive a sequence of digital words at a second input, and provide an added output, which is the second adder. A second input is provided. One of the output bits of the second adder is available as a spread spectrum clock and may be provided to a phase locked loop to reduce jitter.

Accordingly, the present invention provides a digitally programmable spread spectrum clock generator (SSCG), which has a very low noise or jitter E
Generate an accurate output waveform with low spectral density for MI reduction. In addition, being programmable allows real time accuracy, independent settings, or changes in output center frequency, peak deviation and modulation frequency via software without changing hardware or software. In many digital systems, some embodiments of the present invention are operable over a wide temperature range from -40C to + 150C.

[0024] These and other features of the present invention will become apparent to those skilled in the art from the following detailed description of the invention when taken in conjunction with the accompanying drawings.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment of the present invention provides a digital spread spectrum clock generator system that reduces EMI while increasing jitter. The system is digital and can be accurately programmed in real time. The center frequency, peak deviation and modulation can be set independently or can be changed via software without changing hardware or other components. The advantages of this system, even if it's digital, stand out from other approaches: The ability to more accurately set the SSCG output center frequency, peak deviation and modulation frequency. 2. Ability to generate spread spectrum clocks with very low jitter. 3. The ability to digitally program the center frequency, peak deviation and modulation frequency independently in real time. 4. Ability to operate over a wide temperature range (up to 150 ° C.) because the described SSCG does not use D / A converters and reconstruction filters.

A simplified block diagram of the preferred embodiment is shown in FIG. SSCG is composed of three basic functional blocks: a modulator (M) 20 and an accumulator (AC).
C) 21 and a phase lock loop (PLL) 22. Reference source 23, referred to as input clock _FCLK , is generated from an external source, such as a crystal oscillator, or from another PLL. This input clock _FCLK is supplied to both the modulator 20 and the accumulator 21. Modulator 20 generates a sequence of digital words representing a triangular waveform from input clock _FCLK , the frequency of which is programmed with a frequency modulation control word. Although other waveforms can be generated in accordance with the principles of the present invention, triangular waveforms are relatively easy to generate and provide favorable spread spectrum performance. For example,
As other waveforms, a rectangular wave or a trapezoid symmetrical to the central axis can be used. In order to generate such other waveforms, the modulator 20 needs to be suitably modified, but such modifications will be obvious to those of ordinary skill in the art. In all such cases, the purpose is to obtain a periodically changing waveform.

The modulator 20 output is then combined with the output frequency control and output frequency deviation control words. The result is provided to an accumulator 21 which produces an unfiltered spread spectrum clock in the form of a sequence of K-bit words. Finally, the most significant bit (MSB) of each K-bit word, which contains the required frequency information from accumulator 21, is supplied to PLL 22, which operates to remove jitter from the signal, Provides a spread spectrum signal to the system with low EMI and very low jitter.

(Reference Source) As described above, the reference source 2
3, or input clock _FCLK, is an input signal from another function in the system, such as a crystal oscillator, another PLL, or the like. This is generally less expensive and it is more practical to use signals already available in the system. The frequency of the reference source 23 is preferably at least four times the center frequency of the desired spread spectrum output. This minimizes distortion due to insufficient sampling rate.

(Modulator) A functional block diagram of the modulator 20 is shown in FIG. Modulator 20 comprises three functional blocks: a programmable N-bit counter 30, a fixed M-bit counter 31, and a triangular address generator 32. Programmable counter 30 receives input clock F
Count in response to _CLK and therefore at that rate. It also divides the frequency of the input clock _FCLK to a lower defined frequency, and the resulting divided clock is subsequently provided to the fixed counter 31. The exact frequency of the programmable counter output is controlled by a 4-bit digital frequency modulation control word provided to the frequency modulation control input.
This word determines the intensity of the counting step of the N-bit counter, and thus the frequency of the resulting output. Typical values of the frequency divider range from 2 to 16. However, for high frequency clock inputs, a larger divider is required to obtain the desired frequency.

The second section of modulator 20 is a fixed counter 31, which converts the serial clock from programmable counter 30 into a parallel digital binary signal.
Convert to word. This binary word counts from a minimum to a maximum at a rate proportional to the input serial clock from programmable counter 30 divided by the number of states in fixed counter 31. In addition, the fixed counter digital word changes so that the next state is one count greater than the previous state. This digital pattern repeats in the fixed counter until it reaches a maximum value, at which point the counter is reset to a minimum value. The value of the digital binary sequence generated by the fixed counter is commonly known as a sawtooth pattern.

The final section triangular address generator 32
Converts a sawtooth binary word sequence to a triangular binary
Convert to word sequence. The operation is implemented with an array of exclusive-OR gates and occurs at either a maximum or minimum value depending on the particular circuit implementation. The output of the triangular address generator 32 is the output of the modulator 20 and is supplied to the accumulator 21 in FIG.

There are various ways to generate a triangular binary word sequence. The particular modulator embodiment shown in FIG. 4 has a reference source input, a reference clock _FCLK , which is provided to an N-bit programmable counter 30. The frequency modulation control pins S0, S1, S2 and S3 of the programmable counter 30 are set to a binary word having a numerical value designated FMC. Fixed counter 3
1 is an M-bit counter.

The resulting modulation frequency is determined by the following equation:

[0034]

(Equation 2) As an example, F _CLK = 132 MHz, M = 6, N = 4
FMC = 9; F _MOD = 149,659 Hz.

(Accumulator) A simplified functional block diagram of the accumulator 21 of FIG. 3 is shown in FIG. The accumulator 21 is made up of three basic functional blocks: a first K-bit adder 40, a second K-bit adder 41, and a clocked register 42. The accumulator 21 is dynamically driven by an M-bit triangular word output obtained by dividing the input frequency output from the modulator 20, that is, the frequency of _FCLK .
1 the output of the accumulator 21 is made in the form of 2 ^K, thus the minimum frequency F _OUT of the output signal F _OUT of accumulator 21 (mi
n. ) Is:

[0036]

(Equation 3)

The accumulator 21 stores a predetermined number of states in F
Digital skip so as to skip at each clock edge of _CLK.
Word programmed. The skip state reduces the number of states for each cycle of the accumulator output F _OUT , thus increasing the accumulator output frequency. In this way, the accumulator output frequency changes in a controllable and programmable manner.

The inputs to the accumulator 21 are: modulator output F _MOD ; reference clock, F _CLK , frequency division control word,
And an output frequency control word. The output frequency control word is provided to a first input of adder 40. Adder 40
The output frequency control word is the output of adder 40 when no input is connected to the other input of or when a zero value is provided. Accordingly, the output frequency control word determines the lowest frequency of the F _OUT. In each clock cycle, the adder 4
This output frequency control word is added to the other input of 0 to produce the output of adder 40. In this way,
The desired deviation is then achieved in the manner described in more detail.

The modulator output is a sequence of M-bit words that define a triangular waveform, ie, periodically
It will be recalled that counting increases from 00000 to 111111 and decreases from 111111 to 000000. Generally, M <K. For example, assume that M is 6. Also assume that K is 16. The 6-bit modulator output word can be provided to any consecutive 6-bit positions of variable bit weights at the second input to adder 40. Accordingly, the output of the adder 40, and thus the amount of dispersion (deviation) of the output clock signal F _OUT , can be controlled by the arrangement of these 6 bits at the second input to the adder 40. For example,
When placed at the position of the lowest bit weight, 6
The bits are placed in bit positions from 0 to 5, while when placed in the position of the highest bit weight, 6 bits of the modulator output become 1
Bits 0 to 15 are placed. Similarly, these bits can be located at any intermediate position. When these bits are placed in higher weight bit positions, the amount of deviation is incremented by 2 each time the bit position at the second input of adder 40 shifts.

The frequency deviation control word provides another control over the deviation of the output clock signal F _OUT , ie, the frequency deviation control bit “fills” the remaining bit positions of the second input of adder 40.

Thus, the 6-bit modulator output F _MOD is selectively placed at the second input to _summer 40 and is combined with the frequency deviation control word to set the desired peak-to-peak deviation of the accumulator output. The result is the output of the first adder 40, PG
M, which is one input of the second adder 41. Second
The output of the adder 41 operates as the output of the accumulator and the input of the register 42. The contents of the register 42 are the second adder 41
As a second input to Therefore, the output of the adder 41 is fed back to the second input of the adder 41.

In understanding the operation of the adder 41, consider the first case where the value stored in the register 42 is zero and the output of the adder 40 is a constant value of one. For feedback, the K-bit adder 41 counts from zero to 2K every clock cycle, then counts back to zero as before, and repeats periodically to establish the lowest frequency of the accumulator. I do. If the output of adder 40 is a value greater than one, counting is skipped in adder 41, thus accelerating the counting cycle and increasing the output frequency of the accumulator. In this manner, the deviation incorporated in the output of adder 40 as described in detail above is provided to the output of adder 41.

The accumulator 21 is thus programmable with a digital word input to the frequency deviation control input and a digital word input to the output frequency control input of the accumulator 21. The accumulator output can be defined as:

[0044]

(Equation 4)

The center frequency of F _OUT can be controlled and changed with high accuracy in real time. The target center frequency is obtained within +/- value defined by Equation 3.

F_OUTThe peak deviation of
Can be controlled and changed within the box. SSCG system described later
The simulation is the center frequency, that is, the output frequency of the accumulator.
Built-in 16 bits for wave number control input, for modulation control
It incorporates 16 bits. 10 of 16 modulation bits
Is fixed and 6 is variable. 6 variable bits are triangle F
_MODThe modulation binar of the second input of the adder 40, including the word
It can be placed anywhere in the Reword. Therefore,
The deviation can be controlled and changed in real time within the range of coefficient 2.
You. For example, if the peak deviation is 100 kHz,
The next lowest peak deviation that can be obtained is 50 KHz.
The highest possible peak deviation is 200 KHz.

The flexibility and precise setting of the preferred embodiment of the present invention provides the ability to set a lower or higher frequency spread spectrum frequency envelope than the unmodulated clock. This ability has the feature of limiting the maximum frequency during modulation, which prevents "setup and hold" violations in clocked systems. In prior art systems, this "band drop" or "band rise" modulation was not possible because the modulation was symmetric about the center frequency. Prior art systems can perform similar modulation only if the new reference frequency, _FCLK, is used as unmodulated.

Other embodiments will modify Equation 4 as desired to achieve the modified purpose.
However, this equation represents a general class of accumulator output.

(Phase Locked Loop) Phase locked loop (PLL) circuits are well known to those skilled in the art.
In this embodiment, the PLL is used to smooth the jitter of the output signal of the accumulator 21. Accumulator output signal F
_Since the most significant bit (MSB) of _OUT has all the necessary information and frequency accuracy, it is of single interest. However, the MSB contains a large amount of phase modulation caused by accumulating phase errors. As a result, the inter-cycle (C2C) jitter in the MSB of the accumulator output is important. Therefore, a tracking PLL is desirable to substantially eliminate this jitter. Between cycles in the MSB of the accumulator output (C2C)
Jitter is 2X the period of the accumulator clock. Therefore,
The higher the accumulator clock, the lower the MSB C2C jitter.

(Simulation of Preferred Embodiment) FIG.
Is simulated, and as a result this SS
The operation of the CG has been confirmed as described herein.

The function settings for the simulation are as follows: Input clock frequency (F _CLK ): 132 MHz PLL output frequency (F _SSC ): 33 MHz Accumulator bit length: 16 bits Frequency deviation: +/− 1. 8 MHz modulator frequency (F _MOD ): 147 KHz modulator bit length 6 bits

FIGS. 6 and 7 show the results of this simulation.
And in FIG.

FIG. 6 shows a spread spectrum clock (SSC).
3 shows an output histogram. x-axis is the frequency of the SSC output signal, y-axis shows the inhibition relative to the input clock signal F _{CL K} of SSC output signal in dB. It will be seen that the unmodulated input clock signal is suppressed at approximately 30 dB and its desired center frequency is 33 MHz. Further, the output spectrum is the specified 147 KH
It has a deviation of z and is essentially flat as desired.

FIG. 7 is a graph of MSB period versus number of clock periods versus output of the accumulator. The output period is correctly 33 MHz on average. However, there are large fluctuations in the period in which the modulator sweeps the input of the accumulator at F _MOD speed (147 KHz). Also, at this point, a large period-to-period jitter exists on the output, which cannot be satisfied.
A PLL is used to reduce jitter.

FIG. 8 shows the simulated PLL output. This is a graph of SSC frequency versus time.
It will be seen that the PLL smoothes the periodic variation of the accumulator MSB signal shown in FIG. 7 and produces a frequency modulated clock that varies at F _MOD speed and has a triangular frequency band time trajectory.

In addition to reducing the power spectral density of the clock signal, the SSCG must perform its operation without adding jitter to its output. FIG. 9 shows S
Figure 4 shows simulated inter-cycle (C2C) jitter of the SCG PLL output. This is very low, approximately +/-
It exhibits 100 ps jitter, is acceptable for most applications and is even smaller than previously known SSCG systems.

Having described the invention and its features in detail, it will be understood that various modifications, insertions and substitutions can be made without departing from the spirit and scope of the invention as defined in the appended claims. I want to.

With respect to the above description, the following items are further disclosed. (1) a digital spread spectrum clock generator, adapted to generate a sequence of digital words representing a predetermined variable waveform, a first two-input adder; A second two-input adder, the second adder having an output stored and applied to a first input of the second adder, wherein the first two-input adder has Receiving a control word at a first input;
A second input adapted to receive the sequence of digital words and to provide a summed output, the output of which is provided to a second input of the second adder for receiving the second word;
An accumulator wherein one of said output bits of an adder is usable as a spread spectrum clock.

(2) The digital spread spectrum clock generator according to (1), wherein the most significant bit of the output of the second adder is usable as a spread spectrum clock. -Clock generator.

(3) The digital spread spectrum clock generator according to (1), wherein the predetermined variable waveform is a triangular wave.

(4) In the digital spread spectrum clock generator according to (1), the number of bits in the word of the predetermined variable waveform is smaller than the number of bits of the first adder, and The plurality of words having a predetermined variable waveform can be supplied to any of a plurality of positions of the variable bit weights of the first input of the first adder.
The digital spread spectrum clock generator.

(5) The digital spread spectrum clock generator according to item (4) further comprises a second input of the first adder to which the word of the predetermined variable waveform is not supplied. A digital spread spectrum clock generator including means for determining a bit value.

(6) The digital spread spectrum clock generator of (1) further comprises a phase locked loop adapted to receive the one of the bits of the output of the second adder. Includes digital spread spectrum clock generator.

(7) A digital spread spectrum clock generator. The generator includes a digital waveform generator (20) adapted to generate a sequence of digital words representing a predetermined variable waveform, and an accumulator (21). The accumulator includes a first two-input adder and a second two-input adder, the second adder having an output stored and provided to a first input of the second adder. First
Is adapted to receive a control word at a first input, a sequence of digital words at a second input, and provide an added output, which output is provided to a second input of the second adder. Have been. 1 of the output bit of the second adder
One can be used as a spread spectrum clock or provided to a phase locked loop to reduce jitter.

[Brief description of the drawings]

FIG. 1 is “frequency domain representation of a clock signal with and without SSCG”.

FIG. 2 is a functional block diagram of a basic spread spectrum clock generator using a PLL and the considered prior art. This block diagram is "Direct modulation of VCO"
(DIR.MOD) method and “divider modulation” (Div.
Mod. ) Method, both of which are considered prior art.

FIG. 3 is a functional block diagram of the SSCG of the present invention. It is digitally programmable in real time.

FIG. 4 is a functional block diagram of a modulator according to the present invention.

FIG. 5 is a functional block diagram of an accumulator according to the present invention.

FIG. 6 is a simulated spread spectrum clock output waveform showing intensity versus frequency. The intensity reference is a reference source or input clock.

FIG. 7 shows the period versus clock period at the most significant bit (MSB) output of the simulated accumulator.

FIG. 8 shows a simulated triangle output from a PLL. This is also the output of SSCG. The axes are frequency and time.

FIG. 9 shows the simulated output from SSCG (and PLL), showing the cycle-to-period (C2C: cycle-
to-cycle) jitter

[Explanation of symbols]

 Reference Signs List 10 PLL 12 Clock input 14 Phase detector 16 Loop filter 18 VCO 20 Modulator (adder: FIG. 1) 21 Accumulator 22 PLL (Frequency modulator: FIG. 1) 26 Reference source 24 Divider 26 Frequency modulator 32 Triangle Address generator 40, 41 Adder 42 Register

Claims (1)

[Claims] 1. A digital spread spectrum clock generator adapted to generate a sequence of digital words representing a predetermined variable waveform, and a first two-input summation. An accumulator that includes an adder and a second two-input adder, wherein the second adder is stored and a first one of the second adder.
An output provided at an input, wherein the first two-input adder receives a control word at a first input, receives the sequence of digital words at a second input, and provides an added output. An accumulator whose output is provided to a second input of the second adder, wherein one of the output bits of the second adder is usable as a spread spectrum clock. Spread spectrum clock generator.