JP2009290733A - Clock generating circuit with frequency modulation function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit with a frequency modulation function which has an excellent spectrum spreading effect, is less in occurrence of noise and can reduce malfunctions in peripheral circuits or electronic components. <P>SOLUTION: The clock generating circuit 1 includes: a PLL circuit 10 which has a feedback frequency divider 17 and outputs a frequency-modulated clock; a band pass filter 20 which extracts only a predetermined frequency from the feedback frequency divider 17 and inputs the extracted frequency to the PLL circuit 10; and a triangular wave generating circuit 40 which generates a triangular wave. The band pass filter 20 functions also as a sine wave generator, generates a sine wave in predetermined timing and combines the sine wave with the triangular wave, thereby changing a frequency dividing ratio of the feedback frequency divider 17. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a clock generation circuit with a frequency modulation function (SSCG: spread spectrum clock generator) that effectively prevents electromagnetic interference (EMI).

  As a clock generation circuit that is built in a logic LSI such as a microcomputer and generates an operation clock signal, there is a circuit that uses a PLL circuit that generates a high-frequency clock signal obtained by multiplying an oscillation signal of a crystal oscillator as a reference clock. In an LSI incorporating a clock generation circuit using such a PLL circuit, there is a risk of causing malfunctions of the computer main body, peripheral circuits, external devices, etc. due to radiation noise from the oscillation circuit as the clock frequency increases. . As a countermeasure against such a situation, a clock generation IC called SSCG is provided in which a spread spectrum function is provided in a PLL circuit to slightly change the frequency of the clock signal. Since the peak value of the frequency spectrum of the clock signal is lowered, radiation noise can be reduced.

  In a general SSCG circuit, the oscillation frequency is changed at a constant period T. Depending on the frequency component, a large number of small peaks occur, and the peak value of radiation noise at a specific frequency increases. There is a possibility that EMI (electromagnetic interference) noise may increase due to composite noise between wirings with other clock signals that are used, etc., leading to malfunction of peripheral circuits and electronic components.

  Therefore, Patent Document 1 discloses a semiconductor integrated circuit that has a good spread spectrum effect and generates less noise and aims to reduce malfunctions of peripheral circuits and electronic components. FIG. 10 shows a semiconductor integrated circuit described in Patent Document 1. In FIG. In FIG. 10, P1 to P3 are external terminals (electrode pads) provided on the semiconductor chip, among which P1 and P2 are terminals to which a vibrator 101 such as a crystal vibrator is connected, and P3 is a generated clock. φ0 is the output terminal.

  The clock generation circuit 110 is coupled to the terminals P1 and P2 to which the vibrator 101 is connected, applies a bias voltage to the vibrator 101, and outputs an oscillation signal that changes at a frequency corresponding to the natural frequency of the vibrator. 111, a fixed frequency dividing circuit 112 that divides the output of the oscillation circuit 111 by M, a phase comparison circuit 113 that detects a phase difference between the frequency division signal of the fixed frequency dividing circuit 112 and a feedback signal, and a current corresponding to the phase difference Charge pump 114, loop filter 115 for smoothing the output of the charge pump 114, voltage controlled oscillation circuit (VCO) 116 for oscillating at a frequency corresponding to the smoothing voltage, and dividing the output of the VCO by N, the phase comparator. The PLL circuit is composed of a frequency dividing circuit 117 that feeds back to 113. A buffer 118 buffers the oscillation output of the VCO and outputs it as a generated clock φ0 from the external terminal P4 to the outside of the chip.

  The clock generation circuit 110 further includes counter circuits 121A and 121B for counting up and down each of the signals divided by the frequency dividing circuit 117 to a predetermined value, and the frequency dividing ratio N of the frequency dividing circuit 117. A fluctuation amount giving circuit 122 that generates a given fluctuation amount ΔN or −ΔN to be applied, and a fluctuation amount ΔN or −ΔN supplied from the fluctuation amount giving circuit 122 to a predetermined frequency division ratio (initial value) N are added. An adder circuit 123 that supplies the obtained frequency division ratio to the frequency divider circuit 117, and a logic circuit 124 that receives the count value of the variable frequency divider circuit 121A or 121B and outputs a signal according to the state of the input. The changeover switch 125 for switching whether the signal divided by the divider circuit 117 is supplied to the counter circuit 121A or 121B, and the variable divider circuit 121 Or selector 126 for selecting whether to input provided any count of 121B to the logic circuit 124.

  The fluctuation amount assigning circuit 122 includes a circuit that generates a predetermined binary code corresponding to ΔN and −ΔN, and a switch or selector that selects which value of the generated code ΔN or −ΔN is output. Therefore, a register or a ROM (Read Only Memory) can be used for the circuit for generating the code. The logic circuit 124 operates as a circuit that outputs a signal that gives the timing to add the variation amount ΔN or −ΔN output from the modulation amplitude adjusting circuit 122 to the frequency division ratio N to the adding circuit 123. It can be configured by a random logic such as a circuit, a ROM, or a combinational circuit whose output is uniquely determined by input. In the case of using a decoder circuit, a plurality of unit decoders whose output is high level or low level for a combination of a plurality of input signals can be used.

  The change-over switch 125 is controlled by the count end signals CE1 and CE2 from the counter circuits 121A and 121B. When the counter circuit 121A counts up to a predetermined number and counts down to “0” again, frequency division is performed. It is switched to supply the signal frequency-divided by the circuit 117 to the counter circuit 121B. When the counter circuit 121B counts up to a predetermined number and counts down again to “0” twice, the counter circuit 121B is switched to supply the signal divided by the frequency divider circuit 117 to the counter circuit 121A.

  Accordingly, the modulation cycle TA and the modulation cycle TB are operated so as to be alternately repeated twice. Further, the selector 126 is switched according to the operation period of the counter circuits 121A and 121B. On the other hand, the selection of whether the fluctuation amount ΔN or −ΔN is output in the fluctuation amount applying circuit 122 is configured to be alternately performed by the count end signals CE1 and CE2 output from the counter circuits 121A and 121B. ing.

  Further, in Patent Document 2, frequency modulation is performed by using a PLL circuit and a modulator, and changing the frequency division ratio of the feedback frequency divider in the PLL circuit according to the modulation data generated based on the modulation profile of the modulator. A clock generation circuit that spreads a spread spectrum by moving a folding point of a modulation profile to disperse a frequency frequency when performing spread spectrum is disclosed. This clock generation circuit is composed of a PLL circuit and a modulator. A multiple modulation profile generation circuit is provided in the modulator, the folding point of the modulation profile is moved, and the frequency frequency is dispersed to respread the spread spectrum. is there.

  Further, Patent Document 3 discloses a clock generator capable of effectively reducing EMI using a spread spectrum clock signal even when a high-speed operation memory is used.

Furthermore, Patent Document 4 discloses a spread spectrum clock generation circuit for the purpose of performing good spread spectrum with a simple configuration. This clock generation circuit generates a frequency phase comparator that detects the phase difference between the reference clock and the generated clock, a charge pump that generates a charge / discharge signal according to the detected phase difference, and generates a difference signal according to the charge / discharge signal A spread spectrum clock generation circuit comprising: a loop filter that performs a spread spectrum modulation circuit that modulates a difference signal to generate a spread spectrum modulation signal; and a clock generator that generates a clock having a frequency corresponding to the spread spectrum signal. The spread modulation circuit generates a spread spectrum modulation signal whose amplitude changes to a plurality of different amplitudes.
JP 2006-2111479 A JP 2006-197308 A JP 2006-333174 A JP 2004-208037 A

  However, in the technique described in Patent Document 1, a plurality of counters must be provided in the SSCG feedback mechanism, which increases the circuit scale. In addition, since the fluctuation of the frequency with respect to time in the feedback mechanism becomes linear, noise may occur.

  Further, in the techniques of Patent Documents 1 to 4, as shown in the spectrum distribution of the generated clock in FIG. 11, a peak occurs at the end on the low frequency side or the end on the high frequency side. EMI (electromagnetic interference) noise may increase due to a large peak value of the signal, or composite noise between wirings with other clock signals used in the system, which may cause malfunction of peripheral circuits and electronic components. is there.

  The clock generation circuit with a frequency modulation function according to the present invention has a feedback frequency divider, outputs a frequency-modulated clock, and extracts only a predetermined frequency from the feedback frequency divider and inputs it to the PLL circuit. And a first waveform generation circuit that generates a first periodic wave having a predetermined period, and the bandpass filter may be used as a second periodic wave generator having a predetermined period. It functions to generate a second periodic wave at a predetermined timing and combine it with the first periodic wave to vary the frequency division ratio of the feedback divider.

  In the present invention, the clock spectrum is obtained by taking out only a predetermined frequency from the feedback frequency divider by the band pass filter and changing the frequency divider by synthesizing the second periodic wave into the first periodic wave. The characteristics can be made more uniform. Furthermore, since the band pass filter and the second periodic wave generator are shared, an increase in circuit scale can be minimized.

  According to the present invention, it is possible to provide a clock generation circuit with a frequency modulation function that has a good spread spectrum effect, generates less noise, and can reduce malfunctions of peripheral circuits and electronic components.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a clock generation circuit with a frequency modulation function according to the present embodiment. The clock generation circuit 1 with a frequency modulation function according to the present embodiment is not particularly limited, but is formed as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon.

  The clock generation circuit 1 according to the present embodiment includes a feedback frequency divider 17 and outputs a frequency-modulated clock, and a PLL circuit 10 that extracts only a predetermined frequency from the frequency divider 17. And a triangular wave generation circuit 40 that generates a triangular wave as a first periodic wave having a predetermined period. The bandpass filter 20 also functions as a sine wave generator that generates a sine wave as a second periodic wave having a predetermined period, generates a sine wave at a predetermined timing, and combines it with a triangular wave to divide the feedback frequency. The frequency dividing ratio of the device 17 is changed.

  The PLL circuit 10 includes an oscillation circuit 11, an M divider (fixed divider circuit) 12, a phase comparator 13, a charge pump 14, a loop filter 15, a voltage controlled oscillator circuit (VCO) 116, and a feedback divider (N Frequency divider) 17. A buffer 18 buffers the oscillation output of the VCO 16 and outputs the generated clock φ0 from the external terminal to the outside of the chip.

  The oscillator 101 is connected to the oscillator 101 and outputs an oscillation signal that changes at a frequency corresponding to the natural frequency of the oscillator. The M divider 12 divides the output of the oscillation circuit 11 by M. The phase comparator 13 detects a phase difference between the frequency-divided signal of the M frequency divider 12 and a feedback signal (a feedback signal corresponding to the oscillation signal). The charge pump 14 outputs an analog signal (current) corresponding to the pulse width of the phase difference signal output from the phase comparator. The loop filter 15 smoothes the analog signal output from the charge pump circuit and outputs a frequency control signal. The voltage controlled oscillation circuit (VCO) 16 outputs an oscillation signal having a frequency corresponding to the smoothed voltage (frequency control signal). The feedback frequency divider 17 divides the output of the VCO 16 by N and feeds it back to the phase comparator 13.

  2A shows the input of the feedback divider 17, and FIG. 2B shows the output of the feedback divider 17. As shown in FIG. FIG. 3 is a characteristic diagram showing the spectrum distribution of the generated clock when no modulation is performed. FIG. 4 is a characteristic diagram showing a spectrum distribution of the output of the frequency divider 17 after modulation, that is, the feedback frequency divider 17. FIG. 5 is a schematic diagram showing the output of the bandpass filter 20. FIG. 6 is a schematic diagram showing a sine wave generated by a sine wave generator, and FIG. 7 is a schematic diagram showing a triangular wave generated by a triangular wave generation circuit 40.

  In the clock generation circuit 1, as shown in FIG. 2, the bandpass filter 20 functions as a bandpass filter for a predetermined period of one clock, and functions as a sine wave generator for a predetermined period. For example, the switch 52 switches the switch at a timing as shown in FIG. When the switch 52 is connected to the output of the feedback frequency divider 17, the bandpass filter 20 functions as a sine wave generator. The generated sine wave is combined with the triangular wave by the adder 54, and the modulation period and the frequency division ratio N of the feedback frequency divider 17 are switched. The selector 55 inputs "0" when resetting, and the register 53 temporarily latches the value of the adder 54. By superimposing a sine wave on a triangular wave and modulating it, a small peak at the peak portion which has been generated conventionally can be made smoother.

  On the other hand, when the switch 52 is connected to the output of the bandpass filter 20, the bandpass filter 20 functions to pass only a predetermined frequency component as shown in FIG. As a result, peaks may appear at the low frequency side end and the high frequency side end indicated by the one-dot broken line A in the spectrum characteristics, but these portions can be removed. That is, as shown in FIG. 11, the high frequency can be lowered and the low frequency can be raised by the processing of the band pass filter.

  Next, each circuit will be described in more detail. FIG. 8 is a diagram illustrating an output example of the N frequency divider. The feedback frequency divider 17 outputs the original clock at 1/2, 1/3, 1/4, etc. according to the output of the adder 54.

  FIG. 9 is a timing chart showing a switch operation section and a sine wave processing section. In the case where the output of FIG. 9A is output from Output and N = 4, for example, in the section T2 (clock high period) shown in the figure, the bandpass filter 20 is connected to the sine wave generator. To generate a sine wave, and function as a band pass filter in the section T1 (clock low period). In this example, the switch 52 is switched to change the clock frequency to switch between the section functioning as a bandpass filter and the section generating the sine wave. In this case, in the low period, the switch is connected to the left side to cause the circuit 20 to function as a bandpass filter, and in the high period, the switch is connected to the right side to cause the circuit 20 to function as a sine wave generator. Here, in this example, the predetermined section T1 has been described as functioning as a bandpass filter and the section T2 as functioning as a sine wave generator, but most preferably, as a bandpass filter in the vicinity of the triangular wave peaks P1 and P2. It is made to function, and a sine wave is formed on other slopes of the triangular wave. In this way, the high frequency clock shown in FIG. 11 can be lowered to the low frequency side and the low frequency side clock can be raised to the high frequency side most efficiently.

The band pass filter 20 includes registers 21, 26, 28 _{1 to} 28 ₆ , adders 22, 23 ₁ to 23 _k , and selectors 24, 25, 27 _{1 to} 27 ₆ . In the case of functioning as a band pass filter, the coefficients A to G are input to the adders 23 ₁ to 23 ₇ . Any number of adders 23 _k , selectors 27, and registers 28 may be provided. The selector 27 _1, output of the preceding register 26, the register 28 ₁ of the output, 0, or 1 selects and outputs. The register 28 ₁ holds 0 or 1 input from the selector 27 ₁ . The band pass filter 20 operates using the output of the oscillation circuit 11 or the VCO 16 as a base clock. The selectors 27 _{1 to} 27 ₆ appropriately select data so that the output of the adder 22 satisfies the following mathematical formula.

When the band pass filter 20 generates a sine wave,
sinx = xx 3/3! + X ^ 5/5! -X ^ 7/7! = Gx + Ex ^ 3 + Cx ^ 5 + Ax ^ 7
Is calculated and output. Ie, x is inputted from the register 26, A × x is calculated by the adder 23 _1. In the next cycle, Ax + B is calculated, (Ax + B) x + c is calculated in the next cycle, (Ax ^ 2 + Bx + C) x + D is calculated in the next cycle,
(Ax ^ 3 + Bx ^ 2 + Cx + D) x + E
(Ax ^ 4 + Bx ^ 3 + Cx ^ 2 + Dx + E) x + F
(Ax ^ 5 + Bx ^ 4 + Cx ^ 3 + Dx ^ 2 + Ex + F) x + G
(Ax ^ 6 + Bx ^ 5 + Cx ^ 4 + Dx ^ 3 + Ex ^ 2 + Fx + G) x + H
= Ax ^ 7 + Bx ^ 6 + Cx ^ 5 + Dx ^ 4 + Ex ^ 3 + Fx ^ 2 + Gx + H
Here, in the case of a sine wave generator, B = D = F = H = 0,
sinx = Ax ^ 7 + Cx ^ 5 + Ex ^ 3 + Gx
It becomes.

  This band pass filter measures the frequency f (Hz) with respect to the input digital wave, and when f is higher than the frequency fH (Hz) having a certain value, the digital wave shifted down to the frequency f−Δ is detected. Output. Similarly, when the input frequency f (Hz) is measured and the frequency is lower than a predetermined frequency fL (Hz), the same Δ is used and a digital wave shifted up to a high frequency f + Δ (Hz) is output. . In this way, an operation of shifting the output frequency to a location having a certain width (closer to the center) is performed.

The triangular wave generation circuit 40 includes a counter 41 and a counter value switching circuit 42. The counter value switching circuit 42 includes detectors 43 ₁ to 43 _l (l is an integer) and a register 44. The detector detects the counter value by each detector and adjusts the output value of the counter. A switch for selecting a detector is controlled by a host control unit. The triangular wave generation circuit 40 generates a triangular wave by counting either the clock from the oscillation circuit 11 or the output of the bandpass filter 20.

  In the present embodiment, the spectrum characteristics are made more uniform by removing the high frequency side clock and the low frequency side clock by the band-pass filter. Furthermore, the frequency fluctuation is made smoother by superimposing the sine wave on the triangular wave. Then, the spread spectrum can be made more uniform by switching the function of the bandpass filter and the sine wave superposition in a time division manner. Furthermore, by sharing the bandpass filter and the triangular wave generator with the circuit 20, an increase in circuit scale can be minimized.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the present embodiment, the first periodic wave is described as a triangular wave and the second periodic wave is a sine wave. However, the triangular wave may not be a triangular wave as long as it has a predetermined period. Of course, a cosine wave or the like may be used instead of the sine wave.

It is a figure which shows the clock generation circuit with a frequency modulation function concerning embodiment of this invention. (A) is an input of the feedback frequency divider 17, and (b) is a diagram showing an output of the feedback frequency divider 17. FIG. 11 is a characteristic diagram showing a spectrum distribution of a generated clock when not modulating. 6 is a characteristic diagram showing a spectrum distribution of an output of a feedback frequency divider 17. FIG. 3 is a schematic diagram showing an output of a bandpass filter 20. FIG. A schematic diagram showing a sine wave generated by a sine wave generator, 3 is a schematic diagram showing a triangular wave generated by a triangular wave generating circuit 40. FIG. It is a figure which shows the example of an output of N frequency divider. It is a timing diagram which shows a switch operation area and a sine wave process area. This is a semiconductor integrated circuit described in Patent Document 1. It is a figure which shows the spectrum distribution of the conventional generation clock. DESCRIPTION OF SYMBOLS 1 Clock generation circuit 10 PLL circuit 11 Oscillation circuit 12 M frequency divider 13 Phase comparator 14 Charge pump 15 Loop filter 17 Feedback frequency divider 20 Band pass filter 21, 26, 28 _{1 to} 28 ₆ , 44, 53 Register 22 , 23 _k , 54 Adders 24, 25, 27 _{1 to} 27 ₆ , 55 Selector 40 Triangle wave generation circuit 41 Counter 42 Counter value switching circuit 52 Switch

Claims (7)

A PLL circuit having a feedback divider and outputting a frequency-modulated clock;
A band-pass filter that extracts only a predetermined frequency from the feedback divider and inputs it to the PLL circuit;
A first waveform generation circuit that generates a first periodic wave having a predetermined period;
The band-pass filter also functions as a second periodic wave generator having a predetermined period, generates a second periodic wave at a predetermined timing, and synthesizes the first periodic wave with the second periodic wave. A clock generation circuit with a frequency modulation function that varies the frequency division ratio of the frequency divider. 2. The frequency modulation function according to claim 1, wherein the first periodic wave is caused to function as the bandpass filter in the vicinity of a peak, and the second periodic wave generator is caused to function at other timings. Clock generation circuit. The clock generation circuit with a frequency modulation function according to claim 1, wherein the function as the bandpass filter and the function as the second periodic wave generator are switched at a predetermined ratio. The PLL circuit includes:
A voltage controlled oscillator that outputs an oscillation signal having a frequency according to the control voltage;
A phase comparator that outputs a phase difference signal representing a phase difference between a reference signal and a feedback signal corresponding to the oscillation signal;
A charge pump circuit that outputs an analog signal corresponding to the pulse width of the phase difference signal output from the phase comparator;
A loop filter for smoothing an analog signal output from the charge pump circuit and outputting a frequency control signal;
A voltage controlled oscillator that outputs a clock signal having an oscillation frequency characteristic corresponding to the frequency control signal output from the loop filter;
4. The frequency modulation function-equipped clock according to claim 1, further comprising: the feedback frequency divider that divides the output of the voltage-controlled oscillator into N (N is an integer) and outputs the divided signal. 5. Generation circuit. A PLL circuit having a feedback divider and outputting a frequency-modulated clock;
A band-pass filter that extracts only a predetermined frequency from the feedback divider and inputs it to the PLL circuit;
A first waveform generation circuit for generating a first periodic wave having a predetermined period;
A second waveform generator for generating a second periodic wave having a predetermined period from the output of the feedback divider;
An adder for combining the first waveform and the second waveform;
The feedback frequency divider is a clock generation circuit with a frequency modulation function that changes a frequency division ratio based on an output of the adder. 6. The clock generation circuit with a frequency modulation function according to claim 1, wherein the first periodic wave is a triangular wave. The clock generation circuit with a frequency modulation function according to any one of claims 1 to 6, wherein the second periodic wave is a sine wave or a cosine wave.

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