JP2006148840A - Semiconductor integrated circuit and electronic component for clock generation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with a built-in clock generation circuit and an electronic component for clock generation (SSCG module) in which noise generation is reduced and malfunctions of peripheral circuits and the electronic component or the like can be decreased. <P>SOLUTION: In the semiconductor integrated circuit with the built-in clock generation circuit comprising a PLL circuit which includes a frequency variable oscillator (116) and controls an oscillation frequency of the oscillator by comparing a phase of a reference signal with that of a feedback signal resulting from dividing a frequency of an output oscillation signal of the oscillator, and including a function of modulating the frequency of the output oscillation signal in predetermined cycles, a remarkable change in a modulation waveform is determined by switching a frequency dividing ratio of a frequency divider circuit (117) on a feedback path, and a phase of a signal to be fed back is switched by generating or selecting a plurality of signals resulting from shifting the phase of the output oscillation signal of said oscillator, thereby performing precise control of the modulation waveform. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit including a clock generation circuit including an oscillator and a clock generation circuit including a PLL (phase locked loop) circuit having a spread spectrum function. The present invention relates to a technique that is effective when used in a semiconductor integrated circuit incorporating a clock generation circuit for generating an operation clock signal of an internal circuit such as a computer or a system LSI.

  As a clock generation circuit that is built in a logic LSI such as a microcomputer and generates an operation clock signal, there is a circuit that uses a PLL circuit that generates a high-frequency clock signal obtained by multiplying an oscillation signal of a crystal oscillator as a reference clock. In an LSI incorporating a clock generation circuit using such a PLL circuit, the frequency of the operation clock is increased as the speed of the LSI increases, and the computer main body, peripheral circuits, external devices, etc. are caused by radiation noise from the oscillation circuit. There is a problem that malfunctions are induced. As a countermeasure against such a situation, a clock generation IC called SSCG is provided in which a spread spectrum function is provided in a PLL circuit to vary the clock frequency.

3 is an explanatory diagram of frequency control in the SSCG circuit, and FIG. 4 is a characteristic diagram showing the spread spectrum effect. Frequency control in a conventional general SSCG circuit is performed by changing a frequency dividing ratio of a frequency dividing circuit provided in the middle of a feedback path for feeding back an output oscillation signal of a VCO (voltage controlled oscillator) to a phase comparator at a predetermined period. By doing so, as shown in FIG. 3C, the frequency of the clock signal is modulated in accordance with a triangular wave having a predetermined period T sufficiently longer than the period of the generated clock.
JP 2003-124805 A

  However, in spectrum spreading by frequency modulation in which the frequency dividing ratio of the frequency dividing circuit provided in the middle of the feedback path is changed at a predetermined period, the accuracy of frequency control is rough, so that the modulation waveform is the target in FIG. The triangular wave as shown in FIG. 3C does not become a sine wave as shown in FIG. 3B. Therefore, the spectrum characteristic has a distribution having two peaks as shown in FIG. 4B, and the spectrum as shown in FIG. 4C in the case of frequency modulation to become an ideal triangular wave. The effect of suppressing the peak value is smaller than that of the characteristic SSCG. As a result, it has become clear that the inter-wiring complex noise and EMI (electromagnetic interference) noise with other clock signals used in the system cannot be reduced sufficiently. FIG. 3A shows the frequency of a clock generated by a clock generation circuit that does not perform spread spectrum, and FIG. 4A shows its spectrum characteristics.

  In addition, there exists an invention currently disclosed by patent document 1 as a technique relevant to this invention. In the prior invention, a plurality of clocks having different phases are generated by a VCO, clocks having different phases are sequentially selected and fed back to a phase comparator to perform frequency modulation of the clock. However, this prior invention changes the period only by the phase shift of the clock, does not change the frequency division ratio of the frequency dividing circuit on the feedback path of the PLL at a predetermined period, and uses a ROM. However, the idea is to achieve frequency modulation of the clock, and the idea is different from the present invention.

An object of the present invention is to provide a semiconductor integrated circuit and a clock generation electronic component (SSCG module) incorporating a clock generation circuit that can reduce the occurrence of noise and reduce malfunctions of peripheral circuits and electronic components.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a PLL circuit that has a frequency variable oscillator and controls the oscillation frequency of the oscillator by comparing the phase of the reference signal and the feedback signal obtained by dividing the output oscillation signal of the oscillator is provided. In a semiconductor integrated circuit incorporating a clock generation circuit having a function of modulating at a predetermined period, a large change in a modulation waveform is determined by switching a frequency division ratio of a frequency divider circuit on a feedback path, and an output oscillation signal of the oscillator A plurality of signals whose phases are shifted can be generated or selected, and the modulation waveform is finely controlled by switching the phase of the signal to be fed back.

  According to the above-described means, the frequency of the oscillation signal can be modulated with high accuracy according to a predetermined waveform, and the frequency spectrum distribution of the frequency of the clock signal generated thereby can be flattened to make the peak value of the frequency spectrum. As a result, radiation noise of a specific frequency can be suppressed, and inter-wiring composite noise and EMI noise with other clock signals used in the system can be reduced.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, it is possible to realize a semiconductor integrated circuit and a clock generation electronic component (SSCG module) incorporating a clock generation circuit that can reduce noise and reduce malfunctions of peripheral circuits and electronic components. .

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit block diagram showing a first embodiment of a PLL clock generation circuit having a spread spectrum function according to the present invention. The clock generation circuit of this embodiment is not particularly limited, but is formed as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon. P1 to P4 are external terminals (electrode pads) provided on the semiconductor chip, among which P1 and P2 are terminals to which a vibrator 101 such as a crystal vibrator is connected, and P3 outputs a generated clock φ0. A terminal P4 is a terminal for inputting a control signal for designating the frequency of the output clock φ0.

  In this embodiment, the semiconductor integrated circuit for generating the clock and the vibrator 101 connected to the external terminals P1 and P2 are mounted on an insulating substrate or in a package to constitute a module. In the present specification, a plurality of semiconductor chips and discrete components are mounted on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside or in a package, and each of the printed wiring and bonding wires is used for each. A component configured to be treated as a single electronic component by combining the components so as to play a predetermined role is referred to as a module.

  The clock generation circuit 110 of this embodiment is coupled to terminals P1 and P2 to which the vibrator 101 is connected, and applies a bias voltage to the vibrator 101 to generate an oscillation signal that changes at a frequency corresponding to the natural frequency of the vibrator. An output oscillation circuit (OSC) 111, a fixed frequency dividing circuit 112 that divides the output oscillation signal of the oscillation circuit 111 into a signal having a frequency of 1 / M, and a frequency dividing signal of the fixed frequency dividing circuit 112 and a feedback signal A phase comparison circuit 113 that detects a phase difference, a charge pump 114 that outputs a current corresponding to the phase difference, a loop filter 115 that smoothes the output of the charge pump 114, and a voltage controlled oscillation circuit (VCO that oscillates at a frequency corresponding to a smooth voltage) 116, a PLL comprising a variable frequency divider 117 that divides the output of the VCO 116 by 1 / N and feeds back to the phase comparator 113 It is constituted by the road.

  The oscillation output of the VCO 116 is divided by the frequency dividing circuit 118, amplified by the buffer 119, and output as the generated clock φ0 from the external terminal P3 to the outside of the chip. In the frequency dividing circuit 118, the frequency dividing ratio is switched according to the signal input to the terminal P4 from the outside, and the frequency of the output clock φ0 is switched by an integer ratio such as 2 times, 4 times, 8 times,. Have been able to.

  Further, the clock generation circuit 110 of this embodiment can modulate the frequency of the generated clock φ0 by changing the frequency division ratio N of the variable frequency dividing circuit 117. The variable frequency dividing circuit 117 is constituted by a counter circuit or the like, and can take a value such that the frequency dividing ratio N includes a fraction or a decimal point.

  Further, in the clock generation circuit 110 of the present embodiment, the VCO 116 is configured so as to generate four oscillation signals whose phases are different from each other by 90 degrees, and the generated four oscillation signals are arranged at the subsequent stage of the VCO 116. There is provided a selector circuit 121 that selects any one of the signals and supplies the selected signal to the variable frequency dividing circuit 117. Further, the clock generation circuit 110 of this embodiment includes a counter circuit 122 that counts the oscillation signal of the oscillation circuit 111 and generates a modulation period, and converts the count value of the counter circuit 122 into code and converts the selector circuit 121. A code conversion circuit 130 for generating the selection signal SEL and the frequency dividing ratio N of the variable frequency dividing circuit 117 is provided.

  The code conversion circuit 130 stores an SSC pattern ROM 131 in which predetermined pattern data is stored and data is sequentially read out using the output of the counter circuit 122 as an address signal, and data read from the pattern ROM 131 is used as an address in advance. It comprises ROMs 132 and 133 that output stored data. Of these, the ROM 132 can be replaced with a decoder circuit that outputs a signal corresponding to the input. The ROMs 131 to 133 may be rewritable ones such as a mask ROM, but rewritable ones such as an EEPROM are effective. By doing so, the ROM data for generating the SSC pattern can be easily rewritten, and the change to the new SSC pattern and the correction of the defect can be easily performed.

  In the clock generation circuit 110 of this embodiment, the modulation ratio N is switched by switching the frequency division ratio N of the variable frequency dividing circuit 117 on the feedback path, and a plurality of oscillations output from the VCO 116 and having different phases are output. By sequentially selecting one of the signals and supplying it to the variable frequency dividing circuit 117, the modulation period can be finely changed. Specifically, the entire waveform of the triangular wave in FIG. 3C is controlled by switching the division ratio N of the variable frequency dividing circuit 117, and from the VCO 116 to the variable frequency dividing circuit 117 in the portion near the apex below the triangular wave. The phase of the supplied oscillation signal is corrected by switching in the order of, for example, 0 °, 90 °, 180 °, 270 °, 360 ° (0 °), 270 °, 180 °, 90 °, 0 °. In the portion near the top of the triangular wave, the phase of the oscillation signal supplied is, for example, 0 °, −90 °, −180 °, −270 °, −360 ° (0 °), −270 °, −180 °. , −90 °, 0 °, and so on.

  FIG. 5A shows the amount of phase shift of the feedback signal input to the phase comparison circuit 113 when four signals having phases different from each other by 90 ° are sequentially switched as signals supplied to the variable frequency dividing circuit 117. 5 (B), the phase of the feedback signal input to the phase comparison circuit 113 when the phase of the signal supplied to the variable frequency dividing circuit 117 is fixed and the frequency dividing ratio N of the variable frequency dividing circuit 117 is sequentially switched. The shift amount is shown. As shown in FIG. 5, the phase shift amount is smaller when the phase of the signal supplied to the variable frequency dividing circuit 117 is sequentially switched than when the frequency dividing ratio N of the variable frequency dividing circuit 117 is sequentially switched. It can be seen that fine frequency modulation can be performed.

  Therefore, only by switching the frequency dividing ratio N of the variable frequency dividing circuit 117, the portion near the apex of the triangular wave is distorted as shown in FIG. 3B, and the frequency modulation is performed according to the waveform like a sine wave. However, as in the circuit of the embodiment, the frequency modulation according to the waveform such as the triangular wave in FIG. 3C can be accurately realized by combining the switching of the division ratio N and the switching of the phase. It becomes like this.

  In this embodiment, since the code conversion circuit 122 for generating the switching signal of the frequency division ratio N of the variable frequency dividing circuit 117 and the selection signal SEL of the selector 121 is constituted by the ROM, the pattern data stored in the ROM is stored in the ROM. By changing, for example, a frequency modulation according to an arbitrary waveform such as a waveform called a Hershey kiss signal (Hershey kiss signal) which is a patent of Lexmark shown in FIG. 3D can be performed and used. The frequency modulation optimum for the system can be easily realized or changed in the middle.

  Further, the ROMs 131 to 133 are configured by one ROM so that the control data for generating the switching signal of the dividing ratio N of the variable frequency dividing circuit 117 and the selection signal SEL of the selector 121 is output from one ROM. It is also possible to configure. However, as in the embodiment, by composing the code conversion circuit with the ROM 131 and the ROM 132, 133 that is accessed by the read data, the code conversion circuit can be shared, and the common efficient pattern data can be obtained. By creating and storing, the capacity of the ROM can be reduced, and the chip size of the IC can be reduced.

  In this embodiment, the VCO 116 is configured to generate four oscillation signals whose phases are different from each other by 90 degrees, and a selector circuit 121 for selecting one of the signals is provided in the subsequent stage. Only one oscillation signal is generated, and a phase shift circuit is provided in place of the selector circuit 121 at the subsequent stage to generate a signal obtained by phase-shifting the oscillation signal of the VCO 116 in accordance with the signal from the ROM 131 and to the variable frequency divider circuit 117 You may comprise so that it may supply. In the embodiment of FIG. 1, only one external terminal P4 is provided, but a plurality of external terminals are provided so that the frequency dividing ratio of the frequency dividing circuit 118 can be set in a plurality of stages. Also good. Various types of phase shift circuits have been proposed in the past, such as JP-A-8-307208 and JP-A-2004-253919, and such a known phase shift circuit is also used in this embodiment. Therefore, illustration and description of a specific circuit example are omitted.

  Further, in this embodiment, the input of the ROM 131 is generated by the counter 122 that counts the reference clock generated by the oscillation circuit 111. This counter 122 is a signal divided by the variable frequency dividing circuit 117. May be configured to operate as a clock. The reference clock generated by the oscillation circuit 111 has a fixed frequency, but the frequency of the signal divided by the variable frequency dividing circuit 117 changes depending on the frequency division ratio, so the read cycle of the ROM 131 changes. As a result, the frequency spectrum of the generated clock becomes more spread.

  In the embodiment, the pattern data for generating the signal for switching the frequency division ratio and the signal for switching the selector 121 are constituted by three ROMs, but may be constituted by one ROM. The ROMs 131 to 133 store a plurality of control data groups (referred to as modulation patterns) that can execute frequency modulation according to a plurality of waveforms such as the triangular wave and the Hersikis wave, and are supplied from the outside. Any one of the modulation patterns can be designated according to the modulation pattern designation signal (mode signal) to be read, and the control data corresponding to the modulation pattern can be read out in a predetermined order.

  FIG. 2 shows a specific example of the VCO 116. As shown in FIG. 2, the VCO 116 of this embodiment cascade-connects a plurality of inverter circuits INV1, INV2, INV3, and INV4, and uses the output of the final stage inverter circuit INV4 as the input of the first stage inverter circuit INV1. It is composed of a ring oscillator that is fed back. The four oscillation signals φ0, φ1, φ2, and φ3, which are out of phase with each other by 90 degrees from the inverter circuits INV1 to INV4, are extracted by the buffers BFF1 to BFF4. In this embodiment, the inverter circuit INV1 is used. The voltage Vc smoothed by the loop filter 115 of FIG. 1 is used as the control voltage of the common current source CI of .about.INV4. When the current flowing through the current source CI is changed according to the voltage Vc, the transmission delay time of each of the inverter circuits INV1 to INV4 is changed, and thereby the oscillation frequency of the VCO 116 is changed.

  Instead of changing the oscillation frequency by changing the current of the current source CI by the voltage Vc from the loop filter 115, a common power supply voltage source is provided in the inverter circuits INV1 to INV4 constituting the ring oscillator, and the power supply voltage of the inverter May be changed by the voltage Vc from the loop filter 115 to change the oscillation frequency. Further, FIG. 2 shows a ring oscillator in which four inverter circuits INV1 to INV4 are cascade-connected. This is an image, and in an actual circuit, each inverter of FIG. The circuits INV1 to INV4 are configured by a plurality of CMOS inverters, logic gate circuits such as NAND gates and NOR gates, which are connected in cascade.

  Next, a configuration example of a system LSI will be described with reference to FIG. 6 as an example of a semiconductor integrated circuit incorporating the clock generation circuit of the above embodiment as a circuit for generating an internal operation clock. In FIG. 6, a circuit block constituting the clock generation circuit 110 shown in FIG. 1 excluding the oscillation circuit 111 is shown as one block 110 ′.

  The system LSI 200 according to this embodiment is mounted on, for example, a portable electronic device, and performs control of the entire system, data processing of moving images, and the like. In the system LSI of this embodiment, a processor 210 that executes a program, a memory interface 220 that performs data access control to a main memory such as an externally connected SDRAM (Synchronous DRAM), and the like are necessary for encoding and decoding moving image data. A coprocessor 230 for performing various arithmetic processing, a video scaler 240 for performing data processing necessary for expansion / contraction of moving images and encoding / decoding, an IO unit 250 for exchanging data with externally connected input / output devices, and a processor 210 A direct memory access (DMA) controller 260 that directly transfers data between peripheral modules and main memory without going through the CPU, a timer circuit 270 that generates a timer interrupt signal for the processor 210, and measures the current time, and an external device Serial communication with It is provided, such as Al communication interface 280.

  In the system LSI 200 of this embodiment, the variable frequency clock signal φ0 generated by the clock generation circuit 110 ′ is supplied to the processor 210, the coprocessor 230, and the DMA controller 260 whose period, that is, the operation speed may be slightly changed. On the other hand, the clock signal φs before the frequency is changed by the clock generation circuit 110 ′ generated by the oscillation circuit (OSC) 111 is supplied to the timer circuit 270 and the serial communication interface 280, which are inconvenient when the period varies. Has been to be.

  If the frequency of the clock signal supplied to the video scaler 240 also fluctuates, it may be visible to the human eye as a phenomenon such as image shaking, so the clock signal φs generated by the oscillation circuit (OSC) 111 is supplied. It is desirable to do. In the system LSI 200 of FIG. 6, since the spectrum is spread by changing the frequency of the operation clock φ0 supplied to the processor 210 and the coprocessor 230, radiation noise at a specific frequency can be suppressed.

  Further, in this embodiment, since the clock generation circuit 110 ′ is an on-chip circuit, when a plurality of pattern data is stored in the pattern ROM 131 in the clock generation circuit 110 ′ as described above, the processor 210 supplies a control signal C0 for designating any pattern data in the pattern ROM 131 in accordance with a program, whereby the modulation waveform of the generated clock can be changed, thereby further reducing the peak value of the frequency spectrum. be able to. In addition, the processor 210 can be configured to provide a control signal C1 for switching the frequency division ratio of the output side frequency divider circuit 118, whereby the clock signal can be changed according to the specifications and operation mode of the system to which the present invention is to be applied. You will be able to change the frequency.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the description has been given of the case where the present invention is applied to a clock generation circuit having an external terminal to which a resonator is connected. However, in a microcomputer or an SSC type clock generation IC, an external to which a crystal resonator is connected Some have a clock generation circuit that has a terminal and can generate a desired internal clock signal even when an externally generated clock signal is input without connecting a crystal resonator to the external terminal. The clock generation circuit of the present invention can also be configured as such a circuit.

  In the above embodiment, a ring oscillator is used as the voltage controlled oscillation circuit (VCO) 116, but an LC type voltage controlled oscillation circuit having an inductor and a capacitive element may be used.

  In the above description, the invention made mainly by the present inventor has been described by taking the system LSI, which is a field of use as its background, as an example. However, the present invention is not limited to this, and a microcomputer, microprocessor, DSP ( Digital signal processor) It can be widely used for other semiconductor integrated circuits incorporating logic circuits that operate in response to clock signals.

1 is a circuit block diagram showing a first embodiment of a PLL clock generation circuit having a spread spectrum function according to the present invention. It is a circuit block diagram which shows an example of the oscillation circuit with variable oscillation frequency. (A) is a frequency change in a clock generation circuit that does not perform frequency modulation, (B) is a frequency change in a conventional clock generation circuit that performs triangular wave modulation, and (C) is a clock generation that performs triangular wave modulation by applying the present invention. FIG. 4D is a timing chart showing the frequency change in the clock generation circuit that performs modulation according to another waveform by applying the present invention. FIG. 4 is a characteristic diagram showing a spectrum distribution of generated clocks corresponding to (A), (B), and (C) of FIG. 3. 5A shows the phase shift amount of the signal input to the phase comparison circuit when the phase of the signal supplied to the variable frequency dividing circuit is sequentially switched, and FIG. 5B shows the frequency division of the variable frequency dividing circuit. It is a timing chart which shows the amount of phase shifts of the signal inputted into a phase comparison circuit when ratios are switched sequentially. FIG. 3 is a block diagram illustrating a configuration example of a system LSI as an example of a semiconductor integrated circuit in which the clock generation circuit according to the embodiment is incorporated as a circuit that generates an internal operation clock.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Oscillator 110 Clock generation circuit 111 Oscillation circuit 112 Fixed frequency dividing circuit 113 Phase comparison circuit 114 Charge pump 115 Loop filter 116 Oscillation circuit (VCO)
117 Variable Divider Circuit 118 Divider Circuit 119 Buffer 121 Selector 122 Modulation Period Counter Circuit 130 Code Conversion Circuit 131-132 ROM (Read Only Memory)

Claims (11)

A semiconductor integrated circuit including a clock generation circuit having a function of modulating a frequency of a clock signal to be supplied to a predetermined circuit at a predetermined cycle,
The clock generation circuit includes a first oscillation circuit having a variable oscillation frequency, a frequency division circuit having a variable division ratio for dividing the output oscillation signal of the first oscillation circuit, and a feedback divided by the frequency division circuit. A phase comparison circuit that compares the phase of the signal with the phase of a reference signal, and a PLL circuit that controls the oscillation frequency of the first oscillation circuit according to the phase difference detected by the phase comparison circuit ,
The first oscillation circuit is configured to be capable of outputting a plurality of oscillation signals having different phases, and selects any one first oscillation signal from the plurality of oscillation signals, and supplies the first oscillation signal to the frequency divider circuit.
The frequency of the clock signal generated by the first oscillation circuit is modulated by changing the frequency division ratio of the frequency dividing circuit and sequentially changing the selected first transmission signal and supplying it to the frequency dividing circuit. A semiconductor integrated circuit, characterized in that it is configured.   The first oscillation circuit includes an oscillator that generates the plurality of oscillation signals having different phases from each other and a selector, and the selector selects the first oscillation signal having a desired phase from the plurality of oscillation signals. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured to be supplied to the frequency divider circuit.   The first oscillation circuit includes an oscillator and a phase shift circuit capable of shifting the phase of the output of the oscillator, and the first oscillation signal having a desired phase phase-shifted by the phase shift circuit is supplied to the frequency divider circuit. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured to be supplied.   Controls the first control code that specifies the frequency division ratio in the frequency divider circuit according to the input and the second control code that controls the signal selection operation of the first oscillation signal in the selector or the phase shift amount in the phase shift circuit The semiconductor integrated circuit according to claim 2, further comprising a code conversion circuit that generates a third control code to be generated.   The code conversion circuit includes a nonvolatile memory circuit that stores a plurality of the first, second, and third control codes, and each of the first, second, and third pluralities according to an input. 5. The semiconductor integrated circuit according to claim 4, wherein any one of the control codes is read and output.   6. The semiconductor integrated circuit according to claim 5, wherein the nonvolatile memory circuit performs a read operation based on the reference signal or a signal obtained by dividing the first oscillation signal by the divider circuit. .   A counter circuit that performs a counting operation based on the reference signal or a signal obtained by dividing the first oscillation signal by the frequency dividing circuit, and the nonvolatile memory circuit performs a reading operation with the count value of the counter circuit as an input. The semiconductor integrated circuit according to claim 6, which is performed.   A plurality of control code groups corresponding to a plurality of modulation waveforms are stored in advance in the non-volatile memory circuit, and any one of the plurality of control code groups is selected according to a designated modulation waveform, 6. The semiconductor device according to claim 5, wherein each of the first and second or third control codes belonging to the selected control code group is read in a predetermined order. Integrated circuit.   An external terminal to which a vibrator having a natural frequency can be connected; and a second oscillation circuit that outputs a second oscillation signal having a frequency corresponding to the natural frequency of the vibrator connected to the external terminal. 2. The semiconductor integrated circuit according to claim 1, wherein the reference signal is the second oscillation signal output from the second oscillation circuit. A clock generation circuit having a function of modulating a frequency of a clock signal to be supplied to a predetermined circuit at a predetermined period;
An external terminal to which a vibrator having a natural frequency can be connected;
The electronic component for clock generation having the vibrator connected to the external terminal,
The clock generation circuit includes: a first oscillation circuit having a variable oscillation frequency; a second oscillation circuit that outputs a second oscillation signal having a frequency corresponding to the natural frequency of the vibrator connected to the external terminal; A frequency dividing circuit that divides the output oscillation signal of the first oscillation circuit, and a phase comparison that compares the phase of the feedback signal divided by the frequency dividing circuit with the phase of the reference signal A PLL circuit that controls the oscillation frequency of the first oscillation circuit according to the phase difference detected by the phase comparison circuit,
The first oscillation circuit is configured to be capable of outputting a plurality of oscillation signals having different phases, and selects any one first oscillation signal from the plurality of oscillation signals, and supplies the first oscillation signal to the frequency divider circuit.
The frequency of the clock signal generated by the first oscillating circuit is changed by changing the dividing ratio of the dividing circuit and sequentially changing the selected first transmission signal and supplying the first transmitting signal to the dividing circuit. Modulate,
The clock generation electronic component according to claim 1, wherein the reference signal is the second oscillation signal output from the second oscillation circuit.   A semiconductor integrated circuit comprising the clock generation circuit according to claim 1 and a processor that operates according to the clock signal generated by the clock generation circuit.

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