JP2006074306A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock generation circuit generating little noise and reducing the malfunction of peripheral circuits and electronic parts and to provide a semiconductor integrated circuit incorporating the clock generation circuit. <P>SOLUTION: The semiconductor integrated circuit incorporates the clock generation circuit (110) which has: a PLL circuit having a voltage controlled oscillator (116) and for controlling the oscillation frequency of the voltage controlled oscillator by comparing the phase of a reference signal with that of a feedback signal obtained by dividing the frequency of an output oscillation signal; and a function for modulating the frequency of the output oscillation signal at a prescribed period, wherein the modulation period is changed by a digital control signal or by giving a prescribed control signal to a feedback route. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit including a clock generation circuit including an oscillator and a clock generation circuit including a PLL (phase locked loop) circuit having a spread spectrum function. The present invention relates to a technique that is effective when used in a semiconductor integrated circuit incorporating a clock generation circuit for generating an operation clock signal of an internal circuit such as a computer or a system LSI.

  As a clock generation circuit that is built in a logic LSI such as a microcomputer and generates an operation clock signal, there is a circuit that uses a PLL circuit that generates a high-frequency clock signal obtained by multiplying an oscillation signal of a crystal oscillator as a reference clock. In an LSI incorporating a clock generation circuit using such a PLL circuit, there is a risk of causing malfunctions of the computer main body, peripheral circuits, external devices, etc. due to radiation noise from the oscillation circuit as the clock frequency increases. As a countermeasure against such a situation, a clock generation IC called SSCG is provided in which a spread spectrum function is provided in a PLL circuit to vary the clock frequency.

Spread spectrum gives jitter that slightly modulates the frequency of the clock signal so that the spectrum of electromagnetic noise energy emitted by electronic components and electronic equipment is not concentrated in a narrow band, and the energy of radiated electromagnetic noise is reduced to a certain frequency. This is a technique for suppressing the peak value by dispersing the bandwidth. FIG. 2A is an explanatory diagram of frequency control in a conventional SSCG circuit, and FIG. 3 is a characteristic diagram showing the spectrum spread effect caused by the frequency control. As shown in FIG. 2A, the frequency control in the conventional general SSCG circuit is performed by setting the oscillation frequency to a predetermined ratio (for example, ± 1) at a predetermined period T sufficiently longer than the period of the generated clock. .5%).
JP 2003-101408 A

  In spread spectrum based on frequency control as shown in FIG. 2A in a conventional general SSCG circuit, the oscillation frequency is changed at a constant period T. Therefore, depending on the modulation frequency, FIG. As shown in the enlarged spectrum characteristics, unevenness occurs, the peak value PEAK of radiation noise at a specific frequency increases, and the inter-wiring complex noise and EMI (electromagnetic interference) with other clock signals used in the system It has become clear that noise may increase and cause malfunctions of peripheral circuits and electronic components.

  In addition, there exists an invention currently disclosed by patent document 1 as a technique relevant to this invention. However, in the prior invention, an adder for frequency modulation is provided between the loop filter of the PLL circuit and the VCO, and modulation is performed by controlling the control voltage of the VCO and modulation is performed by changing the control amount. The period is changed. That is, modulation control for spread spectrum is performed on an analog signal and on the PLL forward path, and as will be clarified later, modulation control for spread spectrum is performed on a digital signal and on the feedback path of the PLL. The method of realization differs from that of the present invention.

An object of the present invention is to provide a clock generation circuit that can reduce the occurrence of noise and reduce malfunctions of peripheral circuits and electronic components, and a semiconductor integrated circuit incorporating the clock generation circuit.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
In other words, a PLL circuit that has a voltage controlled oscillator and controls the oscillation frequency of the voltage controlled oscillator by comparing the phase of a feedback signal obtained by dividing the reference signal and the output oscillation signal, and setting the frequency of the output oscillation signal to a predetermined value In a semiconductor integrated circuit incorporating a clock generation circuit that has a function of modulating at a period of, the modulation period is changed by a digital control signal, or the modulation period is changed by giving a predetermined control signal in a feedback path It is a thing.

  According to the above-described means, the frequency spectrum can be spread in order to modulate the frequency of the oscillation signal with a predetermined period, and the peak value of the frequency spectrum can be set because the modulation period of the frequency of the generated clock signal is changed. Thus, radiation noise at a specific frequency can be suppressed, and inter-wiring composite noise and EMI noise with other clock signals used in the system can be reduced.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, it is possible to realize a clock generation circuit that can reduce the occurrence of noise and reduce malfunctions of peripheral circuits and electronic components, and a semiconductor integrated circuit incorporating the clock generation circuit.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit block diagram showing a first embodiment of a PLL clock generation circuit having a spread spectrum function according to the present invention. The clock generation circuit of this embodiment is not particularly limited, but is formed as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon. P1 to P5 are external terminals (electrode pads) provided on the semiconductor chip, among which P1 and P2 are terminals to which a vibrator 101 such as a crystal vibrator is connected, and P3 and P4 are external control signals. An input terminal, P5, is a terminal from which the generated clock is output.

  The clock generation circuit 110 of this embodiment is coupled to terminals P1 and P2 to which the vibrator 101 is connected, and applies a bias voltage to the vibrator 101 to generate an oscillation signal that changes at a frequency corresponding to the natural frequency of the vibrator. An output oscillation circuit 111, a fixed frequency division circuit 112 that divides the output of the oscillation circuit 111 by M, a phase comparison circuit 113 that detects a phase difference between the frequency division signal of the fixed frequency division circuit 112 and a feedback signal, a phase difference A charge pump 114 that outputs a current according to the output, a loop filter 115 that smoothes the output of the charge pump 114, a voltage controlled oscillation circuit (VCO) 116 that oscillates at a frequency corresponding to the smoothed voltage, and the output of the VCO is divided by N. A PLL circuit including a frequency dividing circuit 117 that feeds back to the phase comparison circuit 113 is formed. A buffer 118 amplifies the oscillation output of the VCO and outputs it as a generated clock φ0 from the external terminal P4 to the outside of the chip. The clock generation circuit 110 of this embodiment can switch the frequency of the generated clock φ0 by switching the frequency dividing ratio M of the fixed frequency dividing circuit 112.

  The clock generation circuit 110 of the present embodiment further includes a variable frequency dividing circuit 121 that includes a counter circuit and divides the signal divided by the frequency dividing circuit 117 at an arbitrary frequency dividing ratio, and the frequency dividing circuit 117. A modulation amplitude adjustment circuit 122 that generates a predetermined variation amount ΔN to be given to the frequency division ratio N, and a variation amount ΔN generated by the modulation amplitude adjustment circuit 122 to the predetermined frequency division ratio N Is provided to the frequency dividing circuit 117 as a current frequency dividing ratio, and a modulation period adjusting circuit 124 is provided for adjusting the modulation period by changing the count value of the variable frequency dividing circuit 121, that is, the frequency dividing ratio. ing. The variable frequency dividing circuit 121 operates as a circuit that generates a signal that gives the adding circuit 123 the timing for adding the variation ΔN output from the modulation amplitude adjusting circuit 122 to the frequency dividing ratio N.

  In this embodiment, the control signal C0 from the external terminal P3 is supplied to the modulation amplitude adjustment circuit 122, and the modulation amplitude adjustment circuit 122 changes the modulation amplitude, that is, the frequency division ratio N according to the control signal C0 from P3. Whether or not to generate the quantity ΔN is set. Also, the control signal C1 from the external terminal P4 is supplied to the modulation period adjustment circuit 124, and the modulation period adjustment circuit 122 adds ΔN to the modulation period, that is, the frequency division ratio N according to the control signal C1 from P4. It is configured to set whether to change or not. ΔN is selected to be a value that changes the frequency f0 of the generated clock φ0 by several percent (eg, 3%).

  In the embodiment of FIG. 1, each of the external terminals P3 and P4 is provided, but a plurality of external terminals are provided, that is, the control signals C0 and C1 are input as a multi-bit signal, The change amount ΔN of the frequency division ratio N may be set in a plurality of stages, or the modulation period may be set in a plurality of stages. Further, it is also possible to configure so that ΔN and the modulation period can be set in a plurality of stages by providing serial code control signals C0 and C1 with one external terminal P3 and P4, respectively.

  Next, the operation of the clock generation circuit 110 of this embodiment will be described. In order to facilitate understanding, the control operation by the modulation amplitude adjustment circuit 122 and the control operation by the modulation period adjustment circuit 124 will be described separately.

  FIG. 2 shows how the frequency f0 of the generated clock φ0 changes when the modulation amplitude adjustment circuit 122 operates when the output of the modulation period adjustment circuit 124 is fixed, that is, when the modulation period adjustment circuit 124 is not provided. Among these, FIG. 2A shows the case where ΔN is changed by the same amount in the plus direction and the minus direction by the modulation amplitude adjusting circuit 122, that is, the case where the macroscopic average frequency is made constant, and FIG. This shows a case where ΔN is changed only in the minus direction by the modulation amplitude adjusting circuit 122.

  2A and 2B, the modulation amplitude adjusting circuit 122 adds ΔN to the frequency division ratio N to change the frequency division ratio N of the frequency dividing circuit 117, thereby changing the frequency of the generated clock φ0. It can be seen that f0 is modulated with a predetermined period T0. The modulation period T0 at this time is given by the variable frequency dividing circuit 121. When the frequency f0 of the generated clock φ0 is modulated, the spectrum of φ0 is concentrated at the frequency f0 as shown by a solid line when no modulation is applied, as shown in FIGS. However, when modulation is performed by the modulation amplitude adjusting circuit 122, the signal is diffused by several percent as indicated by broken lines.

  Note that the modulation only in the negative direction as shown in FIG. 2B does not reduce the operation margin when, for example, the frequency of the generated clock is close to the maximum operating frequency of the circuit that operates by receiving the supply of the clock. There is an advantage that the frequency spectrum of φ0 can be spread. Therefore, which of the modulation schemes of FIGS. 2A and 2B is applied depends on the circuit in which the clock is used, when the circuit gives priority to the operation speed over the operation margin. When the modulation method A) is applied and the circuit gives priority to the operation margin over the operation speed, the modulation method shown in FIG. 2B may be applied.

  4 shows how the frequency f0 of the generated clock φ0 changes when the modulation amplitude adjustment circuit 122 and the modulation period adjustment circuit 124 operate. 4A shows the case where the modulation period T is changed by the same amount a in the plus direction and the minus direction by the modulation period adjusting circuit 124, that is, the macroscopic average period is made constant. (B) shows a case where the modulation period T is changed only in the plus direction by the modulation period adjustment circuit 124. When the operation speed is given priority over the operation margin according to the circuit in which the clock is used, the modulation cycle control in FIG. 4A is applied, and the circuit gives priority to the operation margin over the operation speed. 4 may be applied with the modulation cycle control in FIG.

  5 shows the frequency spectrum distribution of the generated clock φ0 when only the modulation amplitude adjustment circuit 122 operates and the modulation cycle adjustment circuit 124 does not operate. FIG. 6 shows the modulation amplitude adjustment circuit 122 and the modulation cycle adjustment circuit 124. The frequency spectrum distribution of the generated clock φ0 when both operate is shown. 5 and FIG. 6, (B) shows an enlarged part of the distribution of (A). 5 and 6 that the peak value PEAK of the frequency spectrum distribution of the generated clock φ0 can be reduced by changing the modulation period T by the modulation period adjusting circuit 124. And by reducing the peak value PEAK in this way, it becomes possible to reduce inter-wiring complex noise and EMI (electromagnetic interference) noise with other clock signals used in the system.

FIG. 7 is a circuit block diagram showing a second embodiment of a PLL clock generation circuit having a spread spectrum function according to the present invention. In FIG. 7, the same circuit blocks as those in FIG.
In the clock generation circuit of this embodiment, the input of the variable frequency dividing circuit 121 that gives the timing for changing the modulation period is not the output of the N frequency divider 117 but the input, that is, the generated clock φ0. A decoder 125 is provided in the subsequent stage, and the timing for changing the modulation period is changed by changing the decode value of the decoder 125 by the control signal from the modulation period adjustment circuit 124.

  In this embodiment, the same effect as that of the first embodiment can be obtained. However, in the second embodiment, the frequency of the signal divided by the variable frequency dividing circuit 121 is constant, whereas in the first embodiment, the signal is divided by the frequency division ratio N changed by the modulation amplitude adjusting circuit 122. Since the variable frequency dividing circuit 121 divides the generated signal, that is, the signal whose frequency changes, the first embodiment can reduce the peak value PEAK of the frequency spectrum distribution of the clock φ0 as compared with the second embodiment. There are advantages.

  In the embodiment of FIG. 7, instead of providing the decoder 125, the modulation period is changed by changing the count value of the variable frequency dividing circuit 121 by the control signal from the modulation period adjusting circuit 124 as in the first embodiment. You may make it change the timing to perform. On the contrary, in the embodiment of FIG. 1, a decoder 125 whose decode value is changed by a control signal from the modulation period adjusting circuit 124 may be provided in the subsequent stage of the variable frequency dividing circuit 121.

  Next, a configuration example of a system LSI will be described with reference to FIG. 8 as an example of a semiconductor integrated circuit in which the clock generation circuit of the above embodiment is incorporated as a circuit for generating an internal operation clock. In FIG. 8, the circuit block constituting the clock generation circuit 110 shown in FIGS. 1 and 7 except for the oscillation circuit 111 is shown as one block 110 '.

  The system LSI 200 according to this embodiment is mounted on, for example, a portable electronic device, and performs control of the entire system, data processing of moving images, and the like. In the system LSI of this embodiment, a processor 210 that executes a program, a memory interface 220 that performs data access control to a main memory such as an externally connected SDRAM (Synchronous DRAM), and the like are necessary for encoding and decoding moving image data. A coprocessor 230 for performing various arithmetic processing, a video scaler 240 for performing data processing necessary for expansion / contraction of moving images and encoding / decoding, an IO unit 250 for exchanging data with externally connected input / output devices, and a processor 210 A direct memory access (DMA) controller 260 that directly transfers data between peripheral modules and main memory without going through the CPU, a timer circuit 270 that generates a timer interrupt signal for the processor 210, and measures the current time, and an external device Serial communication with It is provided, such as Al communication interface 280.

  In the system LSI 200 of this embodiment, the frequency-variable clock signal φ0 generated by the clock generation circuit 110 ′ is supplied to the processor 210, coprocessor 230, and DMA controller 260 whose period, that is, the operation speed may be varied. On the other hand, the clock signal φs before the frequency is changed by the clock generation circuit 110 ′ generated by the oscillation circuit (OSC) 111 is supplied to the timer circuit 270 and the serial communication interface 280 that are in trouble if the period varies. Has been.

  If the frequency of the clock signal supplied to the video scaler 240 also fluctuates, it may be visible to the human eye as a phenomenon such as image shaking, so the clock signal φs generated by the oscillation circuit (OSC) 111 is supplied. It is desirable to do. In the system LSI 200 of FIG. 8, the frequency of the operation clock φ0 supplied to the processor 210 and the coprocessor 230 is changed and the spectrum is spread, so that radiation noise at a specific frequency can be suppressed.

  Further, in this embodiment, since the clock generation circuit 110 ′ is an on-chip circuit, the processor 210 performs modulation amplitude and modulation by the modulation amplitude adjustment circuit 122 and the modulation period adjustment circuit 124 in the clock generation circuit 110 ′ according to a program. By switching the control signals C0 and C1 for adjusting the period, the modulation period can be dynamically changed, and the peak value of the frequency spectrum can be further reduced. However, instead of the processor 210 receiving the control signals C0 and C1 for adjusting the modulation period, external terminals P3 and P4 for inputting the control signals C0 and C1 are provided, and the control signals C0 and C1 are modulated from the outside. You may comprise so that it may give to the adjustment circuit 122 and the modulation period adjustment circuit 124. FIG.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the description has been given of the case where the present invention is applied to a clock generation circuit having an external terminal to which a resonator is connected. However, in a microcomputer or an SSC type clock generation IC, an external to which a crystal resonator is connected Some have a clock generation circuit that has a terminal and can generate a desired internal clock signal even when an externally generated clock signal is input without connecting a crystal resonator to the external terminal. The clock generation circuit of the present invention can also be configured as such a circuit.

  In the above embodiment, the case where the generated clock is modulated according to the triangular wave as shown in FIG. 2 has been described. However, the sine wave or the hypotenuse of the triangular wave in FIG. The present invention can also be applied to a case where modulation is performed according to a changing pseudo triangular wave or the like.

  Further, in the above embodiment, the variable frequency dividing circuit 121 and the modulation period adjusting circuit 124 for adjusting the modulation period by changing the count value, that is, the frequency dividing ratio are provided to modulate the clock period. Instead of this circuit, modulation may be performed by providing a random number generator or a sigma delta modulator. When a sigma delta modulator is used, the peak value of the frequency spectrum can be further reduced by increasing the order.

  In the above description, the invention made mainly by the present inventor has been described by taking the system LSI, which is a field of use as its background, as an example. However, the present invention is not limited to this, and a microcomputer, microprocessor, DSP ( Digital signal processor) It can be widely used for other semiconductor integrated circuits incorporating logic circuits that operate in response to clock signals.

1 is a circuit block diagram showing a first embodiment of a PLL clock generation circuit having a spread spectrum function according to the present invention. (A) and (B) are timing charts respectively showing changes in the frequency of the generated clock when the modulation amplitude adjustment circuit operates when the output of the modulation period adjustment circuit is fixed. FIG. 3 is a characteristic diagram showing a spectrum distribution of generated clocks corresponding to (A) and (B) of FIG. 2. (A) and (B) are timing charts respectively showing changes in the frequency of the generated clock when the modulation amplitude adjustment circuit and the modulation period adjustment circuit are operated. FIG. 6 is a characteristic diagram showing a frequency spectrum distribution of a generated clock when only the modulation amplitude adjustment circuit operates and the modulation cycle adjustment circuit does not operate. FIG. 10 is a characteristic diagram showing a frequency spectrum distribution of a generated clock when both a modulation amplitude adjustment circuit and a modulation cycle adjustment circuit are operated. FIG. 6 is a circuit block diagram showing a second embodiment of a PLL clock generation circuit having a spread spectrum function according to the present invention. 1 is a block diagram illustrating a configuration example of a system LSI as an example of a semiconductor integrated circuit in which a clock generation circuit according to an embodiment is incorporated as a circuit that generates an internal operation clock; FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Oscillator 110 Clock generation circuit 111 Oscillation circuit 112 Fixed frequency dividing circuit 113 Phase comparison circuit 114 Charge pump 115 Loop filter 116 Voltage control oscillation circuit (VCO)
117 Frequency Dividing Circuit for Feedback 118 Buffer 121 Variable Frequency Dividing Circuit 122 Modulation Amplitude Adjustment Circuit 123 Adder Circuit 124 Modulation Period Adjustment Circuit 125 Decoder

Claims (11)

A semiconductor integrated circuit including a clock generation circuit having a function of modulating a clock oscillation frequency to be supplied to a predetermined circuit at a predetermined modulation period,
The clock generation circuit is a PLL that controls the oscillation frequency of the voltage controlled oscillator according to a phase difference from a comparison circuit that compares the phase of a reference signal and a feedback signal obtained by dividing the output oscillation signal of the voltage controlled oscillator. With a circuit,
The PLL circuit has the voltage controlled oscillator and the comparison circuit,
A semiconductor integrated circuit configured to change the modulation period by a digital control signal. A semiconductor integrated circuit including a clock generation circuit having a function of modulating a clock oscillation frequency to be supplied to a predetermined circuit at a predetermined modulation period,
The clock generation circuit is a PLL that controls the oscillation frequency of the voltage controlled oscillator according to a phase difference from a comparison circuit that compares the phase of a reference signal and a feedback signal obtained by dividing the output oscillation signal of the voltage controlled oscillator. With a circuit,
The PLL circuit has the voltage controlled oscillator and the comparison circuit,
A semiconductor integrated circuit, wherein the modulation period is changed by applying a predetermined control signal in a feedback path of the feedback signal.   3. The frequency of the output oscillation signal is modulated at a predetermined period by changing a frequency dividing ratio of a frequency dividing circuit that divides the output oscillation signal to generate the feedback signal. A semiconductor integrated circuit according to 1.   4. The semiconductor integrated circuit according to claim 3, further comprising a modulation period switching circuit that changes the modulation period by changing a timing at which a frequency dividing ratio of the frequency dividing circuit is changed.   The modulation period switching circuit includes a variable frequency dividing circuit that divides the output signal or input signal of the frequency dividing circuit, and an adjustment circuit that changes the modulation period by changing a frequency dividing ratio of the variable frequency dividing circuit. The semiconductor integrated circuit according to claim 4, comprising:   The modulation cycle switching circuit includes a variable frequency dividing circuit that divides the output signal or input signal of the frequency dividing circuit, a decoder that decodes the output of the variable frequency dividing circuit, and a decoding value of the decoder. The semiconductor integrated circuit according to claim 4, comprising an adjustment circuit that changes the modulation period.   4. The semiconductor integrated circuit according to claim 3, further comprising an external terminal for inputting a control signal for changing a frequency dividing ratio of the frequency dividing circuit that generates the feedback signal.   5. An external terminal for inputting a second control signal for instructing the modulation cycle switching circuit to change a timing for changing a frequency dividing ratio of the frequency dividing circuit. A semiconductor integrated circuit according to 1.   An external terminal to which a vibrator having a natural frequency can be connected; and an oscillation circuit that outputs an oscillation signal that changes at a frequency corresponding to the natural frequency of the vibrator connected to the external terminal, and the reference The semiconductor integrated circuit according to claim 1, wherein the signal to be is an oscillation signal output from the oscillation circuit. A semiconductor integrated circuit including a clock generation circuit having a function of modulating an oscillation frequency of a first clock signal to be supplied to a predetermined circuit at a predetermined modulation cycle, wherein the clock generation circuit controls a reference signal and voltage A PLL circuit that controls the oscillation frequency of the voltage controlled oscillator according to a phase difference from a comparison circuit that compares the phase with a feedback signal obtained by dividing the output oscillation signal of the oscillator;
The PLL circuit includes the voltage controlled oscillator and the comparison circuit,
The semiconductor integrated circuit is configured to change the modulation period with a digital control signal,
A semiconductor integrated circuit including a first logic circuit that operates based on the first clock signal and a second logic circuit that operates based on the reference signal or a second clock signal that is generated based on the reference signal and is not frequency-modulated.   8. A semiconductor integrated circuit comprising: the clock generation circuit according to claim 7; and a control circuit that operates according to the clock generated by the clock generation circuit, wherein the control signal is generated by the control circuit. .

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