TWI439053B - Spread spectrum clock system and spread spectrum clock generator - Google Patents

Spread spectrum clock system and spread spectrum clock generator Download PDF

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TWI439053B
TWI439053B TW99125114A TW99125114A TWI439053B TW I439053 B TWI439053 B TW I439053B TW 99125114 A TW99125114 A TW 99125114A TW 99125114 A TW99125114 A TW 99125114A TW I439053 B TWI439053 B TW I439053B
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triangular wave
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modulator
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TW201206084A (en
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Kengyu Chang
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Himax Tech Ltd
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展頻時脈系統及其展頻時脈產生器Spread spectrum clock system and its spread spectrum clock generator

本發明是有關於一種展頻時脈產生器,且特別是有關於一種可調整頻率的展頻時脈產生器。The present invention relates to a spread spectrum clock generator, and more particularly to an adjustable frequency spread spectrum clock generator.

在高速電子系統當中,例如無線電話系統、光纖網路系統、微電腦系統,以及高階系統單晶片(System on a chip;SOC),其操作速度均已達到十億赫茲(GHZ)的水準。因此,與這些系統配合的電子裝置亦需提升其操作頻率來跟上這些高速系統。此外,由於許多電路均整合於同一顆晶片上,使時脈信號遍佈整個晶片,導致時脈信號產生偏差現象(Clock skew)。In high-speed electronic systems, such as wireless telephone systems, fiber-optic network systems, microcomputer systems, and high-end system-on-chip (SOC), operating speeds have reached the level of one billion hertz (GHZ). Therefore, electronic devices that work with these systems also need to increase their operating frequency to keep up with these high-speed systems. In addition, since many circuits are integrated on the same wafer, the clock signal is spread throughout the wafer, causing clock skew to occur in the clock signal.

舉例來說,當輸入時脈信號驅動一晶片,輸入時脈信號與內部時脈信號之間會存在一變動而不固定的延遲時間,這個變動不固定的延遲時間會造成晶片工作不正常。為了同步系統內部的時脈信號,許多高速電路系統已採用鎖相迴路(Phase locked loop;PLL)與延遲鎖定迴路(Delay-locked loop)來消除時脈信號偏差現象。For example, when the input clock signal drives a chip, there is a variation and a fixed delay time between the input clock signal and the internal clock signal. This unfixed delay time may cause the wafer to work abnormally. In order to synchronize the clock signals inside the system, many high-speed circuit systems have adopted a phase locked loop (PLL) and a delay-locked loop to eliminate clock signal deviation.

當轉換速率的增加,會影響或破壞週邊電子元件效能的電磁干擾效應(Electromagnetic interference)也隨之加劇,造成這些週邊電子元件無法被使用。由於時脈信號是造成電磁干擾效應的主因,所以如何減少時脈信號所造成的電磁干擾效應實為當務之急。As the slew rate increases, the electromagnetic interference that affects or destroys the performance of peripheral electronic components is also exacerbated, causing these peripheral electronic components to be unusable. Since the clock signal is the main cause of the electromagnetic interference effect, how to reduce the electromagnetic interference effect caused by the clock signal is a top priority.

近來,展頻時脈產生器(Spread Spectrum Clock Generator)已被廣泛地應用來減少電磁干擾效應。恰如其名,「展頻」代表將時脈信號的中心頻率作些微的展開,將能量分散至其他頻率上而降低主要頻率上的能量。由於主要頻率上的能量被減少,因而可降低電磁干擾效應。Recently, the Spread Spectrum Clock Generator has been widely used to reduce electromagnetic interference effects. As the name suggests, "spreading frequency" means that the center frequency of the clock signal is slightly spread, and the energy is dispersed to other frequencies to reduce the energy at the main frequency. Since the energy at the main frequency is reduced, the electromagnetic interference effect can be reduced.

換句話說,「展頻」即是使時脈信號的頻率產生些微的變化,藉此減少電磁干擾效應。縱然展頻的作法可以減少電磁干擾效應,時脈信號的抖動現象(Jitter)卻會惡化,使用者必須在降低電磁干擾效應與降低時脈抖動現象之間做出取捨與妥協。In other words, "spreading frequency" is to make a slight change in the frequency of the clock signal, thereby reducing the electromagnetic interference effect. Even though the spread spectrum method can reduce the electromagnetic interference effect, the jitter of the clock signal (Jitter) will deteriorate, and the user must make trade-offs and compromises between reducing the electromagnetic interference effect and reducing the clock jitter phenomenon.

可惜的是,傳統的展頻時脈產生器僅以倍增的方式來擴展時脈信號的頻率,無法連續且彈性地調整時脈信號的展頻量,因而無法在降低電磁干擾效應與降低時脈抖動現象之間做出取捨,導致整體效能下降。Unfortunately, the traditional spread-spectrum clock generator only expands the frequency of the clock signal in a multiplication manner, and cannot continuously and elastically adjust the spread frequency of the clock signal, thereby failing to reduce the electromagnetic interference effect and reduce the clock. Making trade-offs between jitters leads to a decline in overall performance.

因此,需要一個新的展頻時脈產生器,能更彈性地調整時脈信號的平均頻率。Therefore, a new spread-spectrum clock generator is needed to more flexibly adjust the average frequency of the clock signal.

因此,本發明之一態樣是在提供一種展頻時脈產生器,可連續且彈性地調整時脈信號的頻率。Accordingly, one aspect of the present invention is to provide a spread spectrum clock generator that continuously and elastically adjusts the frequency of a clock signal.

依據本發明一實施例,展頻時脈產生器含有一三角波產生器、一數位波形調變器、一三角調變器以及一選擇器。三角波產生器將複數個輸入時脈信號的其中之一轉換成為一原始三角波信號,其中輸入時脈信號具有相同之頻率與彼此相異之相位。數位波形調變器依照一輸入控制信號調整原始三角波信號之波形,來產生一調變三角波信號與相應於調變三角波信號之一第一方波信號。三角調變器電性連接至數位波形調變器,三角波調變器係用以累加調變三角波信號之數值來產生一第二方波信號。選擇器依據第二方波信號與第一方波信號之電壓準位,選擇輸入時脈信號的其中之一作為一輸出時脈信號,其中輸出時脈信號之一平均頻率與輸入時脈信號之頻率相異。According to an embodiment of the invention, the spread spectrum clock generator includes a triangular wave generator, a digital waveform modulator, a triangular modulator, and a selector. The triangular wave generator converts one of the plurality of input clock signals into an original triangular wave signal, wherein the input clock signals have the same frequency and different phases from each other. The digital waveform modulator adjusts the waveform of the original triangular wave signal according to an input control signal to generate a modulated triangular wave signal and a first square wave signal corresponding to one of the modulated triangular wave signals. The triangular modulator is electrically connected to the digital waveform modulator, and the triangular wave modulator is used to accumulate the value of the modulated triangular wave signal to generate a second square wave signal. The selector selects one of the input clock signals as an output clock signal according to the voltage level of the second square wave signal and the first square wave signal, wherein the average frequency of one of the output clock signals and the input clock signal The frequency is different.

因此,本發明之一態樣是在提供一種展頻時脈系統,可連續且彈性地調整時脈信號的頻率。Accordingly, one aspect of the present invention is to provide a spread spectrum clock system that continuously and elastically adjusts the frequency of a clock signal.

依據本發明另一實施例,展頻時脈系統含有一振盪器、一鎖相迴路、一三角波產生器、一數位波形調變器、一三角調變器以及一選擇器。振盪器產生一週期信號,鎖相迴路調變週期信號之頻率,來產生複數個輸入時脈信號,其中輸入時脈信號具有相同的頻率以及彼此相異的相位。三角波產生器將複數個輸入時脈信號的其中之一轉換成為一原始三角波信號。數位波形調變器依照一輸入控制信號調整原始三角波信號之波形,來產生一調變三角波信號與相應於調變三角波信號之一第一方波信號。三角調變器電性連接至數位波形調變器,此三角波調變器係用以累加調變三角波信號之數值來產生一第二方波信號。選擇器依據第二方波信號與第一方波信號之電壓準位,選擇輸入時脈信號的其中之一作為一輸出時脈信號,其中輸出時脈信號之一平均頻率與輸入時脈信號之頻率相異。According to another embodiment of the present invention, the spread spectrum clock system includes an oscillator, a phase locked loop, a triangular wave generator, a digital waveform modulator, a triangular modulator, and a selector. The oscillator generates a periodic signal, and the phase locked loop modulates the frequency of the periodic signal to generate a plurality of input clock signals, wherein the input clock signals have the same frequency and different phases from each other. The triangular wave generator converts one of the plurality of input clock signals into an original triangular wave signal. The digital waveform modulator adjusts the waveform of the original triangular wave signal according to an input control signal to generate a modulated triangular wave signal and a first square wave signal corresponding to one of the modulated triangular wave signals. The triangular modulator is electrically connected to the digital waveform modulator, and the triangular wave modulator is configured to accumulate the value of the modulated triangular wave signal to generate a second square wave signal. The selector selects one of the input clock signals as an output clock signal according to the voltage level of the second square wave signal and the first square wave signal, wherein the average frequency of one of the output clock signals and the input clock signal The frequency is different.

以上實施例的展頻時脈產生器與展頻時脈系統,能夠彈性地調整時脈信號的頻率,以妥切地降低電磁干擾效應並與時脈抖動現象。The spread spectrum clock generator and the spread spectrum clock system of the above embodiments can flexibly adjust the frequency of the clock signal to properly reduce the electromagnetic interference effect and the clock jitter phenomenon.

請同時參照第1圖以及第2A圖至第2D圖,其係繪示本發明一實施方式展頻時脈系統之方塊圖與信號波形圖,其中第2A圖係繪示輸入時脈信號201d、201e、201f,第2D圖則繪示輸出時脈信號207a、207b與207c的時間與頻率關係。Referring to FIG. 1 and FIG. 2A to FIG. 2D, FIG. 2 is a block diagram and a signal waveform diagram of a spread spectrum clock system according to an embodiment of the present invention, wherein FIG. 2A shows an input clock signal 201d, 201e, 201f, and 2D are diagrams showing the time-frequency relationship of the output clock signals 207a, 207b, and 207c.

展頻時脈系統115含有振盪器113、鎖相迴路111(Phase locked loop)與展頻時脈產生器101。振盪器113產生週期信號S1。鎖相迴路111調變週期信號S1之頻率/相位來產生數個輸入時脈信號S5(也就是第2A圖所繪示的輸入時脈信號201d、201e與201f),其中這些輸入時脈信號S5具有相同的頻率以及彼此相異的相位。The spread spectrum clock system 115 includes an oscillator 113, a phase locked loop 111 (Phase locked loop), and a spread spectrum clock generator 101. The oscillator 113 generates a periodic signal S1. The phase-locked loop 111 modulates the frequency/phase of the periodic signal S1 to generate a plurality of input clock signals S5 (that is, the input clock signals 201d, 201e, and 201f shown in FIG. 2A), wherein the input clock signals S5 Have the same frequency and different phases from each other.

展頻時脈產生器101執行選擇的動作選出輸入時脈信號S5的其中之一,來產生輸出時脈信號S7(也就是第2D圖當中的輸出時脈信號207a、207b或207c),這些輸入時脈信號S5具有相同的頻率與彼此相異的相位,輸出時脈信號S7的瞬時頻率則會隨著時間而變化。舉例來說,在不同的時間點上,輸出時脈信號S7的瞬時頻率可分別為210 MHz、211 MHz與209MHz,如第2D圖的207b所繪示。The spread spectrum clock generator 101 performs a selected action to select one of the input clock signals S5 to generate an output clock signal S7 (that is, an output clock signal 207a, 207b or 207c in the 2D map), these inputs. The clock signal S5 has the same frequency and a phase different from each other, and the instantaneous frequency of the output clock signal S7 changes with time. For example, at different points in time, the instantaneous frequency of the output clock signal S7 can be 210 MHz, 211 MHz, and 209 MHz, respectively, as depicted by 207b in Figure 2D.

展頻時脈產生器101內含三角波產生器103、數位波形調變器105、三角調變器(Sigma delta modulator)107以及選擇器109。第2B圖係繪示原始三角波信號203a與兩調變三角波信號203b、203c的波形,第2C圖則繪示具有各種工作週期(Duty cycle)的方波信號205a、205b與205c,這些方波信號分別對應至原始三角波信號203a與兩調變三角波信號203b、203c。三角波產生器103將數個輸入時脈信號S5的其中之一轉換成為原始三角波信號S3(也就是第2B圖的203a)。The spread spectrum clock generator 101 includes a triangular wave generator 103, a digital waveform modulator 105, a Sigma delta modulator 107, and a selector 109. 2B is a waveform diagram of the original triangular wave signal 203a and the two modulated triangular wave signals 203b, 203c, and FIG. 2C is a schematic diagram showing square wave signals 205a, 205b and 205c having various duty cycles (Duty cycle). Corresponding to the original triangular wave signal 203a and the two modulated triangular wave signals 203b, 203c, respectively. The triangular wave generator 103 converts one of the plurality of input clock signals S5 into the original triangular wave signal S3 (that is, 203a of FIG. 2B).

數位波形調變器105依照使用者所調整的輸入控制信號CS,調整原始三角波信號S3(也就是第2B圖的203a)之波形來產生調變三角波信號S4、相應於調變三角波信號的第一方波信號S2(也就是第2C圖的205b或205c)。倘若當前所選中的輸入時脈信號須要被改變,選擇器109可以第一方波信號S2為索引(Index),來選擇具有特定相位(也就是領先相位Leading phase或是落後相位lagging phase)的輸入時脈信號S5。舉例來說,使用者可先依照當前輸出時脈信號的平均頻率與展頻量,調整輸入控制信號CS,之後再由數位波形調變器105依據調整後的輸入控制信號CS,調整原始三角波信號S3(也就是第2B圖的203a)的頻率及/或振幅,來產生調變三角波信號S4(第2B圖的203c)與第一方波信號S2(第2C圖的205c)。The digital waveform modulator 105 adjusts the waveform of the original triangular wave signal S3 (that is, 203a of FIG. 2B) according to the input control signal CS adjusted by the user to generate the modulated triangular wave signal S4, corresponding to the first of the modulated triangular wave signals. Square wave signal S2 (that is, 205b or 205c of Figure 2C). If the currently selected input clock signal needs to be changed, the selector 109 can select the specific phase (ie, the leading phase or the lagging phase) by using the first square wave signal S2 as an index. Enter the clock signal S5. For example, the user may first adjust the input control signal CS according to the average frequency and the spread frequency of the current output clock signal, and then adjust the original triangular wave signal according to the adjusted input control signal CS by the digital waveform modulator 105. The frequency and/or the amplitude of S3 (that is, 203a of FIG. 2B) generates a modulated triangular wave signal S4 (203c in FIG. 2B) and a first square wave signal S2 (205c in FIG. 2C).

三角調變器107電性連接至數位波形調變器105,此三角調變器107係累加調變三角波信號S4之數值,來產生數值為邏輯1或邏輯0的第二方波信號S6。選擇器109可以第二方波信號S6為索引,來決定是否需要調變目前的輸入時脈信號。在此一實施例當中,回授後的輸出時脈信號S7會觸發三角調變器107來產生第二方波信號S6。The triangular modulator 107 is electrically connected to the digital waveform modulator 105. The triangular modulator 107 accumulates the value of the modulated triangular wave signal S4 to generate a second square wave signal S6 having a value of logic 1 or logic 0. The selector 109 can use the second square wave signal S6 as an index to determine whether the current input clock signal needs to be modulated. In this embodiment, the feedback output clock signal S7 triggers the triangular modulator 107 to generate the second square wave signal S6.

選擇器109依據所接收到的第二方波信號S6與第一方波信號S2的電壓準位,選擇輸入時脈信號S5的其中之一,作為輸出時脈信號S7。The selector 109 selects one of the input clock signals S5 as the output clock signal S7 according to the received second square wave signal S6 and the voltage level of the first square wave signal S2.

以下表一顯示了選擇器109的運作,並顯示第一方波信號S2、第二方波信號S6(三角調變器107所輸出),以及被選擇的輸入時脈信號S5三個信號之間的關係。根據表一,選擇器109會依照第一方波信號S2與第二方波信號S6來選擇輸入時脈信號S5的其中之一。更詳細地說,可先依據第二方波信號S6來決定是否需要調變目前所選擇的輸入時脈信號S5。倘若第二方波信號S6顯示需要調變當前已選中的輸入時脈信號S5(也就是表一的狀態2與狀態4),接著就可依據第一方波信號S2來決定要選擇前一輸入時脈信號201d(落後相位)或是後一輸入時脈信號201f(領先相位)作為往後的輸出時脈信號S7。Table 1 below shows the operation of the selector 109, and displays the first square wave signal S2, the second square wave signal S6 (output by the triangular modulator 107), and the selected input clock signal S5 between the three signals. Relationship. According to Table 1, the selector 109 selects one of the input clock signals S5 according to the first square wave signal S2 and the second square wave signal S6. In more detail, whether the currently selected input clock signal S5 needs to be modulated may be determined according to the second square wave signal S6. If the second square wave signal S6 indicates that the currently selected input clock signal S5 needs to be modulated (that is, state 2 and state 4 of Table 1), then the first square wave signal S2 can be used to decide to select the previous one. The clock signal 201d (backward phase) or the subsequent input clock signal 201f (leading phase) is input as the subsequent output clock signal S7.

舉例來說,若當前所選擇的輸入時脈信號為201e且第二方波信號S6為邏輯1,那麼選擇器109就會依據第一方波信號S2的邏輯準位,重新選擇輸入時脈信號S5的其中之一,來取代當前所選中的輸入時脈信號201e。在此情況當中,若第一方波信號S2為邏輯0則會選擇輸入時脈信號201d,若第一方波信號S2為邏輯1則會選擇輸入時脈信號201f。此外,當第二方波信號S6為邏輯0(也就是表一當中的狀態1與3),則選擇器109會維持當前已選中的輸入時脈信號201e,作為輸出時脈信號S7。For example, if the currently selected input clock signal is 201e and the second square wave signal S6 is logic 1, the selector 109 reselects the input clock signal according to the logic level of the first square wave signal S2. One of S5, in place of the currently selected input clock signal 201e. In this case, if the first square wave signal S2 is logic 0, the input clock signal 201d is selected, and if the first square wave signal S2 is logic 1, the input clock signal 201f is selected. In addition, when the second square wave signal S6 is logic 0 (that is, states 1 and 3 in Table 1), the selector 109 maintains the currently selected input clock signal 201e as the output clock signal S7.

若所選擇的輸入時脈信號產生變化,會改變輸出時脈信號S7的週期(Period/cycle)(也就是說,輸出時脈信號S7的頻率會發生變化)。輸出時脈信號S7的平均頻率可相同或是相異於輸入時脈信號S5的頻率,頻率相同或是相異端視輸入控制信號CS來決定。舉例來說,倘若輸入時脈信號S5的頻率為200 MHz,則可利用輸入控制信號CS來將輸出時脈信號的平均頻率調整為210 MHz(也就是將第2B圖當中原始三角波信號203a調整至調變三角波信號203b)。在此範例當中,輸出時脈信號S7的頻率不是輸入時脈信號S5頻率的倍數。在其他例子當中,若輸入控制信號CS使原始三角波信號203a保持不變,則輸出時脈信號S7的平均頻率會等於輸入時脈信號S5的頻率;此外,若三角調變器107尚未被回授後的輸出時脈信號S7觸發,輸出時脈信號S7的平均頻率會等於輸入時脈信號S5的頻率。因此數位波形調變器105的確可彈性地調整輸出時脈信號S7的展頻量。If the selected input clock signal changes, the period of the output clock signal S7 (Period/cycle) is changed (that is, the frequency of the output clock signal S7 changes). The average frequency of the output clock signal S7 may be the same or different from the frequency of the input clock signal S5, the frequency is the same or the difference is determined by the input control signal CS. For example, if the frequency of the input clock signal S5 is 200 MHz, the input control signal CS can be used to adjust the average frequency of the output clock signal to 210 MHz (that is, the original triangular wave signal 203a in FIG. 2B is adjusted to Modulated triangular wave signal 203b). In this example, the frequency of the output clock signal S7 is not a multiple of the frequency of the input clock signal S5. In other examples, if the input control signal CS keeps the original triangular wave signal 203a unchanged, the average frequency of the output clock signal S7 will be equal to the frequency of the input clock signal S5; in addition, if the triangular modulator 107 has not been fed back The subsequent output clock signal S7 is triggered, and the average frequency of the output clock signal S7 is equal to the frequency of the input clock signal S5. Therefore, the digital waveform modulator 105 can elastically adjust the spread amount of the output clock signal S7.

結果如第2D圖所繪示,輸出時脈信號的頻率/時間曲線207b的平均頻率為210 MHz,頻率/時間曲線207c(S7)的平均頻率為190 MHz,此兩平均頻率均與輸入時脈信號的頻率200MHz存在些微差距。As a result, as shown in Fig. 2D, the average frequency of the frequency/time curve 207b of the output clock signal is 210 MHz, and the average frequency of the frequency/time curve 207c (S7) is 190 MHz, both of which are input clocks. There is a slight difference in the frequency of the signal at 200MHz.

根據上述實施例,輸出時脈信號的平均頻率可與輸入時脈信號的頻率相同,或可略與輸入時脈信號的頻率不同而非輸入時脈信號頻率的倍數,因此可更彈性地展開輸出時脈信號的頻率。According to the above embodiment, the average frequency of the output clock signal can be the same as the frequency of the input clock signal, or can be slightly different from the frequency of the input clock signal instead of the multiple of the input clock signal frequency, so that the output can be expanded more flexibly. The frequency of the clock signal.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何在本發明所屬技術領域中具有通常知識者者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

101...展頻時脈產生器101. . . Spread spectrum clock generator

103...三角波產生器103. . . Triangle wave generator

105...數位波形調變器105. . . Digital waveform modulator

107...三角調變器107. . . Triangular modulator

109...選擇器109. . . Selector

111...鎖相迴路111. . . Phase-locked loop

113...振盪器113. . . Oscillator

115...展頻時脈系統115. . . Spread spectrum clock system

201d...輸入時脈信號201d. . . Input clock signal

201e...輸入時脈信號201e. . . Input clock signal

201f...輸入時脈信號201f. . . Input clock signal

203a...原始三角波信號203a. . . Original triangular wave signal

203b...調變三角波信號203b. . . Modulated triangular wave signal

203c...調變三角波信號203c. . . Modulated triangular wave signal

205a...方波信號205a. . . Square wave signal

205b...方波信號205b. . . Square wave signal

205c...方波信號205c. . . Square wave signal

207a...頻率/時間曲線207a. . . Frequency/time curve

207b...頻率/時間曲線207b. . . Frequency/time curve

207c...頻率/時間曲線207c. . . Frequency/time curve

S1...週期信號S1. . . Periodic signal

S2...第一方波信號S2. . . First square wave signal

S3...原始三角波信號S3. . . Original triangular wave signal

S4...調變三角波信號S4. . . Modulated triangular wave signal

S5...輸入時脈信號S5. . . Input clock signal

S6...第二方波信號S6. . . Second square wave signal

S7...輸出時脈信號S7. . . Output clock signal

為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

第1圖係繪示本發明一實施方式展頻時脈系統之方塊圖。1 is a block diagram showing a spread spectrum clock system according to an embodiment of the present invention.

第2A圖至第2D圖係繪示本發明一實施方式展頻時脈系統之信號波形圖。2A to 2D are diagrams showing signal waveforms of a spread spectrum clock system according to an embodiment of the present invention.

101...展頻時脈產生器101. . . Spread spectrum clock generator

103...三角波產生器103. . . Triangle wave generator

105...數位波形調變器105. . . Digital waveform modulator

107...三角調變器107. . . Triangular modulator

109...選擇器109. . . Selector

111...鎖相迴路111. . . Phase-locked loop

113...振盪器113. . . Oscillator

115...展頻時脈系統115. . . Spread spectrum clock system

S1...週期信號S1. . . Periodic signal

S2...第一方波信號S2. . . First square wave signal

S3...原始三角波信號S3. . . Original triangular wave signal

S4...調變三角波信號S4. . . Modulated triangular wave signal

S5...輸入時脈信號S5. . . Input clock signal

S6...第二方波信號S6. . . Second square wave signal

S7...輸出時脈信號S7. . . Output clock signal

Claims (10)

一種展頻時脈產生器,包含:一三角波產生器,以將複數個輸入時脈信號的其中之一轉換成為一原始三角波信號,其中該些輸入時脈信號具有相同之頻率與彼此相異之相位;一數位波形調變器,以依照一輸入控制信號調整該原始三角波信號之波形,來產生一調變三角波信號與相應於該調變三角波信號之一第一方波信號;一三角調變器,電性連接至該數位波形調變器,該三角調變器係用以累加該調變三角波信號之數值來產生一第二方波信號;以及一選擇器,以依據該第二方波信號與該第一方波信號之電壓準位,選擇該些輸入時脈信號的其中之一作為一輸出時脈信號,其中該輸出時脈信號之一平均頻率與該輸入時脈信號之頻率相異。A spread spectrum clock generator includes: a triangular wave generator for converting one of a plurality of input clock signals into an original triangular wave signal, wherein the input clock signals have the same frequency and are different from each other a digital waveform modulator for adjusting a waveform of the original triangular wave signal according to an input control signal to generate a modulated triangular wave signal and a first square wave signal corresponding to the modulated triangular wave signal; Electrically connected to the digital waveform modulator for accumulating the value of the modulated triangular wave signal to generate a second square wave signal; and a selector for relying on the second square wave Selecting one of the input clock signals as an output clock signal, wherein the signal and the voltage level of the first square wave signal are an output clock signal, wherein an average frequency of the output clock signal is proportional to a frequency of the input clock signal different. 如請求項1所述之展頻時脈產生器,其中該數位波形調變器係進一步調整該原始三角波信號之頻率,來產生該調變三角波信號。The spread spectrum clock generator of claim 1, wherein the digital waveform modulator further adjusts a frequency of the original triangular wave signal to generate the modulated triangular wave signal. 如請求項1所述之展頻時脈產生器,其中該數位波形調變器係進一步調整該原始三角波信號之振幅,來產生該調變三角波信號。The spread spectrum clock generator of claim 1, wherein the digital waveform modulator further adjusts an amplitude of the original triangular wave signal to generate the modulated triangular wave signal. 如請求項1所述之展頻時脈產生器,其中該輸出時脈信號係回授至該三角調變器,以觸發該三角調變器來產生該第二方波信號。The spread spectrum clock generator of claim 1, wherein the output clock signal is fed back to the triangular modulator to trigger the triangular modulator to generate the second square wave signal. 如請求項4所述之展頻時脈產生器,其中當該三角調變器尚未被觸發之前,該輸出時脈信號之平均頻率會等於該輸入時脈信號之頻率。The spread spectrum clock generator of claim 4, wherein an average frequency of the output clock signal is equal to a frequency of the input clock signal before the triangular modulator has been triggered. 一種展頻時脈系統,包含:一振盪器,以產生一週期信號;一鎖相迴路,以調變該週期信號之頻率,來產生複數個輸入時脈信號,其中該些輸入時脈信號具有相同的頻率以及相異的相位;一三角波產生器,以將該些輸入時脈信號的其中之一轉換成為一原始三角波信號;一數位波形調變器,以依照一輸入控制信號調整該原始三角波信號之波形,來產生一調變三角波信號與相應於該調變三角波信號之一第一方波信號;一三角調變器,電性連接至該數位波形調變器,該三角波調變器係用以累加該調變三角波信號之數值來產生一第二方波信號;以及一選擇器,以依據該第二方波信號與該第一方波信號之電壓準位,選擇該些輸入時脈信號的其中之一作為一輸出時脈信號,其中該輸出時脈信號之一平均頻率與該輸入時脈信號之頻率相異。A spread spectrum clock system comprising: an oscillator to generate a periodic signal; a phase locked loop to modulate a frequency of the periodic signal to generate a plurality of input clock signals, wherein the input clock signals have a same frequency and a different phase; a triangular wave generator for converting one of the input clock signals into an original triangular wave signal; a digital waveform modulator for adjusting the original triangular wave according to an input control signal a waveform of the signal to generate a modulated triangular wave signal and a first square wave signal corresponding to one of the modulated triangular wave signals; a triangular modulator electrically connected to the digital waveform modulator, the triangular wave modulator system Generating a second square wave signal by accumulating the value of the modulated triangular wave signal; and selecting a selector to select the input clock according to the voltage level of the second square wave signal and the first square wave signal One of the signals acts as an output clock signal, wherein an average frequency of one of the output clock signals is different from the frequency of the input clock signal. 如請求項6所述之展頻時脈系統,其中該數位波形調變器係進一步調整該原始三角波信號之頻率,來產生該調變三角波信號。The spread spectrum clock system of claim 6, wherein the digital waveform modulator further adjusts a frequency of the original triangular wave signal to generate the modulated triangular wave signal. 如請求項6所述之展頻時脈系統,其中該數位波形調變器係進一步調整該原始三角波信號之振幅,來產生該調變三角波信號。The spread spectrum clock system of claim 6, wherein the digital waveform modulator further adjusts an amplitude of the original triangular wave signal to generate the modulated triangular wave signal. 如請求項6所述之展頻時脈系統,其中該輸出時脈信號係回授至該三角調變器,以觸發該三角調變器來產生該第二方波信號。The spread spectrum clock system of claim 6, wherein the output clock signal is fed back to the triangular modulator to trigger the triangular modulator to generate the second square wave signal. 如請求項9所述之展頻時脈系統,其中當該三角調變器尚未被觸發之前,該輸出時脈信號之平均頻率會等於該輸入時脈信號之頻率。The spread spectrum clock system of claim 9, wherein the average frequency of the output clock signal is equal to the frequency of the input clock signal before the triangular modulator has been triggered.
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